mga_reg.h revision eda3803b
1fe5e51b7Smrg/* $XConsortium: mgareg.h /main/2 1996/10/25 10:33:21 kaleb $ */
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5fe5e51b7Smrg/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/mga/mga_reg.h,v 1.18 2001/09/26 12:59:18 alanh Exp $ */
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9fe5e51b7Smrg/*
10fe5e51b7Smrg * MGA Millennium (MGA2064W) functions
11fe5e51b7Smrg * MGA Mystique (MGA1064SG) functions
12fe5e51b7Smrg *
13fe5e51b7Smrg * Copyright 1996 The XFree86 Project, Inc.
14fe5e51b7Smrg *
15fe5e51b7Smrg * Authors
16fe5e51b7Smrg *		Dirk Hohndel
17fe5e51b7Smrg *			hohndel@XFree86.Org
18fe5e51b7Smrg *		David Dawes
19fe5e51b7Smrg *			dawes@XFree86.Org
20fe5e51b7Smrg * Contributors:
21fe5e51b7Smrg *		Guy DESBIEF, Aix-en-provence, France
22fe5e51b7Smrg *			g.desbief@aix.pacwan.net
23fe5e51b7Smrg *		MGA1064SG Mystique register file
24fe5e51b7Smrg */
25fe5e51b7Smrg
26fe5e51b7Smrg
27fe5e51b7Smrg#ifndef _MGA_REG_H_
28fe5e51b7Smrg#define _MGA_REG_H_
29fe5e51b7Smrg
30fe5e51b7Smrg#define	MGAREG_DWGCTL		0x1c00
31fe5e51b7Smrg#define	MGAREG_MACCESS		0x1c04
32fe5e51b7Smrg/* the following is a mystique only register */
33fe5e51b7Smrg#define MGAREG_MCTLWTST		0x1c08
34fe5e51b7Smrg#define	MGAREG_ZORG		0x1c0c
35fe5e51b7Smrg
36fe5e51b7Smrg#define	MGAREG_PAT0		0x1c10
37fe5e51b7Smrg#define	MGAREG_PAT1		0x1c14
38fe5e51b7Smrg#define	MGAREG_PLNWT		0x1c1c
39fe5e51b7Smrg
40fe5e51b7Smrg#define	MGAREG_BCOL		0x1c20
41fe5e51b7Smrg#define	MGAREG_FCOL		0x1c24
42fe5e51b7Smrg
43fe5e51b7Smrg#define	MGAREG_SRC0		0x1c30
44fe5e51b7Smrg#define	MGAREG_SRC1		0x1c34
45fe5e51b7Smrg#define	MGAREG_SRC2		0x1c38
46fe5e51b7Smrg#define	MGAREG_SRC3		0x1c3c
47fe5e51b7Smrg
48fe5e51b7Smrg#define	MGAREG_XYSTRT		0x1c40
49fe5e51b7Smrg#define	MGAREG_XYEND		0x1c44
50fe5e51b7Smrg
51fe5e51b7Smrg#define	MGAREG_SHIFT		0x1c50
52fe5e51b7Smrg/* the following is a mystique only register */
53fe5e51b7Smrg#define MGAREG_DMAPAD		0x1c54
54fe5e51b7Smrg#define	MGAREG_SGN		0x1c58
55fe5e51b7Smrg#define	MGAREG_LEN		0x1c5c
56fe5e51b7Smrg
57fe5e51b7Smrg#define	MGAREG_AR0		0x1c60
58fe5e51b7Smrg#define	MGAREG_AR1		0x1c64
59fe5e51b7Smrg#define	MGAREG_AR2		0x1c68
60fe5e51b7Smrg#define	MGAREG_AR3		0x1c6c
61fe5e51b7Smrg#define	MGAREG_AR4		0x1c70
62fe5e51b7Smrg#define	MGAREG_AR5		0x1c74
63fe5e51b7Smrg#define	MGAREG_AR6		0x1c78
64fe5e51b7Smrg
65fe5e51b7Smrg#define	MGAREG_CXBNDRY		0x1c80
66fe5e51b7Smrg#define	MGAREG_FXBNDRY		0x1c84
67fe5e51b7Smrg#define	MGAREG_YDSTLEN		0x1c88
68fe5e51b7Smrg#define	MGAREG_PITCH		0x1c8c
69fe5e51b7Smrg
70fe5e51b7Smrg#define	MGAREG_YDST		0x1c90
71fe5e51b7Smrg#define	MGAREG_YDSTORG		0x1c94
72fe5e51b7Smrg#define	MGAREG_YTOP		0x1c98
73fe5e51b7Smrg#define	MGAREG_YBOT		0x1c9c
74fe5e51b7Smrg
75fe5e51b7Smrg#define	MGAREG_CXLEFT		0x1ca0
76fe5e51b7Smrg#define	MGAREG_CXRIGHT		0x1ca4
77fe5e51b7Smrg#define	MGAREG_FXLEFT		0x1ca8
78fe5e51b7Smrg#define	MGAREG_FXRIGHT		0x1cac
79fe5e51b7Smrg
80fe5e51b7Smrg#define	MGAREG_XDST		0x1cb0
81fe5e51b7Smrg
82fe5e51b7Smrg#define	MGAREG_DR0		0x1cc0
83fe5e51b7Smrg#define	MGAREG_DR1		0x1cc4
84fe5e51b7Smrg#define	MGAREG_DR2		0x1cc8
85fe5e51b7Smrg#define	MGAREG_DR3		0x1ccc
86fe5e51b7Smrg
87fe5e51b7Smrg#define	MGAREG_DR4		0x1cd0
88fe5e51b7Smrg#define	MGAREG_DR5		0x1cd4
89fe5e51b7Smrg#define	MGAREG_DR6		0x1cd8
90fe5e51b7Smrg#define	MGAREG_DR7		0x1cdc
91fe5e51b7Smrg
92fe5e51b7Smrg#define	MGAREG_DR8		0x1ce0
93fe5e51b7Smrg#define	MGAREG_DR9		0x1ce4
94fe5e51b7Smrg#define	MGAREG_DR10		0x1ce8
95fe5e51b7Smrg#define	MGAREG_DR11		0x1cec
96fe5e51b7Smrg
97fe5e51b7Smrg#define	MGAREG_DR12		0x1cf0
98fe5e51b7Smrg#define	MGAREG_DR13		0x1cf4
99fe5e51b7Smrg#define	MGAREG_DR14		0x1cf8
100fe5e51b7Smrg#define	MGAREG_DR15		0x1cfc
101fe5e51b7Smrg
102fe5e51b7Smrg#define MGAREG_SRCORG		0x2cb4
103fe5e51b7Smrg#define MGAREG_DSTORG		0x2cb8
104fe5e51b7Smrg
105fe5e51b7Smrg/* add or or this to one of the previous "power registers" to start
106fe5e51b7Smrg   the drawing engine */
107fe5e51b7Smrg
108fe5e51b7Smrg#define MGAREG_EXEC		0x0100
109fe5e51b7Smrg
110fe5e51b7Smrg#define	MGAREG_FIFOSTATUS	0x1e10
111fe5e51b7Smrg#define	MGAREG_Status		0x1e14
112fe5e51b7Smrg#define MGAREG_CACHEFLUSH       0x1fff
113fe5e51b7Smrg#define	MGAREG_ICLEAR		0x1e18
114fe5e51b7Smrg#define	MGAREG_IEN		0x1e1c
115fe5e51b7Smrg
116fe5e51b7Smrg#define	MGAREG_VCOUNT		0x1e20
117fe5e51b7Smrg
118fe5e51b7Smrg#define	MGAREG_Reset		0x1e40
119fe5e51b7Smrg
120fe5e51b7Smrg#define	MGAREG_OPMODE		0x1e54
121fe5e51b7Smrg
122fe5e51b7Smrg/* Warp Registers */
123fe5e51b7Smrg#define MGAREG_WIADDR           0x1dc0
124fe5e51b7Smrg#define MGAREG_WIADDR2          0x1dd8
125fe5e51b7Smrg#define MGAREG_WGETMSB          0x1dc8
126fe5e51b7Smrg#define MGAREG_WVRTXSZ          0x1dcc
127fe5e51b7Smrg#define MGAREG_WACCEPTSEQ       0x1dd4
128fe5e51b7Smrg#define MGAREG_WMISC            0x1e70
129fe5e51b7Smrg
130fe5e51b7Smrg/* OPMODE register additives */
131fe5e51b7Smrg
132fe5e51b7Smrg#define MGAOPM_DMA_GENERAL	(0x00 << 2)
133fe5e51b7Smrg#define MGAOPM_DMA_BLIT		(0x01 << 2)
134fe5e51b7Smrg#define MGAOPM_DMA_VECTOR	(0x10 << 2)
135fe5e51b7Smrg
136fe5e51b7Smrg/* MACCESS register additives */
137fe5e51b7Smrg#define MGAMAC_PW8               0x00
138fe5e51b7Smrg#define MGAMAC_PW16              0x01
139fe5e51b7Smrg#define MGAMAC_PW24              0x03 /* not a typo */
140fe5e51b7Smrg#define MGAMAC_PW32              0x02 /* not a typo */
141fe5e51b7Smrg#define MGAMAC_BYPASS332         0x10000000
142fe5e51b7Smrg#define MGAMAC_NODITHER          0x40000000
143fe5e51b7Smrg#define MGAMAC_DIT555            0x80000000
144fe5e51b7Smrg
145fe5e51b7Smrg/* DWGCTL register additives */
146fe5e51b7Smrg
147fe5e51b7Smrg/* Lines */
148fe5e51b7Smrg
149fe5e51b7Smrg#define MGADWG_LINE_OPEN	0x00
150fe5e51b7Smrg#define MGADWG_AUTOLINE_OPEN	0x01
151fe5e51b7Smrg#define MGADWG_LINE_CLOSE	0x02
152fe5e51b7Smrg#define MGADWG_AUTOLINE_CLOSE	0x03
153fe5e51b7Smrg
154fe5e51b7Smrg/* Trapezoids */
155fe5e51b7Smrg#define MGADWG_TRAP		0x04
156fe5e51b7Smrg#define MGADWG_TEXTURE_TRAP	0x06
157fe5e51b7Smrg
158fe5e51b7Smrg/* BitBlts */
159fe5e51b7Smrg
160fe5e51b7Smrg#define MGADWG_BITBLT		0x08
161fe5e51b7Smrg#define MGADWG_FBITBLT		0x0c
162fe5e51b7Smrg#define MGADWG_ILOAD		0x09
163fe5e51b7Smrg#define MGADWG_ILOAD_SCALE	0x0d
164fe5e51b7Smrg#define MGADWG_ILOAD_FILTER	0x0f
165fe5e51b7Smrg#define MGADWG_ILOAD_HIQH	0x07
166fe5e51b7Smrg#define MGADWG_ILOAD_HIQHV	0x0e
167fe5e51b7Smrg#define MGADWG_IDUMP		0x0a
168fe5e51b7Smrg
169fe5e51b7Smrg/* atype access to WRAM */
170fe5e51b7Smrg
171fe5e51b7Smrg#define MGADWG_RPL		( 0x00 << 4 )
172fe5e51b7Smrg#define MGADWG_RSTR		( 0x01 << 4 )
173fe5e51b7Smrg#define MGADWG_ZI		( 0x03 << 4 )
174fe5e51b7Smrg#define MGADWG_BLK 		( 0x04 << 4 )
175fe5e51b7Smrg#define MGADWG_I		( 0x07 << 4 )
176fe5e51b7Smrg
177fe5e51b7Smrg/* specifies whether bit blits are linear or xy */
178fe5e51b7Smrg#define MGADWG_LINEAR		( 0x01 << 7 )
179fe5e51b7Smrg
180fe5e51b7Smrg/* z drawing mode. use MGADWG_NOZCMP for always */
181fe5e51b7Smrg
182fe5e51b7Smrg#define MGADWG_NOZCMP		( 0x00 << 8 )
183fe5e51b7Smrg#define MGADWG_ZE		( 0x02 << 8 )
184fe5e51b7Smrg#define MGADWG_ZNE		( 0x03 << 8 )
185fe5e51b7Smrg#define MGADWG_ZLT		( 0x04 << 8 )
186fe5e51b7Smrg#define MGADWG_ZLTE		( 0x05 << 8 )
187fe5e51b7Smrg#define MGADWG_GT		( 0x06 << 8 )
188fe5e51b7Smrg#define MGADWG_GTE		( 0x07 << 8 )
189fe5e51b7Smrg
190fe5e51b7Smrg/* use this to force colour expansion circuitry to do its stuff */
191fe5e51b7Smrg
192fe5e51b7Smrg#define MGADWG_SOLID		( 0x01 << 11 )
193fe5e51b7Smrg
194fe5e51b7Smrg/* ar register at zero */
195fe5e51b7Smrg
196fe5e51b7Smrg#define MGADWG_ARZERO		( 0x01 << 12 )
197fe5e51b7Smrg
198fe5e51b7Smrg#define MGADWG_SGNZERO		( 0x01 << 13 )
199fe5e51b7Smrg
200fe5e51b7Smrg#define MGADWG_SHIFTZERO	( 0x01 << 14 )
201fe5e51b7Smrg
202fe5e51b7Smrg/* See table on 4-43 for bop ALU operations */
203fe5e51b7Smrg
204fe5e51b7Smrg/* See table on 4-44 for translucidity masks */
205fe5e51b7Smrg
206fe5e51b7Smrg#define MGADWG_BMONOLEF		( 0x00 << 25 )
207fe5e51b7Smrg#define MGADWG_BMONOWF		( 0x04 << 25 )
208fe5e51b7Smrg#define MGADWG_BPLAN		( 0x01 << 25 )
209fe5e51b7Smrg
210fe5e51b7Smrg/* note that if bfcol is specified and you're doing a bitblt, it causes
211fe5e51b7Smrg   a fbitblt to be performed, so check that you obey the fbitblt rules */
212fe5e51b7Smrg
213fe5e51b7Smrg#define MGADWG_BFCOL   		( 0x02 << 25 )
214fe5e51b7Smrg#define MGADWG_BUYUV		( 0x0e << 25 )
215fe5e51b7Smrg#define MGADWG_BU32BGR		( 0x03 << 25 )
216fe5e51b7Smrg#define MGADWG_BU32RGB		( 0x07 << 25 )
217fe5e51b7Smrg#define MGADWG_BU24BGR		( 0x0b << 25 )
218fe5e51b7Smrg#define MGADWG_BU24RGB		( 0x0f << 25 )
219fe5e51b7Smrg
220fe5e51b7Smrg#define MGADWG_PATTERN		( 0x01 << 29 )
221fe5e51b7Smrg#define MGADWG_TRANSC		( 0x01 << 30 )
222fe5e51b7Smrg#define MGAREG_MISC_WRITE	0x3c2
223fe5e51b7Smrg#define MGAREG_MISC_READ	0x3cc
224eda3803bSmrg#define MGAREG_MEM_MISC_WRITE       0x1fc2
225eda3803bSmrg#define MGAREG_MEM_MISC_READ        0x1fcc
226eda3803bSmrg
227fe5e51b7Smrg#define MGAREG_MISC_IOADSEL	(0x1 << 0)
228fe5e51b7Smrg#define MGAREG_MISC_RAMMAPEN	(0x1 << 1)
229fe5e51b7Smrg#define MGAREG_MISC_CLK_SEL_VGA25	(0x0 << 2)
230fe5e51b7Smrg#define MGAREG_MISC_CLK_SEL_VGA28	(0x1 << 2)
231fe5e51b7Smrg#define MGAREG_MISC_CLK_SEL_MGA_PIX	(0x2 << 2)
232fe5e51b7Smrg#define MGAREG_MISC_CLK_SEL_MGA_MSK	(0x3 << 2)
233fe5e51b7Smrg#define MGAREG_MISC_VIDEO_DIS	(0x1 << 4)
234fe5e51b7Smrg#define MGAREG_MISC_HIGH_PG_SEL	(0x1 << 5)
235fe5e51b7Smrg
236fe5e51b7Smrg/* MMIO VGA registers */
237fe5e51b7Smrg#define MGAREG_SEQ_INDEX	0x1fc4
238fe5e51b7Smrg#define MGAREG_SEQ_DATA		0x1fc5
239fe5e51b7Smrg#define MGAREG_CRTC_INDEX	0x1fd4
240fe5e51b7Smrg#define MGAREG_CRTC_DATA	0x1fd5
241fe5e51b7Smrg#define MGAREG_CRTCEXT_INDEX	0x1fde
242fe5e51b7Smrg#define MGAREG_CRTCEXT_DATA	0x1fdf
243fe5e51b7Smrg
244fe5e51b7Smrg
245fe5e51b7Smrg
246fe5e51b7Smrg/* MGA bits for registers PCI_OPTION_REG */
247fe5e51b7Smrg#define MGA1064_OPT_SYS_CLK_PCI   		( 0x00 << 0 )
248fe5e51b7Smrg#define MGA1064_OPT_SYS_CLK_PLL   		( 0x01 << 0 )
249fe5e51b7Smrg#define MGA1064_OPT_SYS_CLK_EXT   		( 0x02 << 0 )
250fe5e51b7Smrg#define MGA1064_OPT_SYS_CLK_MSK   		( 0x03 << 0 )
251fe5e51b7Smrg
252fe5e51b7Smrg#define MGA1064_OPT_SYS_CLK_DIS   		( 0x01 << 2 )
253fe5e51b7Smrg#define MGA1064_OPT_G_CLK_DIV_1   		( 0x01 << 3 )
254fe5e51b7Smrg#define MGA1064_OPT_M_CLK_DIV_1   		( 0x01 << 4 )
255fe5e51b7Smrg
256fe5e51b7Smrg#define MGA1064_OPT_SYS_PLL_PDN   		( 0x01 << 5 )
257fe5e51b7Smrg#define MGA1064_OPT_VGA_ION   		( 0x01 << 8 )
258fe5e51b7Smrg
259fe5e51b7Smrg/* MGA registers in PCI config space */
260fe5e51b7Smrg#define PCI_MGA_INDEX		0x44
261fe5e51b7Smrg#define PCI_MGA_DATA		0x48
262fe5e51b7Smrg#define PCI_MGA_OPTION2		0x50
263fe5e51b7Smrg#define PCI_MGA_OPTION3		0x54
264fe5e51b7Smrg
265fe5e51b7Smrg#define RAMDAC_OFFSET		0x3c00
266fe5e51b7Smrg
267fe5e51b7Smrg/* TVP3026 direct registers */
268fe5e51b7Smrg
269fe5e51b7Smrg#define TVP3026_INDEX		0x00
270fe5e51b7Smrg#define TVP3026_WADR_PAL	0x00
271fe5e51b7Smrg#define TVP3026_COL_PAL		0x01
272fe5e51b7Smrg#define TVP3026_PIX_RD_MSK	0x02
273fe5e51b7Smrg#define TVP3026_RADR_PAL	0x03
274fe5e51b7Smrg#define TVP3026_CUR_COL_ADDR	0x04
275fe5e51b7Smrg#define TVP3026_CUR_COL_DATA	0x05
276fe5e51b7Smrg#define TVP3026_DATA		0x0a
277fe5e51b7Smrg#define TVP3026_CUR_RAM		0x0b
278fe5e51b7Smrg#define TVP3026_CUR_XLOW	0x0c
279fe5e51b7Smrg#define TVP3026_CUR_XHI		0x0d
280fe5e51b7Smrg#define TVP3026_CUR_YLOW	0x0e
281fe5e51b7Smrg#define TVP3026_CUR_YHI		0x0f
282fe5e51b7Smrg
283fe5e51b7Smrg/* TVP3026 indirect registers */
284fe5e51b7Smrg
285fe5e51b7Smrg#define TVP3026_SILICON_REV	0x01
286fe5e51b7Smrg#define TVP3026_CURSOR_CTL	0x06
287fe5e51b7Smrg#define TVP3026_LATCH_CTL	0x0f
288fe5e51b7Smrg#define TVP3026_TRUE_COLOR_CTL	0x18
289fe5e51b7Smrg#define TVP3026_MUX_CTL		0x19
290fe5e51b7Smrg#define TVP3026_CLK_SEL		0x1a
291fe5e51b7Smrg#define TVP3026_PAL_PAGE	0x1c
292fe5e51b7Smrg#define TVP3026_GEN_CTL		0x1d
293fe5e51b7Smrg#define TVP3026_MISC_CTL	0x1e
294fe5e51b7Smrg#define TVP3026_GEN_IO_CTL	0x2a
295fe5e51b7Smrg#define TVP3026_GEN_IO_DATA	0x2b
296fe5e51b7Smrg#define TVP3026_PLL_ADDR	0x2c
297fe5e51b7Smrg#define TVP3026_PIX_CLK_DATA	0x2d
298fe5e51b7Smrg#define TVP3026_MEM_CLK_DATA	0x2e
299fe5e51b7Smrg#define TVP3026_LOAD_CLK_DATA	0x2f
300fe5e51b7Smrg#define TVP3026_KEY_RED_LOW	0x32
301fe5e51b7Smrg#define TVP3026_KEY_RED_HI	0x33
302fe5e51b7Smrg#define TVP3026_KEY_GREEN_LOW	0x34
303fe5e51b7Smrg#define TVP3026_KEY_GREEN_HI	0x35
304fe5e51b7Smrg#define TVP3026_KEY_BLUE_LOW	0x36
305fe5e51b7Smrg#define TVP3026_KEY_BLUE_HI	0x37
306fe5e51b7Smrg#define TVP3026_KEY_CTL		0x38
307fe5e51b7Smrg#define TVP3026_MCLK_CTL	0x39
308fe5e51b7Smrg#define TVP3026_SENSE_TEST	0x3a
309fe5e51b7Smrg#define TVP3026_TEST_DATA	0x3b
310fe5e51b7Smrg#define TVP3026_CRC_LSB		0x3c
311fe5e51b7Smrg#define TVP3026_CRC_MSB		0x3d
312fe5e51b7Smrg#define TVP3026_CRC_CTL		0x3e
313fe5e51b7Smrg#define TVP3026_ID		0x3f
314fe5e51b7Smrg#define TVP3026_RESET		0xff
315fe5e51b7Smrg
316fe5e51b7Smrg
317fe5e51b7Smrg/* MGA1064 DAC Register file */
318fe5e51b7Smrg/* MGA1064 direct registers */
319fe5e51b7Smrg
320fe5e51b7Smrg#define MGA1064_INDEX		0x00
321fe5e51b7Smrg#define MGA1064_WADR_PAL	0x00
322eda3803bSmrg#define MGA1064_SPAREREG        0x00
323fe5e51b7Smrg#define MGA1064_COL_PAL		0x01
324fe5e51b7Smrg#define MGA1064_PIX_RD_MSK	0x02
325fe5e51b7Smrg#define MGA1064_RADR_PAL	0x03
326fe5e51b7Smrg#define MGA1064_DATA		0x0a
327fe5e51b7Smrg
328fe5e51b7Smrg#define MGA1064_CUR_XLOW	0x0c
329fe5e51b7Smrg#define MGA1064_CUR_XHI		0x0d
330fe5e51b7Smrg#define MGA1064_CUR_YLOW	0x0e
331fe5e51b7Smrg#define MGA1064_CUR_YHI		0x0f
332fe5e51b7Smrg
333fe5e51b7Smrg/* MGA1064 indirect registers */
334fe5e51b7Smrg#define MGA1064_DVI_PIPE_CTL    0x03
335fe5e51b7Smrg#define MGA1064_CURSOR_BASE_ADR_LOW	0x04
336fe5e51b7Smrg#define MGA1064_CURSOR_BASE_ADR_HI	0x05
337fe5e51b7Smrg#define MGA1064_CURSOR_CTL	0x06
338fe5e51b7Smrg#define MGA1064_CURSOR_COL0_RED	0x08
339fe5e51b7Smrg#define MGA1064_CURSOR_COL0_GREEN	0x09
340fe5e51b7Smrg#define MGA1064_CURSOR_COL0_BLUE	0x0a
341fe5e51b7Smrg
342fe5e51b7Smrg#define MGA1064_CURSOR_COL1_RED	0x0c
343fe5e51b7Smrg#define MGA1064_CURSOR_COL1_GREEN	0x0d
344fe5e51b7Smrg#define MGA1064_CURSOR_COL1_BLUE	0x0e
345fe5e51b7Smrg
346fe5e51b7Smrg#define MGA1064_CURSOR_COL2_RED	0x010
347fe5e51b7Smrg#define MGA1064_CURSOR_COL2_GREEN	0x011
348fe5e51b7Smrg#define MGA1064_CURSOR_COL2_BLUE	0x012
349fe5e51b7Smrg
350fe5e51b7Smrg#define MGA1064_VREF_CTL	0x018
351fe5e51b7Smrg
352fe5e51b7Smrg#define MGA1064_MUL_CTL		0x19
353fe5e51b7Smrg#define MGA1064_MUL_CTL_8bits		0x0
354fe5e51b7Smrg#define MGA1064_MUL_CTL_15bits		0x01
355fe5e51b7Smrg#define MGA1064_MUL_CTL_16bits		0x02
356fe5e51b7Smrg#define MGA1064_MUL_CTL_24bits		0x03
357fe5e51b7Smrg#define MGA1064_MUL_CTL_32bits		0x04
358fe5e51b7Smrg#define MGA1064_MUL_CTL_2G8V16bits		0x05
359fe5e51b7Smrg#define MGA1064_MUL_CTL_G16V16bits		0x06
360fe5e51b7Smrg#define MGA1064_MUL_CTL_32_24bits		0x07
361fe5e51b7Smrg
362fe5e51b7Smrg#define MGA1064_PIX_CLK_CTL		0x1a
363fe5e51b7Smrg#define MGA1064_PIX_CLK_CTL_CLK_DIS   		( 0x01 << 2 )
364fe5e51b7Smrg#define MGA1064_PIX_CLK_CTL_CLK_POW_DOWN   	( 0x01 << 3 )
365fe5e51b7Smrg#define MGA1064_PIX_CLK_CTL_SEL_PCI   		( 0x00 << 0 )
366fe5e51b7Smrg#define MGA1064_PIX_CLK_CTL_SEL_PLL   		( 0x01 << 0 )
367fe5e51b7Smrg#define MGA1064_PIX_CLK_CTL_SEL_EXT   		( 0x02 << 0 )
368fe5e51b7Smrg#define MGA1064_PIX_CLK_CTL_SEL_MSK   		( 0x03 << 0 )
369fe5e51b7Smrg
370fe5e51b7Smrg#define MGA1064_GEN_CTL		0x1d
371fe5e51b7Smrg#define MGA1064_GEN_CTL_SYNC_ON_GREEN_DIS      (0x01 << 5)
372fe5e51b7Smrg#define MGA1064_MISC_CTL	0x1e
373fe5e51b7Smrg#define MGA1064_MISC_CTL_DAC_EN                ( 0x01 << 0 )
374fe5e51b7Smrg#define MGA1064_MISC_CTL_VGA   		( 0x01 << 1 )
375fe5e51b7Smrg#define MGA1064_MISC_CTL_DIS_CON   		( 0x03 << 1 )
376fe5e51b7Smrg#define MGA1064_MISC_CTL_MAFC   		( 0x02 << 1 )
377fe5e51b7Smrg#define MGA1064_MISC_CTL_VGA8   		( 0x01 << 3 )
378fe5e51b7Smrg#define MGA1064_MISC_CTL_DAC_RAM_CS   		( 0x01 << 4 )
379fe5e51b7Smrg
380fe5e51b7Smrg#define MGA1064_GEN_IO_CTL	0x2a
381fe5e51b7Smrg#define MGA1064_GEN_IO_DATA	0x2b
382fe5e51b7Smrg#define MGA1064_SYS_PLL_M	0x2c
383fe5e51b7Smrg#define MGA1064_SYS_PLL_N	0x2d
384fe5e51b7Smrg#define MGA1064_SYS_PLL_P	0x2e
385fe5e51b7Smrg#define MGA1064_SYS_PLL_STAT	0x2f
386eda3803bSmrg
387eda3803bSmrg#define MGA1064_REMHEADCTL     0x30
388eda3803bSmrg#define MGA1064_REMHEADCTL_CLKDIS ( 0x01 << 0 )
389eda3803bSmrg#define MGA1064_REMHEADCTL_CLKSL_OFF ( 0x00 << 1 )
390eda3803bSmrg#define MGA1064_REMHEADCTL_CLKSL_PLL ( 0x01 << 1 )
391eda3803bSmrg#define MGA1064_REMHEADCTL_CLKSL_PCI ( 0x02 << 1 )
392eda3803bSmrg#define MGA1064_REMHEADCTL_CLKSL_MSK ( 0x03 << 1 )
393eda3803bSmrg
394eda3803bSmrg#define MGA1064_REMHEADCTL2     0x31
395eda3803bSmrg
396fe5e51b7Smrg#define MGA1064_ZOOM_CTL	0x38
397fe5e51b7Smrg#define MGA1064_SENSE_TST	0x3a
398fe5e51b7Smrg
399fe5e51b7Smrg#define MGA1064_CRC_LSB		0x3c
400fe5e51b7Smrg#define MGA1064_CRC_MSB		0x3d
401fe5e51b7Smrg#define MGA1064_CRC_CTL		0x3e
402fe5e51b7Smrg#define MGA1064_COL_KEY_MSK_LSB		0x40
403fe5e51b7Smrg#define MGA1064_COL_KEY_MSK_MSB		0x41
404fe5e51b7Smrg#define MGA1064_COL_KEY_LSB		0x42
405fe5e51b7Smrg#define MGA1064_COL_KEY_MSB		0x43
406fe5e51b7Smrg#define MGA1064_PIX_PLLA_M	0x44
407fe5e51b7Smrg#define MGA1064_PIX_PLLA_N	0x45
408fe5e51b7Smrg#define MGA1064_PIX_PLLA_P	0x46
409fe5e51b7Smrg#define MGA1064_PIX_PLLB_M	0x48
410fe5e51b7Smrg#define MGA1064_PIX_PLLB_N	0x49
411fe5e51b7Smrg#define MGA1064_PIX_PLLB_P	0x4a
412fe5e51b7Smrg#define MGA1064_PIX_PLLC_M	0x4c
413fe5e51b7Smrg#define MGA1064_PIX_PLLC_N	0x4d
414fe5e51b7Smrg#define MGA1064_PIX_PLLC_P	0x4e
415fe5e51b7Smrg
416fe5e51b7Smrg#define MGA1064_PIX_PLL_STAT	0x4f
417fe5e51b7Smrg
418fe5e51b7Smrg/*Added for G450 dual head*/
419fe5e51b7Smrg
420fe5e51b7Smrg#define MGA1064_VID_PLL_STAT    0x8c
421fe5e51b7Smrg#define MGA1064_VID_PLL_P       0x8D
422fe5e51b7Smrg#define MGA1064_VID_PLL_M       0x8E
423fe5e51b7Smrg#define MGA1064_VID_PLL_N       0x8F
424fe5e51b7Smrg
425eda3803bSmrg/* Modified PLL for G200 Winbond (G200WB) */
426eda3803bSmrg#define MGA1064_WB_PIX_PLLC_M	0xb7
427eda3803bSmrg#define MGA1064_WB_PIX_PLLC_N	0xb6
428eda3803bSmrg#define MGA1064_WB_PIX_PLLC_P	0xb8
429eda3803bSmrg
430eda3803bSmrg/* Modified PLL for G200 Maxim (G200EV) */
431eda3803bSmrg#define MGA1064_EV_PIX_PLLC_M	0xb6
432eda3803bSmrg#define MGA1064_EV_PIX_PLLC_N	0xb7
433eda3803bSmrg#define MGA1064_EV_PIX_PLLC_P	0xb8
434eda3803bSmrg
435eda3803bSmrg
436fe5e51b7Smrg#define MGA1064_DISP_CTL        0x8a
437fe5e51b7Smrg#define MGA1064_DISP_CTL_DAC1OUTSEL_MASK       0x01
438fe5e51b7Smrg#define MGA1064_DISP_CTL_DAC1OUTSEL_DIS        0x00
439fe5e51b7Smrg#define MGA1064_DISP_CTL_DAC1OUTSEL_EN         0x01
440fe5e51b7Smrg#define MGA1064_DISP_CTL_DAC2OUTSEL_MASK       (0x03 << 2)
441fe5e51b7Smrg#define MGA1064_DISP_CTL_DAC2OUTSEL_DIS        0x00
442fe5e51b7Smrg#define MGA1064_DISP_CTL_DAC2OUTSEL_CRTC1      (0x01 << 2)
443fe5e51b7Smrg#define MGA1064_DISP_CTL_DAC2OUTSEL_CRTC2      (0x02 << 2)
444fe5e51b7Smrg#define MGA1064_DISP_CTL_DAC2OUTSEL_TVE        (0x03 << 2)
445fe5e51b7Smrg#define MGA1064_DISP_CTL_PANOUTSEL_MASK        (0x03 << 5)
446fe5e51b7Smrg#define MGA1064_DISP_CTL_PANOUTSEL_DIS         0x00
447fe5e51b7Smrg#define MGA1064_DISP_CTL_PANOUTSEL_CRTC1       (0x01 << 5)
448fe5e51b7Smrg#define MGA1064_DISP_CTL_PANOUTSEL_CRTC2RGB    (0x02 << 5)
449fe5e51b7Smrg#define MGA1064_DISP_CTL_PANOUTSEL_CRTC2656    (0x03 << 5)
450fe5e51b7Smrg
451fe5e51b7Smrg#define MGA1064_SYNC_CTL        0x8b
452fe5e51b7Smrg
453fe5e51b7Smrg#define MGA1064_PWR_CTL         0xa0
454fe5e51b7Smrg#define MGA1064_PWR_CTL_DAC2_EN                (0x01 << 0)
455fe5e51b7Smrg#define MGA1064_PWR_CTL_VID_PLL_EN             (0x01 << 1)
456fe5e51b7Smrg#define MGA1064_PWR_CTL_PANEL_EN               (0x01 << 2)
457fe5e51b7Smrg#define MGA1064_PWR_CTL_RFIFO_EN               (0x01 << 3)
458fe5e51b7Smrg#define MGA1064_PWR_CTL_CFIFO_EN               (0x01 << 4)
459fe5e51b7Smrg
460fe5e51b7Smrg#define MGA1064_PAN_CTL         0xa2
461fe5e51b7Smrg
462fe5e51b7Smrg/* Using crtc2 */
463fe5e51b7Smrg#define MGAREG2_C2CTL            0x10
464fe5e51b7Smrg#define MGAREG2_C2HPARAM         0x14
465fe5e51b7Smrg#define MGAREG2_C2HSYNC          0x18
466fe5e51b7Smrg#define MGAREG2_C2VPARAM         0x1c
467fe5e51b7Smrg#define MGAREG2_C2VSYNC          0x20
468fe5e51b7Smrg#define MGAREG2_C2STARTADD0      0x28
469fe5e51b7Smrg
470fe5e51b7Smrg#define MGAREG2_C2OFFSET         0x40
471fe5e51b7Smrg#define MGAREG2_C2DATACTL        0x4c
472fe5e51b7Smrg
473fe5e51b7Smrg#define MGAREG_C2CTL            0x3c10
474fe5e51b7Smrg#define MGAREG_C2CTL_C2_EN                     0x01
475fe5e51b7Smrg
476fe5e51b7Smrg#define MGAREG_C2_HIPRILVL_M                   (0x07 << 4)
477fe5e51b7Smrg#define MGAREG_C2_MAXHIPRI_M                   (0x07 << 8)
478fe5e51b7Smrg
479fe5e51b7Smrg#define MGAREG_C2CTL_PIXCLKSEL_MASK            (0x03 << 1)
480fe5e51b7Smrg#define MGAREG_C2CTL_PIXCLKSELH_MASK           (0x01 << 14)
481fe5e51b7Smrg#define MGAREG_C2CTL_PIXCLKSEL_PCICLK          0x00
482fe5e51b7Smrg#define MGAREG_C2CTL_PIXCLKSEL_VDOCLK          (0x01 << 1)
483fe5e51b7Smrg#define MGAREG_C2CTL_PIXCLKSEL_PIXELPLL        (0x02 << 1)
484fe5e51b7Smrg#define MGAREG_C2CTL_PIXCLKSEL_VIDEOPLL        (0x03 << 1)
485fe5e51b7Smrg#define MGAREG_C2CTL_PIXCLKSEL_VDCLK           (0x01 << 14)
486fe5e51b7Smrg
487fe5e51b7Smrg#define MGAREG_C2CTL_PIXCLKSEL_CRISTAL         (0x01 << 1) | (0x01 << 14)
488fe5e51b7Smrg#define MGAREG_C2CTL_PIXCLKSEL_SYSTEMPLL       (0x02 << 1) | (0x01 << 14)
489fe5e51b7Smrg
490fe5e51b7Smrg#define MGAREG_C2CTL_PIXCLKDIS_MASK            (0x01 << 3)
491fe5e51b7Smrg#define MGAREG_C2CTL_PIXCLKDIS_DISABLE         (0x01 << 3)
492fe5e51b7Smrg
493fe5e51b7Smrg#define MGAREG_C2CTL_CRTCDACSEL_MASK           (0x01 << 20)
494fe5e51b7Smrg#define MGAREG_C2CTL_CRTCDACSEL_CRTC1          0x00
495fe5e51b7Smrg#define MGAREG_C2CTL_CRTCDACSEL_CRTC2          (0x01 << 20)
496fe5e51b7Smrg
497fe5e51b7Smrg#define MGAREG_C2HPARAM         0x3c14
498fe5e51b7Smrg#define MGAREG_C2HSYNC          0x3c18
499fe5e51b7Smrg#define MGAREG_C2VPARAM         0x3c1c
500fe5e51b7Smrg#define MGAREG_C2VSYNC          0x3c20
501fe5e51b7Smrg#define MGAREG_C2STARTADD0      0x3c28
502fe5e51b7Smrg
503fe5e51b7Smrg#define MGAREG_C2OFFSET         0x3c40
504fe5e51b7Smrg#define MGAREG_C2DATACTL        0x3c4c
505fe5e51b7Smrg
506fe5e51b7Smrg/* video register */
507fe5e51b7Smrg
508fe5e51b7Smrg#define MGAREG_BESA1C3ORG	0x3d60
509fe5e51b7Smrg#define MGAREG_BESA1CORG	0x3d10
510fe5e51b7Smrg#define MGAREG_BESA1ORG		0x3d00
511fe5e51b7Smrg#define MGAREG_BESCTL		0x3d20
512fe5e51b7Smrg#define MGAREG_BESGLOBCTL	0x3dc0
513fe5e51b7Smrg#define MGAREG_BESHCOORD	0x3d28
514fe5e51b7Smrg#define MGAREG_BESHISCAL	0x3d30
515fe5e51b7Smrg#define MGAREG_BESHSRCEND	0x3d3c
516fe5e51b7Smrg#define MGAREG_BESHSRCLST	0x3d50
517fe5e51b7Smrg#define MGAREG_BESHSRCST	0x3d38
518fe5e51b7Smrg#define MGAREG_BESLUMACTL	0x3d40
519fe5e51b7Smrg#define MGAREG_BESPITCH		0x3d24
520fe5e51b7Smrg#define MGAREG_BESV1SRCLST	0x3d54
521fe5e51b7Smrg#define MGAREG_BESV1WGHT	0x3d48
522fe5e51b7Smrg#define MGAREG_BESVCOORD	0x3d2c
523fe5e51b7Smrg#define MGAREG_BESVISCAL	0x3d34
524fe5e51b7Smrg
525fe5e51b7Smrg/* texture engine registers */
526fe5e51b7Smrg
527fe5e51b7Smrg#define MGAREG_TMR0		0x2c00
528fe5e51b7Smrg#define MGAREG_TMR1		0x2c04
529fe5e51b7Smrg#define MGAREG_TMR2		0x2c08
530fe5e51b7Smrg#define MGAREG_TMR3		0x2c0c
531fe5e51b7Smrg#define MGAREG_TMR4		0x2c10
532fe5e51b7Smrg#define MGAREG_TMR5		0x2c14
533fe5e51b7Smrg#define MGAREG_TMR6		0x2c18
534fe5e51b7Smrg#define MGAREG_TMR7		0x2c1c
535fe5e51b7Smrg#define MGAREG_TMR8		0x2c20
536fe5e51b7Smrg#define MGAREG_TEXORG		0x2c24
537fe5e51b7Smrg#define MGAREG_TEXWIDTH		0x2c28
538fe5e51b7Smrg#define MGAREG_TEXHEIGHT	0x2c2c
539fe5e51b7Smrg#define MGAREG_TEXCTL		0x2c30
540fe5e51b7Smrg#    define MGA_TW4                             (0x00000000)
541fe5e51b7Smrg#    define MGA_TW8                             (0x00000001)
542fe5e51b7Smrg#    define MGA_TW15                            (0x00000002)
543fe5e51b7Smrg#    define MGA_TW16                            (0x00000003)
544fe5e51b7Smrg#    define MGA_TW12                            (0x00000004)
545fe5e51b7Smrg#    define MGA_TW32                            (0x00000006)
546fe5e51b7Smrg#    define MGA_TW8A                            (0x00000007)
547fe5e51b7Smrg#    define MGA_TW8AL                           (0x00000008)
548fe5e51b7Smrg#    define MGA_TW422                           (0x0000000A)
549fe5e51b7Smrg#    define MGA_TW422UYVY                       (0x0000000B)
550fe5e51b7Smrg#    define MGA_PITCHLIN                        (0x00000100)
551fe5e51b7Smrg#    define MGA_NOPERSPECTIVE                   (0x00200000)
552fe5e51b7Smrg#    define MGA_TAKEY                           (0x02000000)
553fe5e51b7Smrg#    define MGA_TAMASK                          (0x04000000)
554fe5e51b7Smrg#    define MGA_CLAMPUV                         (0x18000000)
555fe5e51b7Smrg#    define MGA_TEXMODULATE                     (0x20000000)
556fe5e51b7Smrg#define MGAREG_TEXCTL2		0x2c3c
557fe5e51b7Smrg#    define MGA_G400_TC2_MAGIC                  (0x00008000)
558fe5e51b7Smrg#    define MGA_TC2_DECALBLEND                  (0x00000001)
559fe5e51b7Smrg#    define MGA_TC2_IDECAL                      (0x00000002)
560fe5e51b7Smrg#    define MGA_TC2_DECALDIS                    (0x00000004)
561fe5e51b7Smrg#    define MGA_TC2_CKSTRANSDIS                 (0x00000010)
562fe5e51b7Smrg#    define MGA_TC2_BORDEREN                    (0x00000020)
563fe5e51b7Smrg#    define MGA_TC2_SPECEN                      (0x00000040)
564fe5e51b7Smrg#    define MGA_TC2_DUALTEX                     (0x00000080)
565fe5e51b7Smrg#    define MGA_TC2_TABLEFOG                    (0x00000100)
566fe5e51b7Smrg#    define MGA_TC2_BUMPMAP                     (0x00000200)
567fe5e51b7Smrg#    define MGA_TC2_SELECT_TMU1                 (0x80000000)
568fe5e51b7Smrg#define MGAREG_TEXTRANS		0x2c34
569fe5e51b7Smrg#define MGAREG_TEXTRANSHIGH	0x2c38
570fe5e51b7Smrg#define MGAREG_TEXFILTER	0x2c58
571fe5e51b7Smrg#    define MGA_MIN_NRST                        (0x00000000)
572fe5e51b7Smrg#    define MGA_MIN_BILIN                       (0x00000002)
573fe5e51b7Smrg#    define MGA_MIN_ANISO                       (0x0000000D)
574fe5e51b7Smrg#    define MGA_MAG_NRST                        (0x00000000)
575fe5e51b7Smrg#    define MGA_MAG_BILIN                       (0x00000020)
576fe5e51b7Smrg#    define MGA_FILTERALPHA                     (0x00100000)
577fe5e51b7Smrg#define MGAREG_ALPHASTART	0x2c70
578fe5e51b7Smrg#define MGAREG_ALPHAXINC	0x2c74
579fe5e51b7Smrg#define MGAREG_ALPHAYINC	0x2c78
580fe5e51b7Smrg#define MGAREG_ALPHACTRL	0x2c7c
581fe5e51b7Smrg#    define MGA_SRC_ZERO                        (0x00000000)
582fe5e51b7Smrg#    define MGA_SRC_ONE                         (0x00000001)
583fe5e51b7Smrg#    define MGA_SRC_DST_COLOR                   (0x00000002)
584fe5e51b7Smrg#    define MGA_SRC_ONE_MINUS_DST_COLOR         (0x00000003)
585fe5e51b7Smrg#    define MGA_SRC_ALPHA                       (0x00000004)
586fe5e51b7Smrg#    define MGA_SRC_ONE_MINUS_SRC_ALPHA         (0x00000005)
587fe5e51b7Smrg#    define MGA_SRC_DST_ALPHA                   (0x00000006)
588fe5e51b7Smrg#    define MGA_SRC_ONE_MINUS_DST_ALPHA         (0x00000007)
589fe5e51b7Smrg#    define MGA_SRC_SRC_ALPHA_SATURATE          (0x00000008)
590fe5e51b7Smrg#    define MGA_SRC_BLEND_MASK                  (0x0000000f)
591fe5e51b7Smrg#    define MGA_DST_ZERO                        (0x00000000)
592fe5e51b7Smrg#    define MGA_DST_ONE                         (0x00000010)
593fe5e51b7Smrg#    define MGA_DST_SRC_COLOR                   (0x00000020)
594fe5e51b7Smrg#    define MGA_DST_ONE_MINUS_SRC_COLOR         (0x00000030)
595fe5e51b7Smrg#    define MGA_DST_SRC_ALPHA                   (0x00000040)
596fe5e51b7Smrg#    define MGA_DST_ONE_MINUS_SRC_ALPHA         (0x00000050)
597fe5e51b7Smrg#    define MGA_DST_DST_ALPHA                   (0x00000060)
598fe5e51b7Smrg#    define MGA_DST_ONE_MINUS_DST_ALPHA         (0x00000070)
599fe5e51b7Smrg#    define MGA_DST_BLEND_MASK                  (0x00000070)
600fe5e51b7Smrg#    define MGA_ALPHACHANNEL                    (0x00000100)
601fe5e51b7Smrg#    define MGA_VIDEOALPHA                      (0x00000200)
602fe5e51b7Smrg#    define MGA_DIFFUSEDALPHA                   (0x01000000)
603fe5e51b7Smrg#    define MGA_MODULATEDALPHA                  (0x02000000)
604fe5e51b7Smrg#define MGAREG_TDUALSTAGE0                      (0x2CF8)
605fe5e51b7Smrg#define MGAREG_TDUALSTAGE1                      (0x2CFC)
606fe5e51b7Smrg#    define MGA_TDS_COLOR_ARG2_DIFFUSE          (0x00000000)
607fe5e51b7Smrg#    define MGA_TDS_COLOR_ARG2_SPECULAR         (0x00000001)
608fe5e51b7Smrg#    define MGA_TDS_COLOR_ARG2_FCOL             (0x00000002)
609fe5e51b7Smrg#    define MGA_TDS_COLOR_ARG2_PREVSTAGE        (0x00000003)
610fe5e51b7Smrg#    define MGA_TDS_COLOR_ALPHA_DIFFUSE         (0x00000000)
611fe5e51b7Smrg#    define MGA_TDS_COLOR_ALPHA_FCOL            (0x00000004)
612fe5e51b7Smrg#    define MGA_TDS_COLOR_ALPHA_CURRTEX         (0x00000008)
613fe5e51b7Smrg#    define MGA_TDS_COLOR_ALPHA_PREVTEX         (0x0000000c)
614fe5e51b7Smrg#    define MGA_TDS_COLOR_ALPHA_PREVSTAGE       (0x00000010)
615fe5e51b7Smrg#    define MGA_TDS_COLOR_ARG1_REPLICATEALPHA   (0x00000020)
616fe5e51b7Smrg#    define MGA_TDS_COLOR_ARG1_INV              (0x00000040)
617fe5e51b7Smrg#    define MGA_TDS_COLOR_ARG2_REPLICATEALPHA   (0x00000080)
618fe5e51b7Smrg#    define MGA_TDS_COLOR_ARG2_INV              (0x00000100)
619fe5e51b7Smrg#    define MGA_TDS_COLOR_ALPHA1INV             (0x00000200)
620fe5e51b7Smrg#    define MGA_TDS_COLOR_ALPHA2INV             (0x00000400)
621fe5e51b7Smrg#    define MGA_TDS_COLOR_ARG1MUL_ALPHA1        (0x00000800)
622fe5e51b7Smrg#    define MGA_TDS_COLOR_ARG2MUL_ALPHA2        (0x00001000)
623fe5e51b7Smrg#    define MGA_TDS_COLOR_ARG1ADD_MULOUT        (0x00002000)
624fe5e51b7Smrg#    define MGA_TDS_COLOR_ARG2ADD_MULOUT        (0x00004000)
625fe5e51b7Smrg#    define MGA_TDS_COLOR_MODBRIGHT_2X          (0x00008000)
626fe5e51b7Smrg#    define MGA_TDS_COLOR_MODBRIGHT_4X          (0x00010000)
627fe5e51b7Smrg#    define MGA_TDS_COLOR_ADD_SUB               (0x00000000)
628fe5e51b7Smrg#    define MGA_TDS_COLOR_ADD_ADD               (0x00020000)
629fe5e51b7Smrg#    define MGA_TDS_COLOR_ADD2X                 (0x00040000)
630fe5e51b7Smrg#    define MGA_TDS_COLOR_ADDBIAS               (0x00080000)
631fe5e51b7Smrg#    define MGA_TDS_COLOR_BLEND                 (0x00100000)
632fe5e51b7Smrg#    define MGA_TDS_COLOR_SEL_ARG1              (0x00000000)
633fe5e51b7Smrg#    define MGA_TDS_COLOR_SEL_ARG2              (0x00200000)
634fe5e51b7Smrg#    define MGA_TDS_COLOR_SEL_ADD               (0x00400000)
635fe5e51b7Smrg#    define MGA_TDS_COLOR_SEL_MUL               (0x00600000)
636fe5e51b7Smrg#    define MGA_TDS_ALPHA_ARG1_INV              (0x00800000)
637fe5e51b7Smrg#    define MGA_TDS_ALPHA_ARG2_DIFFUSE          (0x00000000)
638fe5e51b7Smrg#    define MGA_TDS_ALPHA_ARG2_FCOL             (0x01000000)
639fe5e51b7Smrg#    define MGA_TDS_ALPHA_ARG2_PREVTEX          (0x02000000)
640fe5e51b7Smrg#    define MGA_TDS_ALPHA_ARG2_PREVSTAGE        (0x03000000)
641fe5e51b7Smrg#    define MGA_TDS_ALPHA_ARG2_INV              (0x04000000)
642fe5e51b7Smrg#    define MGA_TDS_ALPHA_ADD                   (0x08000000)
643fe5e51b7Smrg#    define MGA_TDS_ALPHA_ADDBIAS               (0x10000000)
644fe5e51b7Smrg#    define MGA_TDS_ALPHA_ADD2X                 (0x20000000)
645fe5e51b7Smrg#    define MGA_TDS_ALPHA_SEL_ARG1              (0x00000000)
646fe5e51b7Smrg#    define MGA_TDS_ALPHA_SEL_ARG2              (0x40000000)
647fe5e51b7Smrg#    define MGA_TDS_ALPHA_SEL_ADD               (0x80000000)
648fe5e51b7Smrg#    define MGA_TDS_ALPHA_SEL_MUL               (0xc0000000)
649fe5e51b7Smrg
650fe5e51b7Smrg#define MGAREG_DWGSYNC		0x2c4c
651fe5e51b7Smrg
652fe5e51b7Smrg#define MGAREG_AGP_PLL		0x1e4c
653fe5e51b7Smrg#define MGA_AGP2XPLL_ENABLE		0x1
654fe5e51b7Smrg#define MGA_AGP2XPLL_DISABLE		0x0
655fe5e51b7Smrg
656fe5e51b7Smrg#endif
657