nvc0_accel.h revision cd34e0e1
1#ifndef __NVC0_ACCEL_H__ 2#define __NVC0_ACCEL_H__ 3 4#include "hwdefs/nv_object.xml.h" 5#include "hwdefs/nv50_2d.xml.h" 6#include "hwdefs/nvc0_3d.xml.h" 7#include "hwdefs/nvc0_m2mf.xml.h" 8#include "hwdefs/nv50_defs.xml.h" 9#include "hwdefs/nv50_texture.h" 10#include "hwdefs/gm107_texture.xml.h" 11#include "hwdefs/nv_3ddefs.xml.h" 12 13/* subchannel assignments, compatible with kepler's fixed layout */ 14#define SUBC_3D(mthd) 0, (mthd) 15#define NVC0_3D(mthd) SUBC_3D(NVC0_3D_##mthd) 16#define NVE4_3D(mthd) SUBC_3D(NVE4_3D_##mthd) 17#define SUBC_M2MF(mthd) 2, (mthd) 18#define SUBC_P2MF(mthd) 2, (mthd) 19#define NVC0_M2MF(mthd) SUBC_M2MF(NVC0_M2MF_##mthd) 20#define SUBC_2D(mthd) 3, (mthd) 21#define NV50_2D(mthd) SUBC_2D(NV50_2D_##mthd) 22#define NVC0_2D(mthd) SUBC_2D(NVC0_2D_##mthd) 23#define SUBC_COPY(mthd) 4, (mthd) 24#define SUBC_NVSW(mthd) 5, (mthd) 25 26/* scratch buffer offsets */ 27#define CODE_OFFSET 0x00000 /* Code */ 28#define PVP_DATA 0x01000 /* VP constants */ 29#define PFP_DATA 0x01100 /* FP constants */ 30#define TB_OFFSET 0x01800 /* Texture bindings (kepler) */ 31#define TIC_OFFSET 0x02000 /* Texture Image Control */ 32#define TSC_OFFSET 0x03000 /* Texture Sampler Control */ 33#define SOLID(i) (0x04000 + (i) * 0x100) 34#define NTFY_OFFSET 0x08000 35#define SEMA_OFFSET 0x08100 36#define MISC_OFFSET 0x10000 37 38/* vertex/fragment programs */ 39#define SPO ((pNv->Architecture < NV_KEPLER) ? 0x0000 : 0x0030) 40#define PVP_PASS (0x0000 + SPO) /* vertex pass-through shader */ 41#define PFP_S (0x0200 + SPO) /* (src) */ 42#define PFP_C (0x0400 + SPO) /* (src IN mask) */ 43#define PFP_CCA (0x0600 + SPO) /* (src IN mask) component-alpha */ 44#define PFP_CCASA (0x0800 + SPO) /* (src IN mask) component-alpha src-alpha */ 45#define PFP_S_A8 (0x0a00 + SPO) /* (src) a8 rt */ 46#define PFP_C_A8 (0x0c00 + SPO) /* (src IN mask) a8 rt - same for CCA/CCASA */ 47#define PFP_NV12 (0x0e00 + SPO) /* NV12 YUV->RGB */ 48 49 50#define VTX_ATTR(a, c, t, s) \ 51 ((NVC0_3D_VTX_ATTR_DEFINE_TYPE_##t) | \ 52 ((a) << NVC0_3D_VTX_ATTR_DEFINE_ATTR__SHIFT) | \ 53 ((c) << NVC0_3D_VTX_ATTR_DEFINE_COMP__SHIFT) | \ 54 ((s) << NVC0_3D_VTX_ATTR_DEFINE_SIZE__SHIFT)) 55 56static __inline__ void 57PUSH_VTX1s(struct nouveau_pushbuf *push, float sx, float sy, int dx, int dy) 58{ 59 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 3); 60 PUSH_DATA (push, VTX_ATTR(1, 2, FLOAT, 4)); 61 PUSH_DATAf(push, sx); 62 PUSH_DATAf(push, sy); 63 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 3); 64 PUSH_DATA (push, VTX_ATTR(0, 2, SSCALED, 4)); 65 PUSH_DATA (push, dx); 66 PUSH_DATA (push, dy); 67} 68 69static __inline__ void 70PUSH_VTX2s(struct nouveau_pushbuf *push, 71 int x0, int y0, int x1, int y1, int dx, int dy) 72{ 73 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 3); 74 PUSH_DATA (push, VTX_ATTR(1, 2, SSCALED, 4)); 75 PUSH_DATA (push, x0); 76 PUSH_DATA (push, y0); 77 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 3); 78 PUSH_DATA (push, VTX_ATTR(2, 2, SSCALED, 4)); 79 PUSH_DATA (push, x1); 80 PUSH_DATA (push, y1); 81 BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 3); 82 PUSH_DATA (push, VTX_ATTR(0, 2, SSCALED, 4)); 83 PUSH_DATA (push, dx); 84 PUSH_DATA (push, dy); 85} 86 87static __inline__ void 88PUSH_DATAu(struct nouveau_pushbuf *push, struct nouveau_bo *bo, 89 unsigned delta, unsigned dwords) 90{ 91 if (push->client->device->chipset < 0xe0) { 92 BEGIN_NVC0(push, NVC0_M2MF(OFFSET_OUT_HIGH), 2); 93 PUSH_DATA (push, (bo->offset + delta) >> 32); 94 PUSH_DATA (push, (bo->offset + delta)); 95 BEGIN_NVC0(push, NVC0_M2MF(LINE_LENGTH_IN), 2); 96 PUSH_DATA (push, dwords * 4); 97 PUSH_DATA (push, 1); 98 BEGIN_NVC0(push, NVC0_M2MF(EXEC), 1); 99 PUSH_DATA (push, 0x100111); 100 BEGIN_NIC0(push, NVC0_M2MF(DATA), dwords); 101 } else { 102 BEGIN_NVC0(push, SUBC_P2MF(0x0180), 4); 103 PUSH_DATA (push, dwords * 4); 104 PUSH_DATA (push, 1); 105 PUSH_DATA (push, (bo->offset + delta) >> 32); 106 PUSH_DATA (push, (bo->offset + delta)); 107 BEGIN_1IC0(push, SUBC_P2MF(0x01b0), 1 + dwords); 108 PUSH_DATA (push, 0x001001); 109 } 110} 111 112static __inline__ void 113PUSH_TIC(struct nouveau_pushbuf *push, struct nouveau_bo *bo, unsigned offset, 114 unsigned width, unsigned height, unsigned pitch, unsigned format) 115{ 116 if (push->client->device->chipset < 0x110) { 117 unsigned tic2 = 0xd0001000; 118 if (pitch == 0) 119 tic2 |= 0x00004000; 120 else 121 tic2 |= 0x0005c000; 122 PUSH_DATA(push, format); 123 PUSH_DATA(push, bo->offset + offset); 124 PUSH_DATA(push, ((bo->offset + offset) >> 32) | 125 (bo->config.nvc0.tile_mode << 18) | 126 tic2); 127 PUSH_DATA(push, 0x00300000); 128 PUSH_DATA(push, 0x80000000 | width); 129 PUSH_DATA(push, 0x00010000 | height); 130 PUSH_DATA(push, 0x03000000); 131 PUSH_DATA(push, 0x00000000); 132 } else { 133 unsigned tile_mode = bo->config.nvc0.tile_mode; 134 PUSH_DATA(push, (format & 0x3f) | ((format & ~0x3f) << 1)); 135 PUSH_DATA(push, bo->offset + offset); 136 if (pitch == 0) { 137 PUSH_DATA(push, ((bo->offset + offset) >> 32) | 138 GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR); 139 PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 | 140 ((tile_mode & 0x007)) | 141 ((tile_mode & 0x070) >> (4 - 3)) | 142 ((tile_mode & 0x700) >> (8 - 6))); 143 PUSH_DATA(push, GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V | 144 GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR | 145 GM107_TIC2_4_TEXTURE_TYPE_TWO_D | 146 (width - 1)); 147 PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS | 148 ((height - 1) & 0xffff)); 149 PUSH_DATA(push, GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO | 150 GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE); 151 PUSH_DATA(push, 0x00000000); 152 } else { 153 PUSH_DATA(push, ((bo->offset + offset) >> 32) | 154 GM107_TIC2_2_HEADER_VERSION_PITCH); 155 PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 | 156 (pitch >> 5)); 157 PUSH_DATA(push, GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR | 158 GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP | 159 (width - 1)); 160 PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS | (height - 1)); 161 PUSH_DATA(push, 0x000000000); 162 PUSH_DATA(push, 0x000000000); 163 } 164 } 165} 166 167#endif 168