171d7fec4Smrg/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nsc/gfx/tv_geode.c,v 1.1 2002/12/10 15:12:27 alanh Exp $ */
271d7fec4Smrg/*-----------------------------------------------------------------------------
371d7fec4Smrg * TV_GEODE.C
471d7fec4Smrg *
571d7fec4Smrg * Version 1.20 - February 9, 2000
671d7fec4Smrg *
771d7fec4Smrg * This file contains routines to program the TV encoder when it is
871d7fec4Smrg * integrated onto a Geode processor.
971d7fec4Smrg *
1071d7fec4Smrg * History:
1171d7fec4Smrg *    Initial version ported from code by Ilia Stolov.
1271d7fec4Smrg *    Versions 0.1 through 1.20 by Brian Falardeau.
1371d7fec4Smrg *
1471d7fec4Smrg * Copyright (c) 1999-2000 National Semiconductor.
1571d7fec4Smrg *-----------------------------------------------------------------------------
1671d7fec4Smrg */
1771d7fec4Smrg
1871d7fec4Smrg/*-----------------------------------------------------------------------------
1971d7fec4Smrg * gfx_set_tv_defaults
2071d7fec4Smrg *
2171d7fec4Smrg * This routine sets all of the TV encoder registers to default values for
2271d7fec4Smrg * the specified format.  Currently only NTSC is supported.
2371d7fec4Smrg *-----------------------------------------------------------------------------
2471d7fec4Smrg */
2571d7fec4Smrg#if GFX_TV_DYNAMIC
2671d7fec4Smrgint
2771d7fec4Smrggeode_set_tv_defaults(int format)
2871d7fec4Smrg#else
2971d7fec4Smrgint
3071d7fec4Smrggfx_set_tv_defaults(int format)
3171d7fec4Smrg#endif
3271d7fec4Smrg{
3371d7fec4Smrg   /* SET DEFAULTS FOR NTSC */
3471d7fec4Smrg
3571d7fec4Smrg   WRITE_VID32(SC1400_TVOUT_HORZ_TIM, 0x00790359);
3671d7fec4Smrg   WRITE_VID32(SC1400_TVOUT_HORZ_SYNC, 0x03580350);
3771d7fec4Smrg   WRITE_VID32(SC1400_TVOUT_VERT_SYNC, 0x0A002001);
3871d7fec4Smrg   WRITE_VID32(SC1400_TVOUT_LINE_END, 0x039C00F0);
3971d7fec4Smrg   WRITE_VID32(SC1400_TVOUT_VERT_DOWNSCALE, 0xFFFFFFFF);
4071d7fec4Smrg   WRITE_VID32(SC1400_TVOUT_HORZ_SCALING, 0x10220700);
4171d7fec4Smrg   WRITE_VID32(SC1400_TVOUT_EMMA_BYPASS, 0x0002D0F0);
4271d7fec4Smrg   WRITE_VID32(SC1400_TVENC_TIM_CTRL_1, 0xA2E03000);
4371d7fec4Smrg   WRITE_VID32(SC1400_TVENC_TIM_CTRL_2, 0x1FF20000);
4471d7fec4Smrg   WRITE_VID32(SC1400_TVENC_TIM_CTRL_3, 0x00000000);
4571d7fec4Smrg   WRITE_VID32(SC1400_TVENC_SUB_FREQ, 0x21F12000);
4671d7fec4Smrg   WRITE_VID32(SC1400_TVENC_DISP_POS, 0x00030071);
4771d7fec4Smrg   WRITE_VID32(SC1400_TVENC_DISP_SIZE, 0x00EF02CF);
4871d7fec4Smrg
4971d7fec4Smrg   /* ### ADD ### DEFAULTS FOR PAL */
5071d7fec4Smrg   return (0);
5171d7fec4Smrg}
5271d7fec4Smrg
5371d7fec4Smrg/*-----------------------------------------------------------------------------
5471d7fec4Smrg * gfx_set_tv_enable
5571d7fec4Smrg *
5671d7fec4Smrg * This routine enables or disables the TV output.
5771d7fec4Smrg *-----------------------------------------------------------------------------
5871d7fec4Smrg */
5971d7fec4Smrg#if GFX_TV_DYNAMIC
6071d7fec4Smrgint
6171d7fec4Smrggeode_set_tv_enable(int enable)
6271d7fec4Smrg#else
6371d7fec4Smrgint
6471d7fec4Smrggfx_set_tv_enable(int enable)
6571d7fec4Smrg#endif
6671d7fec4Smrg{
6771d7fec4Smrg   unsigned long value;
6871d7fec4Smrg
6971d7fec4Smrg   value = READ_VID32(SC1400_DISPLAY_CONFIG);
7071d7fec4Smrg   if (enable)
7171d7fec4Smrg      value |= SC1400_DCFG_TVOUT_EN;
7271d7fec4Smrg   else
7371d7fec4Smrg      value &= ~(SC1400_DCFG_TVOUT_EN);
7471d7fec4Smrg   WRITE_VID32(SC1400_DISPLAY_CONFIG, value);
7571d7fec4Smrg   return (0);
7671d7fec4Smrg}
7771d7fec4Smrg
7871d7fec4Smrg/*-----------------------------------------------------------------------------
7971d7fec4Smrg * gfx_set_tv_cc_enable
8071d7fec4Smrg *
8171d7fec4Smrg * This routine enables or disables the use of the hardware CC registers
8271d7fec4Smrg * in the TV encoder.
8371d7fec4Smrg *-----------------------------------------------------------------------------
8471d7fec4Smrg */
8571d7fec4Smrg#if GFX_TV_DYNAMIC
8671d7fec4Smrgint
8771d7fec4Smrggeode_set_tv_cc_enable(int enable)
8871d7fec4Smrg#else
8971d7fec4Smrgint
9071d7fec4Smrggfx_set_tv_cc_enable(int enable)
9171d7fec4Smrg#endif
9271d7fec4Smrg{
9371d7fec4Smrg   unsigned long value;
9471d7fec4Smrg
9571d7fec4Smrg   value = READ_VID32(SC1400_TVENC_CC_CONTROL);
9671d7fec4Smrg   value &= ~(0x0005F);
9771d7fec4Smrg   if (enable)
9871d7fec4Smrg      value |= 0x51;
9971d7fec4Smrg   WRITE_VID32(SC1400_TVENC_CC_CONTROL, value);
10071d7fec4Smrg   return (0);
10171d7fec4Smrg}
10271d7fec4Smrg
10371d7fec4Smrg/*-----------------------------------------------------------------------------
10471d7fec4Smrg * gfx_set_tv_cc_data
10571d7fec4Smrg *
10671d7fec4Smrg * This routine writes the two specified characters to the CC data register
10771d7fec4Smrg * of the TV encoder.
10871d7fec4Smrg *-----------------------------------------------------------------------------
10971d7fec4Smrg */
11071d7fec4Smrg#if GFX_TV_DYNAMIC
11171d7fec4Smrgint
11271d7fec4Smrggeode_set_tv_cc_data(unsigned char data1, unsigned char data2)
11371d7fec4Smrg#else
11471d7fec4Smrgint
11571d7fec4Smrggfx_set_tv_cc_data(unsigned char data1, unsigned char data2)
11671d7fec4Smrg#endif
11771d7fec4Smrg{
11871d7fec4Smrg   unsigned long value;
11971d7fec4Smrg
12071d7fec4Smrg   value = data1 | (((unsigned long)data2) << 8);
12171d7fec4Smrg   WRITE_VID32(SC1400_TVENC_CC_DATA, value);
12271d7fec4Smrg   return (0);
12371d7fec4Smrg}
12471d7fec4Smrg
12571d7fec4Smrg/* END OF FILE */
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