190b17f1bSmrg/* 290b17f1bSmrg * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. 390b17f1bSmrg * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. 490b17f1bSmrg * 590b17f1bSmrg * Permission is hereby granted, free of charge, to any person obtaining a 690b17f1bSmrg * copy of this software and associated documentation files (the "Software"), 790b17f1bSmrg * to deal in the Software without restriction, including without limitation 890b17f1bSmrg * the rights to use, copy, modify, merge, publish, distribute, sub license, 990b17f1bSmrg * and/or sell copies of the Software, and to permit persons to whom the 1090b17f1bSmrg * Software is furnished to do so, subject to the following conditions: 1190b17f1bSmrg * 1290b17f1bSmrg * The above copyright notice and this permission notice (including the 1390b17f1bSmrg * next paragraph) shall be included in all copies or substantial portions 1490b17f1bSmrg * of the Software. 1590b17f1bSmrg * 1690b17f1bSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1790b17f1bSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1890b17f1bSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 1990b17f1bSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2090b17f1bSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 2190b17f1bSmrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 2290b17f1bSmrg * DEALINGS IN THE SOFTWARE. 2390b17f1bSmrg */ 2490b17f1bSmrg 2590b17f1bSmrg#ifndef _VIA_ENG_REGS_H_ 2690b17f1bSmrg#define _VIA_H_ 1 2790b17f1bSmrg 2890b17f1bSmrg#include <errno.h> 2990b17f1bSmrg#include <string.h> 3090b17f1bSmrg#include <stdio.h> 3190b17f1bSmrg#include <math.h> 3290b17f1bSmrg#include <assert.h> 3390b17f1bSmrg#include <stdlib.h> 3490b17f1bSmrg 3590b17f1bSmrg/* Video status flag */ 3690b17f1bSmrg 3790b17f1bSmrg#define VIDEO_HIDE 0x00000000 /*Video off*/ 3890b17f1bSmrg#define VIDEO_SHOW 0x80000000 /*Video on*/ 3990b17f1bSmrg#define VIDEO_ACTIVE 0x10000000 /*Video active*/ 4090b17f1bSmrg#define VIDEO_MPEG_INUSE 0x08000000 /*Video is used with MPEG */ 4190b17f1bSmrg#define VIDEO_HQV_INUSE 0x04000000 /*Video is used with HQV*/ 4290b17f1bSmrg#define VIDEO_CAPTURE0_INUSE 0x02000000 /*Video is used with CAPTURE 0*/ 4390b17f1bSmrg#define VIDEO_CAPTURE1_INUSE 0x00000000 /*Video is used with CAPTURE 1*/ 4490b17f1bSmrg#define VIDEO_1_INUSE 0x01000000 /*Video 1 is used with software flip*/ 4590b17f1bSmrg#define VIDEO_3_INUSE 0x00000000 /*Video 3 is used with software flip*/ 4690b17f1bSmrg#define VIDEO_ON 0x00100000 4790b17f1bSmrg#define MPEG_USE_V1 0x00010000 /*[16] : 1:MPEG use V1, 0:MPEG use V3*/ 4890b17f1bSmrg#define MPEG_USE_V3 0x00000000 /*[16] : 1:MPEG use V1, 0:MPEG use V3*/ 4990b17f1bSmrg#define MPEG_USE_HQV 0x00020000 /*[17] : 1:MPEG use HQV,0:MPEG not use HQV*/ 5090b17f1bSmrg#define MPEG_USE_HW_FLIP 0x00040000 /*[18] : 1:MPEG use H/W flip,0:MPEG use S/W flip*/ 5190b17f1bSmrg#define MPEG_USE_SW_FLIP 0x00000000 /*[18] : 1:MPEG use H/W flip,0:MPEG use S/W flip*/ 5290b17f1bSmrg#define CAP0_USE_V1 0x00001000 /*[12] : 1:Capture 0 use V1, 0:Capture 0 use V3*/ 5390b17f1bSmrg#define CAP0_USE_V3 0x00000000 /*[12] : 1:Capture 0 use V1, 0:Capture 0 use V3*/ 5490b17f1bSmrg#define CAP0_USE_HQV 0x00002000 /*[13] : 1:Capture 0 use HQV,0:Capture 0 not use HQV*/ 5590b17f1bSmrg#define CAP0_USE_HW_FLIP 0x00004000 /*[14] : 1:Capture 0 use H/W flip,0:Capture 0 use S/W flip*/ 5690b17f1bSmrg#define CAP0_USE_CCIR656 0x00008000 /*[15] : 1:Capture 0 use CCIR656,0:Capture 0 CCIR601*/ 5790b17f1bSmrg#define CAP1_USE_V1 0x00000100 /*[ 8] : 1:Capture 1 use V1, 0:Capture 1 use V3*/ 5890b17f1bSmrg#define CAP1_USE_V3 0x00000000 /*[ 8] : 1:Capture 1 use V1, 0:Capture 1 use V3*/ 5990b17f1bSmrg#define CAP1_USE_HQV 0x00000200 /*[ 9] : 1:Capture 1 use HQV,0:Capture 1 not use HQV*/ 6090b17f1bSmrg#define CAP1_USE_HW_FLIP 0x00000400 /*[10] : 1:Capture 1 use H/W flip,0:Capture 1 use S/W flip */ 6190b17f1bSmrg#define SW_USE_V1 0x00000010 /*[ 4] : 1:Capture 1 use V1, 0:Capture 1 use V3 */ 6290b17f1bSmrg#define SW_USE_V3 0x00000000 /*[ 4] : 1:Capture 1 use V1, 0:Capture 1 use V3 */ 6390b17f1bSmrg#define SW_USE_HQV 0x00000020 /*[ 5] : 1:Capture 1 use HQV,0:Capture 1 not use HQV */ 6490b17f1bSmrg 6590b17f1bSmrg/* 6690b17f1bSmrg#define VIDEO1_INUSE 0x00000010 //[ 4] : 1:Video 1 is used with S/W flip 6790b17f1bSmrg#define VIDEO1_USE_HQV 0x00000020 //[ 5] : 1:Video 1 use HQV with S/W flip 6890b17f1bSmrg#define VIDEO3_INUSE 0x00000001 //[ 0] : 1:Video 3 is used with S/W flip 6990b17f1bSmrg#define VIDEO3_USE_HQV 0x00000002 //[ 1] : 1:Video 3 use HQV with S/W flip 7090b17f1bSmrg*/ 7190b17f1bSmrg 7290b17f1bSmrg/* H/W registers for Video Engine */ 7390b17f1bSmrg 7490b17f1bSmrg/* 7590b17f1bSmrg * bus master 7690b17f1bSmrg */ 7790b17f1bSmrg#define PCI_MASTER_ENABLE 0x01 7890b17f1bSmrg#define PCI_MASTER_SCATTER 0x00 7990b17f1bSmrg#define PCI_MASTER_SINGLE 0x02 8090b17f1bSmrg#define PCI_MASTER_GUI 0x00 8190b17f1bSmrg#define PCI_MASTER_VIDEO 0x04 8290b17f1bSmrg#define PCI_MASTER_INPUT 0x00 8390b17f1bSmrg#define PCI_MASTER_OUTPUT 0x08 8490b17f1bSmrg 8590b17f1bSmrg/* 8690b17f1bSmrg * video registers 8790b17f1bSmrg */ 8890b17f1bSmrg#define V_FLAGS 0x200 8990b17f1bSmrg#define V_CAP_STATUS 0x204 9090b17f1bSmrg#define V_FLIP_STATUS 0x204 9190b17f1bSmrg#define V_ALPHA_WIN_START 0x208 9290b17f1bSmrg#define V_ALPHA_WIN_END 0x20C 9390b17f1bSmrg#define V_ALPHA_CONTROL 0x210 9490b17f1bSmrg#define V_CRT_STARTADDR 0x214 9590b17f1bSmrg#define V_CRT_STARTADDR_2 0x218 9690b17f1bSmrg#define V_ALPHA_STRIDE 0x21C 9790b17f1bSmrg#define V_COLOR_KEY 0x220 9890b17f1bSmrg#define V_ALPHA_STARTADDR 0x224 9990b17f1bSmrg#define V_CHROMAKEY_LOW 0x228 10090b17f1bSmrg#define V_CHROMAKEY_HIGH 0x22C 10190b17f1bSmrg#define V1_CONTROL 0x230 10290b17f1bSmrg#define V12_QWORD_PER_LINE 0x234 10390b17f1bSmrg#define V1_STARTADDR_1 0x238 10490b17f1bSmrg#define V1_STARTADDR_Y1 V1_STARTADDR_1 10590b17f1bSmrg#define V1_STRIDE 0x23C 10690b17f1bSmrg#define V1_WIN_START_Y 0x240 10790b17f1bSmrg#define V1_WIN_START_X 0x242 10890b17f1bSmrg#define V1_WIN_END_Y 0x244 10990b17f1bSmrg#define V1_WIN_END_X 0x246 11090b17f1bSmrg#define V1_STARTADDR_2 0x248 11190b17f1bSmrg#define V1_STARTADDR_Y2 V1_STARTADDR_2 11290b17f1bSmrg#define V1_ZOOM_CONTROL 0x24C 11390b17f1bSmrg#define V1_MINI_CONTROL 0x250 11490b17f1bSmrg#define V1_STARTADDR_0 0x254 11590b17f1bSmrg#define V1_STARTADDR_Y0 V1_STARTADDR_0 11690b17f1bSmrg#define V_FIFO_CONTROL 0x258 11790b17f1bSmrg#define V1_STARTADDR_3 0x25C 11890b17f1bSmrg#define V1_STARTADDR_Y3 V1_STARTADDR_3 11990b17f1bSmrg#define HI_CONTROL 0x260 12090b17f1bSmrg#define SND_COLOR_KEY 0x264 12190b17f1bSmrg#define ALPHA_V3_PREFIFO_CONTROL 0x268 12290b17f1bSmrg#define V1_SOURCE_HEIGHT 0x26C 12390b17f1bSmrg#define HI_TRANSPARENT_COLOR 0x270 12490b17f1bSmrg#define V_DISPLAY_TEMP 0x274 /* No use */ 12590b17f1bSmrg#define ALPHA_V3_FIFO_CONTROL 0x278 12690b17f1bSmrg#define V3_SOURCE_WIDTH 0x27C 12790b17f1bSmrg#define V3_COLOR_KEY 0x280 12890b17f1bSmrg#define V1_ColorSpaceReg_1 0x284 12990b17f1bSmrg#define V1_ColorSpaceReg_2 0x288 13090b17f1bSmrg#define V1_STARTADDR_CB0 0x28C 13190b17f1bSmrg#define V1_OPAQUE_CONTROL 0x290 /* To be deleted */ 13290b17f1bSmrg#define V3_OPAQUE_CONTROL 0x294 /* To be deleted */ 13390b17f1bSmrg#define V_COMPOSE_MODE 0x298 13490b17f1bSmrg#define V3_STARTADDR_2 0x29C 13590b17f1bSmrg#define V3_CONTROL 0x2A0 13690b17f1bSmrg#define V3_STARTADDR_0 0x2A4 13790b17f1bSmrg#define V3_STARTADDR_1 0x2A8 13890b17f1bSmrg#define V3_STRIDE 0x2AC 13990b17f1bSmrg#define V3_WIN_START_Y 0x2B0 14090b17f1bSmrg#define V3_WIN_START_X 0x2B2 14190b17f1bSmrg#define V3_WIN_END_Y 0x2B4 14290b17f1bSmrg#define V3_WIN_END_X 0x2B6 14390b17f1bSmrg#define V3_ALPHA_QWORD_PER_LINE 0x2B8 14490b17f1bSmrg#define V3_ZOOM_CONTROL 0x2BC 14590b17f1bSmrg#define V3_MINI_CONTROL 0x2C0 14690b17f1bSmrg#define V3_ColorSpaceReg_1 0x2C4 14790b17f1bSmrg#define V3_ColorSpaceReg_2 0x2C8 14890b17f1bSmrg#define V3_DISPLAY_TEMP 0x2CC /* No use */ 14990b17f1bSmrg#define V1_STARTADDR_CB1 0x2E4 15090b17f1bSmrg#define V1_STARTADDR_CB2 0x2E8 15190b17f1bSmrg#define V1_STARTADDR_CB3 0x2EC 15290b17f1bSmrg#define V1_STARTADDR_CR0 0x2F0 15390b17f1bSmrg#define V1_STARTADDR_CR1 0x2F4 15490b17f1bSmrg#define V1_STARTADDR_CR2 0x2F8 15590b17f1bSmrg#define V1_STARTADDR_CR3 0x2FC 15690b17f1bSmrg/*CN400 and older Hardware Icon engine register*/ 15790b17f1bSmrg#define HI_POSSTART 0x208 15890b17f1bSmrg#define HI_CENTEROFFSET 0x20C 15990b17f1bSmrg#define HI_FBOFFSET 0x224 16090b17f1bSmrg#define HI_CONTROL 0x260 16190b17f1bSmrg#define HI_TRANSPARENT_COLOR 0x270 16290b17f1bSmrg#define HI_INVTCOLOR 0x274 16390b17f1bSmrg/* VT3324 primary Hardware Icon engine register */ 16490b17f1bSmrg#define PRIM_HI_POSEND 0x290 16590b17f1bSmrg#define V327_HI_INVTCOLOR 0x2E4 16690b17f1bSmrg#define PRIM_HI_FIFO 0x2E8 16790b17f1bSmrg#define PRIM_HI_TRANSCOLOR 0x2EC 16890b17f1bSmrg#define PRIM_HI_CTRL 0x2F0 16990b17f1bSmrg#define PRIM_HI_FBOFFSET 0x2F4 17090b17f1bSmrg#define PRIM_HI_POSSTART 0x2F8 17190b17f1bSmrg#define PRIM_HI_CENTEROFFSET 0x2FC 17290b17f1bSmrg#define PRIM_HI_INVTCOLOR 0x120C 17390b17f1bSmrg 17490b17f1bSmrg/* Video Capture Engine Registers 17590b17f1bSmrg * Capture Port 1 17690b17f1bSmrg */ 17790b17f1bSmrg#define CAP0_MASKS 0x100 17890b17f1bSmrg#define CAP1_MASKS 0x104 17990b17f1bSmrg#define CAP0_CONTROL 0x110 18090b17f1bSmrg#define CAP0_H_RANGE 0x114 18190b17f1bSmrg#define CAP0_V_RANGE 0x118 18290b17f1bSmrg#define CAP0_SCAL_CONTROL 0x11C 18390b17f1bSmrg#define CAP0_VBI_H_RANGE 0x120 18490b17f1bSmrg#define CAP0_VBI_V_RANGE 0x124 18590b17f1bSmrg#define CAP0_VBI_STARTADDR 0x128 18690b17f1bSmrg#define CAP0_VBI_STRIDE 0x12C 18790b17f1bSmrg#define CAP0_ANCIL_COUNT 0x130 18890b17f1bSmrg#define CAP0_MAXCOUNT 0x134 18990b17f1bSmrg#define CAP0_VBIMAX_COUNT 0x138 19090b17f1bSmrg#define CAP0_DATA_COUNT 0x13C 19190b17f1bSmrg#define CAP0_FB_STARTADDR0 0x140 19290b17f1bSmrg#define CAP0_FB_STARTADDR1 0x144 19390b17f1bSmrg#define CAP0_FB_STARTADDR2 0x148 19490b17f1bSmrg#define CAP0_STRIDE 0x150 19590b17f1bSmrg/* Capture Port 2 */ 19690b17f1bSmrg#define CAP1_CONTROL 0x154 19790b17f1bSmrg#define CAP1_SCAL_CONTROL 0x160 19890b17f1bSmrg#define CAP1_VBI_H_RANGE 0x164 /*To be deleted*/ 19990b17f1bSmrg#define CAP1_VBI_V_RANGE 0x168 /*To be deleted*/ 20090b17f1bSmrg#define CAP1_VBI_STARTADDR 0x16C /*To be deleted*/ 20190b17f1bSmrg#define CAP1_VBI_STRIDE 0x170 /*To be deleted*/ 20290b17f1bSmrg#define CAP1_ANCIL_COUNT 0x174 /*To be deleted*/ 20390b17f1bSmrg#define CAP1_MAXCOUNT 0x178 20490b17f1bSmrg#define CAP1_VBIMAX_COUNT 0x17C /*To be deleted*/ 20590b17f1bSmrg#define CAP1_DATA_COUNT 0x180 20690b17f1bSmrg#define CAP1_FB_STARTADDR0 0x184 20790b17f1bSmrg#define CAP1_FB_STARTADDR1 0x188 20890b17f1bSmrg#define CAP1_STRIDE 0x18C 20990b17f1bSmrg 21090b17f1bSmrg/* SUBPICTURE Registers */ 21190b17f1bSmrg#define SUBP_CONTROL_STRIDE 0x3C0 21290b17f1bSmrg#define SUBP_STARTADDR 0x3C4 21390b17f1bSmrg#define RAM_TABLE_CONTROL 0x3C8 21490b17f1bSmrg#define RAM_TABLE_READ 0x3CC 21590b17f1bSmrg 21690b17f1bSmrg/* HQV Registers*/ 21790b17f1bSmrg#define HQV_CONTROL 0x3D0 21890b17f1bSmrg#define HQV_SRC_STARTADDR_Y 0x3D4 21990b17f1bSmrg#define HQV_SRC_STARTADDR_U 0x3D8 22090b17f1bSmrg#define HQV_SRC_STARTADDR_V 0x3DC 22190b17f1bSmrg#define HQV_SRC_FETCH_LINE 0x3E0 22290b17f1bSmrg#define HQV_FILTER_CONTROL 0x3E4 22390b17f1bSmrg#define HQV_MINIFY_CONTROL 0x3E8 22490b17f1bSmrg#define HQV_DST_STARTADDR0 0x3EC 22590b17f1bSmrg#define HQV_DST_STARTADDR1 0x3F0 22690b17f1bSmrg#define HQV_DST_STARTADDR2 0x3FC 22790b17f1bSmrg#define HQV_DST_STRIDE 0x3F4 22890b17f1bSmrg#define HQV_SRC_STRIDE 0x3F8 22990b17f1bSmrg 23090b17f1bSmrg#define HQV_H_SCALE_CONTROL 0x3B0 23190b17f1bSmrg#define HQV_V_SCALE_CONTROL 0x3B4 23290b17f1bSmrg 23390b17f1bSmrg#define PRO_HQV1_OFFSET 0x1000 23490b17f1bSmrg/* 23590b17f1bSmrg * Video command definition 23690b17f1bSmrg */ 23790b17f1bSmrg/* #define V_ALPHA_CONTROL 0x210 */ 23890b17f1bSmrg#define ALPHA_WIN_EXPIRENUMBER_4 0x00040000 23990b17f1bSmrg#define ALPHA_WIN_CONSTANT_FACTOR_4 0x00004000 24090b17f1bSmrg#define ALPHA_WIN_CONSTANT_FACTOR_12 0x0000c000 24190b17f1bSmrg#define ALPHA_WIN_BLENDING_CONSTANT 0x00000000 24290b17f1bSmrg#define ALPHA_WIN_BLENDING_ALPHA 0x00000001 24390b17f1bSmrg#define ALPHA_WIN_BLENDING_GRAPHIC 0x00000002 24490b17f1bSmrg#define ALPHA_WIN_PREFIFO_THRESHOLD_12 0x000c0000 24590b17f1bSmrg#define ALPHA_WIN_FIFO_THRESHOLD_8 0x000c0000 24690b17f1bSmrg#define ALPHA_WIN_FIFO_DEPTH_16 0x00100000 24790b17f1bSmrg 24890b17f1bSmrg/* V_CHROMAKEY_LOW 0x228 */ 24990b17f1bSmrg#define V_CHROMAKEY_V3 0x80000000 25090b17f1bSmrg 25190b17f1bSmrg/* V1_CONTROL 0x230 */ 25290b17f1bSmrg#define V1_ENABLE 0x00000001 25390b17f1bSmrg#define V1_FULL_SCREEN 0x00000002 25490b17f1bSmrg#define V1_YUV422 0x00000000 25590b17f1bSmrg#define V1_RGB32 0x00000004 25690b17f1bSmrg#define V1_RGB15 0x00000008 25790b17f1bSmrg#define V1_RGB16 0x0000000C 25890b17f1bSmrg#define V1_YCbCr420 0x00000010 25990b17f1bSmrg#define V1_COLORSPACE_SIGN 0x00000080 26090b17f1bSmrg#define V1_SRC_IS_FIELD_PIC 0x00000200 26190b17f1bSmrg#define V1_SRC_IS_FRAME_PIC 0x00000000 26290b17f1bSmrg#define V1_BOB_ENABLE 0x00400000 26390b17f1bSmrg#define V1_FIELD_BASE 0x00000000 26490b17f1bSmrg#define V1_FRAME_BASE 0x01000000 26590b17f1bSmrg#define V1_SWAP_SW 0x00000000 26690b17f1bSmrg#define V1_SWAP_HW_HQV 0x02000000 26790b17f1bSmrg#define V1_SWAP_HW_CAPTURE 0x04000000 26890b17f1bSmrg#define V1_SWAP_HW_MC 0x06000000 26990b17f1bSmrg/* #define V1_DOUBLE_BUFFERS 0x00000000 */ 27090b17f1bSmrg/* #define V1_QUADRUPLE_BUFFERS 0x18000000 */ 27190b17f1bSmrg#define V1_EXPIRE_NUM 0x00050000 27290b17f1bSmrg#define V1_EXPIRE_NUM_A 0x000a0000 27390b17f1bSmrg#define V1_EXPIRE_NUM_F 0x000f0000 /* jason */ 27490b17f1bSmrg#define V1_FIFO_EXTENDED 0x00200000 27590b17f1bSmrg#define V1_ON_PRI 0x00000000 27690b17f1bSmrg#define V1_ON_SND_DISPLAY 0x80000000 27790b17f1bSmrg#define V1_FIFO_32V1_32V2 0x00000000 27890b17f1bSmrg#define V1_FIFO_48V1_32V2 0x00200000 27990b17f1bSmrg#define V1_PREFETCH_ON_3336 0x40000000 /*V1_PREFETCH_ON*/ 28090b17f1bSmrg#define V1_GAMMA_ENABLE_3336 0x20000000 /*V1_Gamma_ENABLE*/ 28190b17f1bSmrg 28290b17f1bSmrg/* V12_QWORD_PER_LINE 0x234 */ 28390b17f1bSmrg#define V1_FETCH_COUNT 0x3ff00000 28490b17f1bSmrg#define V1_FETCHCOUNT_ALIGNMENT 0x0000000f 28590b17f1bSmrg#define V1_FETCHCOUNT_UNIT 0x00000004 /* Doubld QWORD */ 28690b17f1bSmrg 28790b17f1bSmrg/* V1_STRIDE */ 28890b17f1bSmrg#define V1_STRIDE_YMASK 0x00001fff 28990b17f1bSmrg#define V1_STRIDE_UVMASK 0x1ff00000 29090b17f1bSmrg 29190b17f1bSmrg/* V1_ZOOM_CONTROL 0x24C */ 29290b17f1bSmrg#define V1_X_ZOOM_ENABLE 0x80000000 29390b17f1bSmrg#define V1_Y_ZOOM_ENABLE 0x00008000 29490b17f1bSmrg 29590b17f1bSmrg/* V1_MINI_CONTROL 0x250 */ 29690b17f1bSmrg#define V1_X_INTERPOLY 0x00000002 /* X interpolation */ 29790b17f1bSmrg#define V1_Y_INTERPOLY 0x00000001 /* Y interpolation */ 29890b17f1bSmrg#define V1_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ 29990b17f1bSmrg#define V1_X_DIV_2 0x01000000 30090b17f1bSmrg#define V1_X_DIV_4 0x03000000 30190b17f1bSmrg#define V1_X_DIV_8 0x05000000 30290b17f1bSmrg#define V1_X_DIV_16 0x07000000 30390b17f1bSmrg#define V1_Y_DIV_2 0x00010000 30490b17f1bSmrg#define V1_Y_DIV_4 0x00030000 30590b17f1bSmrg#define V1_Y_DIV_8 0x00050000 30690b17f1bSmrg#define V1_Y_DIV_16 0x00070000 30790b17f1bSmrg 30890b17f1bSmrg/* V1_STARTADDR0 0x254 */ 30990b17f1bSmrg#define SW_FLIP_ODD 0x08000000 31090b17f1bSmrg 31190b17f1bSmrg/* V_FIFO_CONTROL 0x258 31290b17f1bSmrg * IA2 has 32 level FIFO for packet mode video format 31390b17f1bSmrg * 32 level FIFO for planar mode video YV12. with extension reg 230 bit 21 enable 31490b17f1bSmrg * 16 level FIFO for planar mode video YV12. with extension reg 230 bit 21 disable 31590b17f1bSmrg * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 31690b17f1bSmrg */ 31790b17f1bSmrg#define V1_FIFO_DEPTH12 0x0000000B 31890b17f1bSmrg#define V1_FIFO_DEPTH16 0x0000000F 31990b17f1bSmrg#define V1_FIFO_DEPTH32 0x0000001F 32090b17f1bSmrg#define V1_FIFO_DEPTH48 0x0000002F 32190b17f1bSmrg#define V1_FIFO_DEPTH64 0x0000003F 32290b17f1bSmrg#define V1_FIFO_THRESHOLD6 0x00000600 32390b17f1bSmrg#define V1_FIFO_THRESHOLD8 0x00000800 32490b17f1bSmrg#define V1_FIFO_THRESHOLD12 0x00000C00 32590b17f1bSmrg#define V1_FIFO_THRESHOLD16 0x00001000 32690b17f1bSmrg#define V1_FIFO_THRESHOLD24 0x00001800 32790b17f1bSmrg#define V1_FIFO_THRESHOLD32 0x00002000 32890b17f1bSmrg#define V1_FIFO_THRESHOLD40 0x00002800 32990b17f1bSmrg#define V1_FIFO_THRESHOLD48 0x00003000 33090b17f1bSmrg#define V1_FIFO_THRESHOLD56 0x00003800 33190b17f1bSmrg#define V1_FIFO_THRESHOLD61 0x00003D00 33290b17f1bSmrg#define V1_FIFO_PRETHRESHOLD10 0x0A000000 33390b17f1bSmrg#define V1_FIFO_PRETHRESHOLD12 0x0C000000 33490b17f1bSmrg#define V1_FIFO_PRETHRESHOLD29 0x1d000000 33590b17f1bSmrg#define V1_FIFO_PRETHRESHOLD40 0x28000000 33690b17f1bSmrg#define V1_FIFO_PRETHRESHOLD44 0x2c000000 33790b17f1bSmrg#define V1_FIFO_PRETHRESHOLD56 0x38000000 33890b17f1bSmrg#define V1_FIFO_PRETHRESHOLD61 0x3D000000 33990b17f1bSmrg 34090b17f1bSmrg#define VIDEO_FIFO_DEPTH_VT3336 225 34190b17f1bSmrg#define VIDEO_FIFO_THRESHOLD_VT3336 200 34290b17f1bSmrg#define VIDEO_FIFO_PRETHRESHOLD_VT3336 250 34390b17f1bSmrg#define VIDEO_EXPIRE_NUM_VT3336 31 34490b17f1bSmrg 34590b17f1bSmrg/* Those values are only valid for IGA1 */ 34690b17f1bSmrg#define VIDEO_FIFO_DEPTH_VT3409 400 34790b17f1bSmrg#define VIDEO_FIFO_THRESHOLD_VT3409 320 34890b17f1bSmrg#define VIDEO_FIFO_PRETHRESHOLD_VT3409 230 34990b17f1bSmrg#define VIDEO_EXPIRE_NUM_VT3409 160 35090b17f1bSmrg 35190b17f1bSmrg/* ALPHA_V3_FIFO_CONTROL 0x278 35290b17f1bSmrg * IA2 has 32 level FIFO for packet mode video format 35390b17f1bSmrg * 32 level FIFO for planar mode video YV12. with extension reg 230 bit 21 enable 35490b17f1bSmrg * 16 level FIFO for planar mode video YV12. with extension reg 230 bit 21 disable 35590b17f1bSmrg * 8 level FIFO for ALPHA 35690b17f1bSmrg * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 35790b17f1bSmrg */ 35890b17f1bSmrg#define V3_FIFO_DEPTH16 0x0000000F 35990b17f1bSmrg#define V3_FIFO_DEPTH24 0x00000017 36090b17f1bSmrg#define V3_FIFO_DEPTH32 0x0000001F 36190b17f1bSmrg#define V3_FIFO_DEPTH48 0x0000002F 36290b17f1bSmrg#define V3_FIFO_DEPTH64 0x0000003F 36390b17f1bSmrg#define V3_FIFO_THRESHOLD8 0x00000800 36490b17f1bSmrg#define V3_FIFO_THRESHOLD12 0x00000C00 36590b17f1bSmrg#define V3_FIFO_THRESHOLD16 0x00001000 36690b17f1bSmrg#define V3_FIFO_THRESHOLD24 0x00001800 36790b17f1bSmrg#define V3_FIFO_THRESHOLD29 0x00001D00 36890b17f1bSmrg#define V3_FIFO_THRESHOLD32 0x00002000 36990b17f1bSmrg#define V3_FIFO_THRESHOLD40 0x00002800 37090b17f1bSmrg#define V3_FIFO_THRESHOLD48 0x00003000 37190b17f1bSmrg#define V3_FIFO_THRESHOLD56 0x00003800 37290b17f1bSmrg#define V3_FIFO_THRESHOLD61 0x00003D00 37390b17f1bSmrg#define V3_FIFO_PRETHRESHOLD10 0x0000000A 37490b17f1bSmrg#define V3_FIFO_PRETHRESHOLD12 0x0000000C 37590b17f1bSmrg#define V3_FIFO_PRETHRESHOLD29 0x0000001d 37690b17f1bSmrg#define V3_FIFO_PRETHRESHOLD40 0x00000028 37790b17f1bSmrg#define V3_FIFO_PRETHRESHOLD44 0x0000002c 37890b17f1bSmrg#define V3_FIFO_PRETHRESHOLD56 0x00000038 37990b17f1bSmrg#define V3_FIFO_PRETHRESHOLD61 0x0000003D 38090b17f1bSmrg#define V3_FIFO_MASK 0x0000007F 38190b17f1bSmrg#define V3_FIFO_MASK_3314 0x000000FF 38290b17f1bSmrg#define ALPHA_FIFO_DEPTH8 0x00070000 38390b17f1bSmrg#define ALPHA_FIFO_THRESHOLD4 0x04000000 38490b17f1bSmrg#define ALPHA_FIFO_MASK 0xffff0000 38590b17f1bSmrg#define ALPHA_FIFO_PRETHRESHOLD4 0x00040000 38690b17f1bSmrg 38790b17f1bSmrg/* IA2 */ 38890b17f1bSmrg#define ColorSpaceValue_1 0x140020f2 38990b17f1bSmrg#define ColorSpaceValue_2 0x0a0a2c00 39090b17f1bSmrg 39190b17f1bSmrg#define ColorSpaceValue_1_3123C0 0x13000DED 39290b17f1bSmrg#define ColorSpaceValue_2_3123C0 0x13171000 39390b17f1bSmrg#define ColorSpaceValue_1_32045 0x13000DED 39490b17f1bSmrg#define ColorSpaceValue_2_32045 0x13171000 39590b17f1bSmrg 39690b17f1bSmrg/* For TV setting */ 39790b17f1bSmrg#define ColorSpaceValue_1TV 0x140020f2 39890b17f1bSmrg#define ColorSpaceValue_2TV 0x0a0a2c00 39990b17f1bSmrg 40090b17f1bSmrg/* V_COMPOSE_MODE 0x298 */ 40190b17f1bSmrg#define SELECT_VIDEO_IF_COLOR_KEY 0x00000001 /* select video if (color key),otherwise select graphics */ 40290b17f1bSmrg#define SELECT_VIDEO3_IF_COLOR_KEY 0x00000020 /* For 3123C0, select video3 if (color key),otherwise select graphics */ 40390b17f1bSmrg#define SELECT_VIDEO_IF_CHROMA_KEY 0x00000002 /* 0x0000000a //select video if (chroma key ),otherwise select graphics */ 40490b17f1bSmrg#define ALWAYS_SELECT_VIDEO 0x00000000 /* always select video,Chroma key and Color key disable */ 40590b17f1bSmrg#define COMPOSE_V1_V3 0x00000000 /* V1 on top of V3 */ 40690b17f1bSmrg#define COMPOSE_V3_V1 0x00100000 /* V3 on top of V1 */ 40790b17f1bSmrg#define COMPOSE_V1_TOP 0x00000000 40890b17f1bSmrg#define COMPOSE_V3_TOP 0x00100000 40990b17f1bSmrg#define V1_COMMAND_FIRE 0x80000000 /* V1 commands fire */ 41090b17f1bSmrg#define V3_COMMAND_FIRE 0x40000000 /* V3 commands fire */ 41190b17f1bSmrg#define V_COMMAND_LOAD 0x20000000 /* Video register always loaded */ 41290b17f1bSmrg#define V_COMMAND_LOAD_VBI 0x10000000 /* Video register always loaded at vbi without waiting source flip */ 41390b17f1bSmrg#define V3_COMMAND_LOAD 0x08000000 /* CLE_C0 Video3 register always loaded */ 41490b17f1bSmrg#define V3_COMMAND_LOAD_VBI 0x00000100 /* CLE_C0 Video3 register always loaded at vbi without waiting source flip */ 41590b17f1bSmrg#define SECOND_DISPLAY_COLOR_KEY_ENABLE 0x00010000 41690b17f1bSmrg 41790b17f1bSmrg/* V3_ZOOM_CONTROL 0x2bc */ 41890b17f1bSmrg#define V3_X_ZOOM_ENABLE 0x80000000 41990b17f1bSmrg#define V3_Y_ZOOM_ENABLE 0x00008000 42090b17f1bSmrg 42190b17f1bSmrg/* V3_MINI_CONTROL 0x2c0 */ 42290b17f1bSmrg#define V3_X_INTERPOLY 0x00000002 /* X interpolation */ 42390b17f1bSmrg#define V3_Y_INTERPOLY 0x00000001 /* Y interpolation */ 42490b17f1bSmrg#define V3_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ 42590b17f1bSmrg#define V3_X_DIV_2 0x01000000 42690b17f1bSmrg#define V3_X_DIV_4 0x03000000 42790b17f1bSmrg#define V3_X_DIV_8 0x05000000 42890b17f1bSmrg#define V3_X_DIV_16 0x07000000 42990b17f1bSmrg#define V3_Y_DIV_2 0x00010000 43090b17f1bSmrg#define V3_Y_DIV_4 0x00030000 43190b17f1bSmrg#define V3_Y_DIV_8 0x00050000 43290b17f1bSmrg#define V3_Y_DIV_16 0x00070000 43390b17f1bSmrg 43490b17f1bSmrg/* SUBP_CONTROL_STRIDE 0x3c0 */ 43590b17f1bSmrg#define SUBP_HQV_ENABLE 0x00010000 43690b17f1bSmrg#define SUBP_IA44 0x00020000 43790b17f1bSmrg#define SUBP_AI44 0x00000000 43890b17f1bSmrg#define SUBP_STRIDE_MASK 0x00001fff 43990b17f1bSmrg#define SUBP_CONTROL_MASK 0x00070000 44090b17f1bSmrg 44190b17f1bSmrg/* RAM_TABLE_CONTROL 0x3c8 */ 44290b17f1bSmrg#define RAM_TABLE_RGB_ENABLE 0x00000007 44390b17f1bSmrg 44490b17f1bSmrg/* CAPTURE0_CONTROL 0x310 */ 44590b17f1bSmrg#define C0_ENABLE 0x00000001 44690b17f1bSmrg#define BUFFER_2_MODE 0x00000000 44790b17f1bSmrg#define BUFFER_3_MODE 0x00000004 44890b17f1bSmrg#define BUFFER_4_MODE 0x00000006 44990b17f1bSmrg#define SWAP_YUYV 0x00000000 45090b17f1bSmrg#define SWAP_UYVY 0x00000100 45190b17f1bSmrg#define SWAP_YVYU 0x00000200 45290b17f1bSmrg#define SWAP_VYUY 0x00000300 45390b17f1bSmrg#define IN_601_8 0x00000000 45490b17f1bSmrg#define IN_656_8 0x00000010 45590b17f1bSmrg#define IN_601_16 0x00000020 45690b17f1bSmrg#define IN_656_16 0x00000030 45790b17f1bSmrg#define DEINTER_ODD 0x00000000 45890b17f1bSmrg#define DEINTER_EVEN 0x00001000 45990b17f1bSmrg#define DEINTER_ODD_EVEN 0x00002000 46090b17f1bSmrg#define DEINTER_FRAME 0x00003000 46190b17f1bSmrg#define VIP_1 0x00000000 46290b17f1bSmrg#define VIP_2 0x00000400 46390b17f1bSmrg#define H_FILTER_2 0x00010000 46490b17f1bSmrg#define H_FILTER_4 0x00020000 46590b17f1bSmrg#define H_FILTER_8_1331 0x00030000 46690b17f1bSmrg#define H_FILTER_8_12221 0x00040000 46790b17f1bSmrg#define VIP_ENABLE 0x00000008 46890b17f1bSmrg#define EN_FIELD_SIG 0x00000800 46990b17f1bSmrg#define VREF_INVERT 0x00100000 47090b17f1bSmrg#define FIELD_INPUT_INVERSE 0x00400000 47190b17f1bSmrg#define FIELD_INVERSE 0x40000000 47290b17f1bSmrg 47390b17f1bSmrg#define C1_H_MINI_EN 0x00000800 47490b17f1bSmrg#define C0_H_MINI_EN 0x00000800 47590b17f1bSmrg#define C1_V_MINI_EN 0x04000000 47690b17f1bSmrg#define C0_V_MINI_EN 0x04000000 47790b17f1bSmrg#define C1_H_MINI_2 0x00000400 47890b17f1bSmrg 47990b17f1bSmrg/* CAPTURE1_CONTROL 0x354 */ 48090b17f1bSmrg#define C1_ENABLE 0x00000001 48190b17f1bSmrg 48290b17f1bSmrg/* V3_CONTROL 0x2A0 */ 48390b17f1bSmrg#define V3_ENABLE 0x00000001 48490b17f1bSmrg#define V3_FULL_SCREEN 0x00000002 48590b17f1bSmrg#define V3_YUV422 0x00000000 48690b17f1bSmrg#define V3_RGB32 0x00000004 48790b17f1bSmrg#define V3_RGB15 0x00000008 48890b17f1bSmrg#define V3_RGB16 0x0000000C 48990b17f1bSmrg#define V3_COLORSPACE_SIGN 0x00000080 49090b17f1bSmrg#define V3_EXPIRE_NUM 0x00040000 49190b17f1bSmrg#define V3_EXPIRE_NUM_F 0x000f0000 49290b17f1bSmrg#define V3_EXPIRE_NUM_3204 0x00100000 49390b17f1bSmrg#define V3_EXPIRE_NUM_3205 0x00080000 49490b17f1bSmrg#define V3_BOB_ENABLE 0x00400000 49590b17f1bSmrg#define V3_FIELD_BASE 0x00000000 49690b17f1bSmrg#define V3_FRAME_BASE 0x01000000 49790b17f1bSmrg#define V3_SWAP_SW 0x00000000 49890b17f1bSmrg#define V3_SWAP_HW_HQV 0x02000000 49990b17f1bSmrg#define V3_FLIP_HW_CAPTURE0 0x04000000 50090b17f1bSmrg#define V3_FLIP_HW_CAPTURE1 0x06000000 50190b17f1bSmrg 50290b17f1bSmrg/* V3_ALPHA_FETCH_COUNT 0x2B8 */ 50390b17f1bSmrg#define V3_FETCH_COUNT 0x3ff00000 50490b17f1bSmrg#define ALPHA_FETCH_COUNT 0x000003ff 50590b17f1bSmrg 50690b17f1bSmrg/* HQV_CONTROL 0x3D0 */ 50790b17f1bSmrg#define HQV_RGB32 0x00000000 50890b17f1bSmrg#define HQV_RGB16 0x20000000 50990b17f1bSmrg#define HQV_RGB15 0x30000000 51090b17f1bSmrg#define HQV_YUV422 0x80000000 51190b17f1bSmrg#define HQV_YUV420 0xC0000000 51290b17f1bSmrg#define HQV_ENABLE 0x08000000 51390b17f1bSmrg#define HQV_SRC_SW 0x00000000 51490b17f1bSmrg#define HQV_SRC_MC 0x01000000 51590b17f1bSmrg#define HQV_SRC_CAPTURE0 0x02000000 51690b17f1bSmrg#define HQV_SRC_CAPTURE1 0x03000000 51790b17f1bSmrg#define HQV_FLIP_EVEN 0x00000000 51890b17f1bSmrg#define HQV_FLIP_ODD 0x00000020 51990b17f1bSmrg#define HQV_SW_FLIP 0x00000010 /* Write 1 to flip HQV buffer */ 52090b17f1bSmrg#define HQV_DEINTERLACE 0x00010000 /* First line of odd field will be repeated 3 times */ 52190b17f1bSmrg#define HQV_FIELD_2_FRAME 0x00020000 /* Src is field. Display each line 2 times */ 52290b17f1bSmrg#define HQV_FRAME_2_FIELD 0x00040000 /* Src is field. Display field */ 52390b17f1bSmrg#define HQV_FRAME_UV 0x00000000 /* Src is Non-interleaved */ 52490b17f1bSmrg#define HQV_FIELD_UV 0x00100000 /* Src is interleaved */ 52590b17f1bSmrg#define HQV_IDLE 0x00000008 52690b17f1bSmrg#define HQV_FLIP_STATUS 0x00000001 52790b17f1bSmrg#define HQV_DOUBLE_BUFF 0x00000000 52890b17f1bSmrg#define HQV_TRIPLE_BUFF 0x04000000 52990b17f1bSmrg#define HQV_SUBPIC_FLIP 0x00008000 53090b17f1bSmrg#define HQV_FIFO_STATUS 0x00001000 53190b17f1bSmrg#define HQV_GEN_IRQ 0x00000080 53290b17f1bSmrg#define HQV_FIFO_DEPTH_1 0x00010000 53390b17f1bSmrg/* for CME engine */ 53490b17f1bSmrg#define HQV_SW_FLIP_QUEUE_ENABLE 0x00100000 53590b17f1bSmrg 53690b17f1bSmrg/* for hwDiff->dwNewScaleCtl */ 53790b17f1bSmrg#define HQV_H_SCALE_ENABLE 0x80000000 53890b17f1bSmrg#define HQV_H_SCALE_UP 0x00000000 53990b17f1bSmrg#define HQV_H_SCALE_DOWN_FOURTH_TO_1 0x10000000 54090b17f1bSmrg#define HQV_H_SCALE_DOWN_FOURTH_TO_EIGHTH 0x20000000 54190b17f1bSmrg#define HQV_H_SCALE_DOWN_UNDER_EIGHTH 0x30000000 54290b17f1bSmrg 54390b17f1bSmrg#define HQV_V_SCALE_ENABLE 0x80000000 54490b17f1bSmrg#define HQV_V_SCALE_UP 0x00000000 54590b17f1bSmrg#define HQV_V_SCALE_DOWN 0x10000000 54690b17f1bSmrg 54790b17f1bSmrg/* HQV Default Vodeo Color 0x3B8 */ 54890b17f1bSmrg#define HQV_FIX_COLOR 0x0643212c 54990b17f1bSmrg 55090b17f1bSmrg/* HQV_FILTER_CONTROL 0x3E4 */ 55190b17f1bSmrg#define HQV_H_LOWPASS_2TAP 0x00000001 55290b17f1bSmrg#define HQV_H_LOWPASS_4TAP 0x00000002 55390b17f1bSmrg#define HQV_H_LOWPASS_8TAP1 0x00000003 /* To be deleted */ 55490b17f1bSmrg#define HQV_H_LOWPASS_8TAP2 0x00000004 /* To be deleted */ 55590b17f1bSmrg#define HQV_H_HIGH_PASS 0x00000008 55690b17f1bSmrg#define HQV_H_LOW_PASS 0x00000000 55790b17f1bSmrg#define HQV_V_LOWPASS_2TAP 0x00010000 55890b17f1bSmrg#define HQV_V_LOWPASS_4TAP 0x00020000 55990b17f1bSmrg#define HQV_V_LOWPASS_8TAP1 0x00030000 56090b17f1bSmrg#define HQV_V_LOWPASS_8TAP2 0x00040000 56190b17f1bSmrg#define HQV_V_HIGH_PASS 0x00080000 56290b17f1bSmrg#define HQV_V_LOW_PASS 0x00000000 56390b17f1bSmrg#define HQV_H_HIPASS_F1_DEFAULT 0x00000040 56490b17f1bSmrg#define HQV_H_HIPASS_F2_DEFAULT 0x00000000 56590b17f1bSmrg#define HQV_V_HIPASS_F1_DEFAULT 0x00400000 56690b17f1bSmrg#define HQV_V_HIPASS_F2_DEFAULT 0x00000000 56790b17f1bSmrg#define HQV_H_HIPASS_F1_2TAP 0x00000050 56890b17f1bSmrg#define HQV_H_HIPASS_F2_2TAP 0x00000100 56990b17f1bSmrg#define HQV_V_HIPASS_F1_2TAP 0x00500000 57090b17f1bSmrg#define HQV_V_HIPASS_F2_2TAP 0x01000000 57190b17f1bSmrg#define HQV_H_HIPASS_F1_4TAP 0x00000060 57290b17f1bSmrg#define HQV_H_HIPASS_F2_4TAP 0x00000200 57390b17f1bSmrg#define HQV_V_HIPASS_F1_4TAP 0x00600000 57490b17f1bSmrg#define HQV_V_HIPASS_F2_4TAP 0x02000000 57590b17f1bSmrg#define HQV_H_HIPASS_F1_8TAP 0x00000080 57690b17f1bSmrg#define HQV_H_HIPASS_F2_8TAP 0x00000400 57790b17f1bSmrg#define HQV_V_HIPASS_F1_8TAP 0x00800000 57890b17f1bSmrg#define HQV_V_HIPASS_F2_8TAP 0x04000000 57990b17f1bSmrg/* IA2 NEW */ 58090b17f1bSmrg#define HQV_V_FILTER2 0x00080000 58190b17f1bSmrg#define HQV_H_FILTER2 0x00000008 58290b17f1bSmrg#define HQV_H_TAP2_11 0x00000041 58390b17f1bSmrg#define HQV_H_TAP4_121 0x00000042 58490b17f1bSmrg#define HQV_H_TAP4_1111 0x00000401 58590b17f1bSmrg#define HQV_H_TAP8_1331 0x00000221 58690b17f1bSmrg#define HQV_H_TAP8_12221 0x00000402 58790b17f1bSmrg#define HQV_H_TAP16_1991 0x00000159 58890b17f1bSmrg#define HQV_H_TAP16_141041 0x0000026A 58990b17f1bSmrg#define HQV_H_TAP32 0x0000015A 59090b17f1bSmrg#define HQV_V_TAP2_11 0x00410000 59190b17f1bSmrg#define HQV_V_TAP4_121 0x00420000 59290b17f1bSmrg#define HQV_V_TAP4_1111 0x04010000 59390b17f1bSmrg#define HQV_V_TAP8_1331 0x02210000 59490b17f1bSmrg#define HQV_V_TAP8_12221 0x04020000 59590b17f1bSmrg#define HQV_V_TAP16_1991 0x01590000 59690b17f1bSmrg#define HQV_V_TAP16_141041 0x026A0000 59790b17f1bSmrg#define HQV_V_TAP32 0x015A0000 59890b17f1bSmrg#define HQV_V_FILTER_DEFAULT 0x00420000 59990b17f1bSmrg#define HQV_H_FILTER_DEFAULT 0x00000040 60090b17f1bSmrg 60190b17f1bSmrg/* HQV_MINI_CONTROL 0x3E8 */ 60290b17f1bSmrg#define HQV_H_MINIFY_ENABLE 0x00000800 60390b17f1bSmrg#define HQV_H_MINIFY_DOWN 0x00001000 60490b17f1bSmrg#define HQV_V_MINIFY_ENABLE 0x08000000 60590b17f1bSmrg#define HQV_V_MINIFY_DOWN 0x10000000 60690b17f1bSmrg#define HQV_VDEBLOCK_FILTER 0x80000000 60790b17f1bSmrg#define HQV_HDEBLOCK_FILTER 0x00008000 60890b17f1bSmrg 60990b17f1bSmrg/* new added registers for VT3409.For some registers have different meanings 61090b17f1bSmrg * but the same address,we add postfix _409 to distinguish */ 61190b17f1bSmrg#define HQV_COLOR_ADJUSTMENT_PRE_CTRL1 0x360 61290b17f1bSmrg#define HQV_COLOR_ADJUSTMENT_PRE_CTRL2 0x364 61390b17f1bSmrg#define HQV_COLOR_ADJUSTMENT_PRE_CTRL3 0x368 61490b17f1bSmrg#define HQV_COLOR_ADJUSTMENT_PRE_CTRL4 0x36C 61590b17f1bSmrg#define HQV_SRC_DATA_OFFSET_CTRL1_409 0x370 61690b17f1bSmrg#define HQV_SRC_DATA_OFFSET_CTRL2_409 0x374 61790b17f1bSmrg#define HQV_SRC_DATA_OFFSET_CTRL3_409 0x378 61890b17f1bSmrg#define HQV_SRC_DATA_OFFSET_CTRL4_409 0x37C 61990b17f1bSmrg#define HQV_DST_DATA_OFFSET_CTRL1 0x380 62090b17f1bSmrg#define HQV_DST_DATA_OFFSET_CTRL2 0x384 62190b17f1bSmrg#define HQV_DST_DATA_OFFSET_CTRL3 0x388 62290b17f1bSmrg#define HQV_DST_DATA_OFFSET_CTRL4 0x38C 62390b17f1bSmrg#define HQV_SHARPNESS_DECODER_HANDSHAKE_CTRL_410 0x3A4 62490b17f1bSmrg#define HQV_RESIDUE_PIXEL_FRAME_STARTADDR 0x3BC 62590b17f1bSmrg#define HQV_BACKGROUND_DATA_OFFSET 0x3CC 62690b17f1bSmrg#define HQV_SUBP_HSCALE_CTRL 0x3E0 62790b17f1bSmrg#define HQV_SUBP_VSCALE_CTRL 0x3E8 62890b17f1bSmrg 62990b17f1bSmrg/* Add new HQV Registers for VT3353: */ 63090b17f1bSmrg#define HQV_SRC_DATA_OFFSET_CONTROL1 0x380 63190b17f1bSmrg#define HQV_SRC_DATA_OFFSET_CONTROL2 0x384 63290b17f1bSmrg#define HQV_SRC_DATA_OFFSET_CONTROL3 0x388 63390b17f1bSmrg#define HQV_SRC_DATA_OFFSET_CONTROL4 0x38C 63490b17f1bSmrg#define HQV_HW_TUNING_PERFORMANCE 0x390 63590b17f1bSmrg#define HQV_EXTENDED_CONTROL 0x394 63690b17f1bSmrg#define HQV_STATIC_RECORD_FB_STARTADDR 0x398 63790b17f1bSmrg#define HQV_STATIC_RECORD_FB_STRIDE 0x39C 63890b17f1bSmrg#define HQV_COLOR_ADJUSTMENT_CONTROL1 0x3A0 63990b17f1bSmrg#define HQV_COLOR_ADJUSTMENT_CONTROL2 0x3A4 64090b17f1bSmrg#define HQV_COLOR_ADJUSTMENT_CONTROL3 0x3A8 64190b17f1bSmrg#define HQV_COLOR_ADJUSTMENT_CONTROL5 0x3AC 64290b17f1bSmrg#define HQV_DEFAULT_VIDEO_COLOR 0x3B8 64390b17f1bSmrg 64490b17f1bSmrg#define CHROMA_KEY_LOW 0x00FFFFFF 64590b17f1bSmrg#define CHROMA_KEY_HIGH 0x00FFFFFF 64690b17f1bSmrg 64790b17f1bSmrg/* V_CAP_STATUS */ 64890b17f1bSmrg#define V_ST_UPDATE_NOT_YET 0x00000003 64990b17f1bSmrg#define V1_ST_UPDATE_NOT_YET 0x00000001 65090b17f1bSmrg#define V3_ST_UPDATE_NOT_YET 0x00000008 65190b17f1bSmrg 65290b17f1bSmrg#define VBI_STATUS 0x00000002 65390b17f1bSmrg 65490b17f1bSmrg/* 65590b17f1bSmrg * Macros for Video MMIO 65690b17f1bSmrg */ 65790b17f1bSmrg#ifndef V4L2 65890b17f1bSmrg#define MPGOutD(port, data) *((volatile CARD32 *)(pVia->MpegMapBase +(port))) = (data) 65990b17f1bSmrg#define MPGInD(port) *((volatile CARD32 *)(pVia->MpegMapBase +(port))) 66090b17f1bSmrg#endif 66190b17f1bSmrg 66290b17f1bSmrg/* 66390b17f1bSmrg * Macros for GE MMIO 66490b17f1bSmrg */ 66590b17f1bSmrg#define GEInW(port) *((volatile CARD16 *)(lpGEMMIO + (port))) 66690b17f1bSmrg#define GEInD(port) *((volatile CARD32 *)(lpGEMMIO + (port))) 66790b17f1bSmrg#define GEOutW(port, data) *((volatile CARD16 *)(lpGEMMIO + (port))) = (data) 66890b17f1bSmrg#define GEOutD(port, data) *((volatile CARD32 *)(lpGEMMIO + (port))) = (data) 66990b17f1bSmrg 67090b17f1bSmrg/* 67190b17f1bSmrg * MPEG 1/2 Slice Engine (at 0xC00 relative to base) 67290b17f1bSmrg */ 67390b17f1bSmrg 67490b17f1bSmrg#define MPG_CONTROL 0x00 67590b17f1bSmrg#define MPG_CONTROL_STRUCT 0x03 67690b17f1bSmrg#define MPG_CONTROL_STRUCT_TOP 0x01 67790b17f1bSmrg#define MPG_CONTROL_STRUCT_BOTTOM 0x02 67890b17f1bSmrg#define MPG_CONTROL_STRUCT_FRAME 0x03 67990b17f1bSmrg /* Use TOP if interlaced */ 68090b17f1bSmrg#define MPG_CONTROL_TYPE 0x3C 68190b17f1bSmrg#define MPG_CONTROL_TYPE_I (0x01 << 2) 68290b17f1bSmrg#define MPG_CONTROL_TYPE_B (0x02 << 2) 68390b17f1bSmrg#define MPG_CONTROL_TYPE_P (0x03 << 3) 68490b17f1bSmrg#define MPG_CONTROL_ALTSCAN 0x40 68590b17f1bSmrg#define MPG_BLOCK 0x08 /* Unsure */ 68690b17f1bSmrg#define MPG_COMMAND 0x0C 68790b17f1bSmrg#define MPG_DATA1 0x10 68890b17f1bSmrg#define MPG_DATA2 0x14 68990b17f1bSmrg#define MPG_DATA3 0x18 69090b17f1bSmrg#define MPG_DATA4 0x1C 69190b17f1bSmrg 69290b17f1bSmrg#define MPG_YPHYSICAL(x) (0x20 + 12*(x)) 69390b17f1bSmrg#define MPG_CbPHYSICAL(x) (0x24 + 12*(x)) 69490b17f1bSmrg#define MPG_CrPHYSICAL(x) (0x28 + 12*(x)) 69590b17f1bSmrg 69690b17f1bSmrg#define MPG_PITCH 0x50 69790b17f1bSmrg#define MPG_STATUS 0x54 69890b17f1bSmrg 69990b17f1bSmrg#define MPG_MATRIX_IDX 0x5C 70090b17f1bSmrg#define MPG_MATRIX_IDX_INTRA 0x00 70190b17f1bSmrg#define MPG_MATRIX_IDX_NON 0x01 70290b17f1bSmrg#define MPG_MATRIX_DATA 0x60 70390b17f1bSmrg 70490b17f1bSmrg#define MPG_SLICE_CTRL_1 0x90 70590b17f1bSmrg#define MPG_SLICE_MBAMAX 0x2FFF 70690b17f1bSmrg#define MPG_SLICE_PREDICTIVE_DCT 0x4000 70790b17f1bSmrg#define MPG_SLICE_TOP_FIRST 0x8000 70890b17f1bSmrg#define MPG_SLICE_MACROBLOCK_WIDTH(x) ((x)<<18) /* in 64's */ 70990b17f1bSmrg#define MPG_SLICE_CTRL_2 0x94 71090b17f1bSmrg#define MPG_SLICE_CONCEAL_MVEC 0x0000001 71190b17f1bSmrg#define MPG_SLICE_QSCALE_TYPE 0x0000002 71290b17f1bSmrg#define MPG_SLICE_DCPRECISION 0x000000C 71390b17f1bSmrg#define MPG_SLICE_MACROBQUOT 0x0FFFFF0 71490b17f1bSmrg#define MPG_SLICE_INTRAVLC 0x1000000 71590b17f1bSmrg#define MPG_SLICE_CTRL_3 0x98 71690b17f1bSmrg#define MPG_SLICE_FHMVR 0x0000003 71790b17f1bSmrg#define MPG_SLICE_FVMVR 0x000000C 71890b17f1bSmrg#define MPG_SLICE_BHMVR 0x0000030 71990b17f1bSmrg#define MPG_SLICE_BVMVR 0x00000C0 72090b17f1bSmrg#define MPG_SLICE_SECOND_FIELD 0x0100000 72190b17f1bSmrg#define MPG_SLICE_RESET 0x0400000 72290b17f1bSmrg#define MPG_SLICE_LENGTH 0x9C 72390b17f1bSmrg#define MPG_SLICE_DATA 0xA0 72490b17f1bSmrg 72590b17f1bSmrg#ifdef HAVE_PCIACCESS 72690b17f1bSmrg#define VIA_MEMBASE(p,n) (p)->regions[(n)].base_addr 72790b17f1bSmrg#define VENDOR_ID(p) (p)->vendor_id 72890b17f1bSmrg#define DEVICE_ID(p) (p)->device_id 72990b17f1bSmrg#define SUBVENDOR_ID(p) (p)->subvendor_id 73090b17f1bSmrg#define SUBSYS_ID(p) (p)->subdevice_id 73190b17f1bSmrg#define CHIP_REVISION(p) (p)->revision 73290b17f1bSmrg#else 73390b17f1bSmrg#define VIA_MEMBASE(p,n) (p)->memBase[n] 73490b17f1bSmrg#define VENDOR_ID(p) (p)->vendor 73590b17f1bSmrg#define DEVICE_ID(p) (p)->chipType 73690b17f1bSmrg#define SUBVENDOR_ID(p) (p)->subsysVendor 73790b17f1bSmrg#define SUBSYS_ID(p) (p)->subsysCard 73890b17f1bSmrg#define CHIP_REVISION(p) (p)->chipRev 73990b17f1bSmrg#endif 74090b17f1bSmrg 74190b17f1bSmrg#endif /* _VIA_ENG_REGS_H_ */ 742