1c582b7e3Smrg/*
2c582b7e3Smrg * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
3c582b7e3Smrg *                      Precision Insight, Inc., Cedar Park, Texas, and
4c582b7e3Smrg *                      VA Linux Systems Inc., Fremont, California.
5c582b7e3Smrg *
6c582b7e3Smrg * All Rights Reserved.
7c582b7e3Smrg *
8c582b7e3Smrg * Permission is hereby granted, free of charge, to any person obtaining
9c582b7e3Smrg * a copy of this software and associated documentation files (the
10c582b7e3Smrg * "Software"), to deal in the Software without restriction, including
11c582b7e3Smrg * without limitation on the rights to use, copy, modify, merge,
12c582b7e3Smrg * publish, distribute, sublicense, and/or sell copies of the Software,
13c582b7e3Smrg * and to permit persons to whom the Software is furnished to do so,
14c582b7e3Smrg * subject to the following conditions:
15c582b7e3Smrg *
16c582b7e3Smrg * The above copyright notice and this permission notice (including the
17c582b7e3Smrg * next paragraph) shall be included in all copies or substantial
18c582b7e3Smrg * portions of the Software.
19c582b7e3Smrg *
20c582b7e3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21c582b7e3Smrg * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22c582b7e3Smrg * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
23c582b7e3Smrg * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
24c582b7e3Smrg * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
25c582b7e3Smrg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
26c582b7e3Smrg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
27c582b7e3Smrg * OTHER DEALINGS IN THE SOFTWARE.
28c582b7e3Smrg */
29c582b7e3Smrg
30c582b7e3Smrg/*
31c582b7e3Smrg * Authors:
32c582b7e3Smrg *   Kevin E. Martin <martin@valinux.com>
33c582b7e3Smrg *   Rickard E. Faith <faith@valinux.com>
34c582b7e3Smrg *   Gareth Hughes <gareth@valinux.com>
35c582b7e3Smrg *
36c582b7e3Smrg */
37c582b7e3Smrg
38c582b7e3Smrg#ifndef _R128_DRI_
39c582b7e3Smrg#define _R128_DRI_
40c582b7e3Smrg
41c582b7e3Smrg#include "xf86drm.h"
42c582b7e3Smrg
43c582b7e3Smrg/* DRI Driver defaults */
44c582b7e3Smrg#define R128_DEFAULT_CCE_PIO_MODE R128_PM4_64PIO_64VCBM_64INDBM
45c582b7e3Smrg#define R128_DEFAULT_CCE_BM_MODE  R128_PM4_64BM_64VCBM_64INDBM
46c582b7e3Smrg#define R128_DEFAULT_AGP_MODE     1
47c582b7e3Smrg#define R128_DEFAULT_AGP_SIZE     8 /* MB (must be a power of 2 and > 4MB) */
48c582b7e3Smrg#define R128_DEFAULT_RING_SIZE    1 /* MB (must be page aligned) */
49c582b7e3Smrg#define R128_DEFAULT_BUFFER_SIZE  2 /* MB (must be page aligned) */
50c582b7e3Smrg#define R128_DEFAULT_AGP_TEX_SIZE 1 /* MB (must be page aligned) */
51c582b7e3Smrg
52c582b7e3Smrg#define R128_DEFAULT_CCE_TIMEOUT  10000  /* usecs */
53c582b7e3Smrg
54c582b7e3Smrg#define R128_AGP_MAX_MODE         4
55c582b7e3Smrg
56c582b7e3Smrg#define R128_CARD_TYPE_R128          1
57c582b7e3Smrg#define R128_CARD_TYPE_R128_PRO      2
58c582b7e3Smrg#define R128_CARD_TYPE_R128_MOBILITY 3
59c582b7e3Smrg
60c582b7e3Smrg#define R128CCE_USE_RING_BUFFER(m)                                        \
61c582b7e3Smrg(((m) == R128_PM4_192BM) ||                                               \
62c582b7e3Smrg ((m) == R128_PM4_128BM_64INDBM) ||                                       \
63c582b7e3Smrg ((m) == R128_PM4_64BM_128INDBM) ||                                       \
64c582b7e3Smrg ((m) == R128_PM4_64BM_64VCBM_64INDBM))
65c582b7e3Smrg
66c582b7e3Smrgtypedef struct {
67c582b7e3Smrg    /* DRI screen private data */
68c582b7e3Smrg    int           deviceID;     /* PCI device ID */
69c582b7e3Smrg    int           width;        /* Width in pixels of display */
70c582b7e3Smrg    int           height;       /* Height in scanlines of display */
71c582b7e3Smrg    int           depth;        /* Depth of display (8, 15, 16, 24) */
72c582b7e3Smrg    int           bpp;          /* Bit depth of display (8, 16, 24, 32) */
73c582b7e3Smrg
74c582b7e3Smrg    int           IsPCI;        /* Current card is a PCI card */
75c582b7e3Smrg    int           AGPMode;
76c582b7e3Smrg
77c582b7e3Smrg    int           frontOffset;  /* Start of front buffer */
78c582b7e3Smrg    int           frontPitch;
79c582b7e3Smrg    int           backOffset;   /* Start of shared back buffer */
80c582b7e3Smrg    int           backPitch;
81c582b7e3Smrg    int           depthOffset;  /* Start of shared depth buffer */
82c582b7e3Smrg    int           depthPitch;
83c582b7e3Smrg    int           spanOffset;   /* Start of scratch spanline */
84c582b7e3Smrg    int           textureOffset;/* Start of texture data in frame buffer */
85c582b7e3Smrg    int           textureSize;
86c582b7e3Smrg    int           log2TexGran;
87c582b7e3Smrg
88c582b7e3Smrg    /* MMIO register data */
89c582b7e3Smrg    drm_handle_t     registerHandle;
90c582b7e3Smrg    drmSize       registerSize;
91c582b7e3Smrg
92c582b7e3Smrg    /* CCE AGP Texture data */
93c582b7e3Smrg    drm_handle_t     agpTexHandle;
94c582b7e3Smrg    drmSize       agpTexMapSize;
95c582b7e3Smrg    int           log2AGPTexGran;
96c582b7e3Smrg    int           agpTexOffset;
97c582b7e3Smrg    unsigned int  sarea_priv_offset;
98c582b7e3Smrg} R128DRIRec, *R128DRIPtr;
99c582b7e3Smrg
100c582b7e3Smrg#endif
101