commonregs.h revision bdcaa8d0
1/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/rendition/commonregs.h,v 1.1 1999/11/19 13:54:44 hohndel Exp $ */ 2 3#ifndef __COMMONREGS_H__ 4#define __COMMONREGS_H__ 5 6 7#define FIFO_SIZE 0x1f 8 9/* IO register offsets. */ 10#define FIFO_SWAP_NO 0x00 /* FIFO. No byte swap. */ 11#define FIFO_SWAP_END 0x04 /* FIFO. Swap bytes 3<>0, 2<>1. */ 12#define FIFO_SWAP_INHW 0x08 /* FIFO. Swap bytes 3<>2, 1<>0. */ 13#define FIFO_SWAP_HW 0x0c /* FIFO. Swap half-words. */ 14#define FIFOINFREE 0x40 /* Input FIFO free entry count. */ 15#define FIFOOUTVALID 0x41 /* Output FIFO valid entry count. */ 16#define COMM 0x42 /* dual 4 bit communications ports */ 17#define MEMENDIAN 0x43 /* set byte swapping on PCI mem accesses */ 18#define INTR 0x44 /* which interrupts occurred */ 19#define INTREN 0x46 /* enable different interrupts */ 20#define DEBUGREG 0x48 /* soft resets, RISC hold/single step */ 21#define LOWWATERMARK 0x49 /* Input FIFO low water mark for interrupt */ 22#define PCITEST 0x4C /* PCI test */ 23#define DMACMDPTR 0x50 /* DMA command list pointer */ 24#define DMA_ADDRESS 0x54 /* DMA data address */ 25#define DMA_COUNT 0x58 /* DMA remaining transfer count */ 26#define STATEINDEX 0x60 /* state index info */ 27#define STATEDATA 0x64 /* state data info */ 28#define SCRATCH 0x70 /* 16-bit BIOS scratch space */ 29#define MODEREG 0x72 /* Mode -- to differentiate from old MODE */ 30#define MODE_ MODEREG 31#define MODE MODEREG 32#define BANKSELECT 0x74 /* Local memory to A0000 mapping */ 33#define BANKSELECT_PHYSADDR ((unsigned long)(0xA0000)) 34#define CRTCTEST 0x80 /* CRTC test register */ 35#define CRTCCTL 0x84 /* CRTC mode */ 36#define CRTCHORZ 0x88 /* CRTC horizontal timing */ 37#define CRTCVERT 0x8c /* CRTC vertical timing */ 38#define FRAMEBASEB 0x90 /* Stereoscopic frame base b address */ 39#define FRAMEBASEA 0x94 /* Frame base A address */ 40#define CRTCOFFSET 0x98 /* CRTC StrideOffset */ 41#define CRTCSTATUS 0x9c /* CRTC video scan position */ 42#define DRAMCTL 0xa0 /* DRAM timing */ 43#define PALETTE 0xb0 /* Access to DAC */ 44#define RAMDACBASEADDR 0xb0 /* Access to DAC */ 45#define DEVICE0 0xc0 /* external device 0 (PLL) */ 46#define DEVICE1 0xd0 /* external device 1 */ 47 48/* IO register flag bits */ 49/* _MASK defined for multi-bit values */ 50/* _ADDR defined for registers accessible from RISC */ 51 52/* COMM */ 53#define SYSSTATUS_MASK 0x0f /* host->RISC comm */ 54#define SYSSTATUS_SHIFT 0 55#define RISCSTATUS_MASK 0xf0 /* RISC->host comm r/o */ 56#define RISCSTATUS_SHIFT 4 57 58/* MEMENDIAN */ 59#define MEMENDIAN_NO 0 /* No byte swap. */ 60#define MEMENDIAN_END 1 /* Swap bytes 3<>0, 2<>1. */ 61#define MEMENDIAN_INHW 2 /* Swap bytes 3<>2, 1<>0. */ 62#define MEMENDIAN_HW 3 /* Swap half-words. */ 63#define MEMENDIAN_MASK 3 64#define MEMENDIAN_SHIFT 0 65 66#define DMABUSY 0x80 /* DMA busy r/o */ 67#define DMACMDPTR_DMABUSY 0x1 /* corresponding bit in other reg */ 68 69/* INTR */ 70#define VERTINTR 0x01 /* vert retrace */ 71#define FIFOLOWINTR 0x02 /* free entries rose above low water */ 72#define RISCINTR 0x04 /* RISC firmware interrupt */ 73#define HALTINTR 0x08 /* RISC halted */ 74#define FIFOERRORINTR 0x10 /* FIFO under/over flow */ 75#define DMAERRORINTR 0x20 /* PCI error during DMA */ 76#define DMAINTR 0x40 /* DMA done interrupt */ 77#define XINTR 0x80 /* external device pass thru intr */ 78 79/* INTREN */ 80#define VERTINTREN 0x01 /* vert retrace */ 81#define FIFOLOWINTREN 0x02 /* free entries rose above low water */ 82#define RISCINTREN 0x04 /* RISC firmware interrupt */ 83#define HALTINTREN 0x08 /* RISC halted */ 84#define FIFOERRORINTREN 0x10 /* FIFO under/over flow */ 85#define DMAERRORINTREN 0x20 /* PCI error during DMA */ 86#define DMAINTREN 0x40 /* DMA done interrupt */ 87#define XINTREN 0x80 /* external device pass thru intr */ 88 89/* DEBUG */ 90#define SOFTRESET 0x01 /* soft reset chip */ 91#define HOLDRISC 0x02 /* stop RISC when set */ 92#define STEPRISC 0x04 /* single step RISC */ 93#define DIRECTSCLK 0x08 /* disable internal divide by 2 for sys clk */ 94#define SOFTVGARESET 0x10 /* assert VGA reset */ 95#define SOFTXRESET 0x20 /* assert XReset output to ext devices */ 96 97/* MODE_ register */ 98#define VESA_MODE 0x01 /* enable 0xA0000 in native mode */ 99#define VGA_MODE 0x02 /* VGA mode if set else native mode */ 100#define VGA_32 0x04 /* enable VGA 32 bit accesses */ 101#define DMA_EN 0x08 /* enable DMA accesses */ 102 103#define NATIVE_MODE 0 /* not VESA and not VGA */ 104 105/* DRAM register */ 106#define DRAMCTL_ADDR 0xffe00500 107#define DRAMCTL_SLOWPRECHARGE 0x140010 108#define DRAMCTL_NORMAL 0x140000 109 110/* CRTC registers */ 111#define CRTCTEST_ADDR 0xffe00400 112#define CRTCCTL_ADDR 0xffe00420 113#define CRTCHORZ_ADDR 0xffe00440 114#define CRTCVERT_ADDR 0xffe00460 115#define FRAMEBASEB_ADDR 0xffe00480 116#define FRAMEBASEA_ADDR 0xffe004a0 117#define CRTCOFFSET_ADDR 0xffe004c0 118#define CRTCSTATUS_ADDR 0xffe004e0 119 120#define CRTCTEST_VIDEOLATENCY_MASK 0x1F 121#define CRTCTEST_NOTVBLANK 0x10000 122#define CRTCTEST_VBLANK 0x40000 123 124#define CRTCCTL_SCRNFMT_MASK 0xF 125#define CRTCCTL_VIDEOFIFOSIZE128 0x10 126#define CRTCCTL_ENABLEDDC 0x20 127#define CRTCCTL_DDCOUTPUT 0x40 128#define CRTCCTL_DDCDATA 0x80 129#define CRTCCTL_VSYNCHI 0x100 130#define CRTCCTL_HSYNCHI 0x200 131#define CRTCCTL_VSYNCENABLE 0x400 132#define CRTCCTL_HSYNCENABLE 0x800 133#define CRTCCTL_VIDEOENABLE 0x1000 134#define CRTCCTL_STEREOSCOPIC 0x2000 135#define CRTCCTL_FRAMEDISPLAYED 0x4000 136#define CRTCCTL_FRAMEBUFFERBGR 0x8000 137#define CRTCCTL_EVENFRAME 0x10000 138#define CRTCCTL_LINEDOUBLE 0x20000 139#define CRTCCTL_FRAMESWITCHED 0x40000 140 141#define CRTCHORZ_ACTIVE_MASK 0xFF 142#define CRTCHORZ_ACTIVE_SHIFT 0 143#define CRTCHORZ_BACKPORCH_MASK 0x7E00 144#define CRTCHORZ_BACKPORCH_SHIFT 11 145#define CRTCHORZ_SYNC_MASK 0x1F0000L 146#define CRTCHORZ_SYNC_SHIFT 16 147#define CRTCHORZ_FRONTPORCH_MASK 0xE00000L 148#define CRTCHORZ_FRONTPORCH_SHIFT 20 149 150#define CRTCVERT_ACTIVE_MASK 0x7FF 151#define CRTCVERT_BACKPORCH_MASK 0x1F800 152#define CRTCVERT_SYNC_MASK 0xE0000 153#define CRTCVERT_FRONTPORCH_MASK 0x03F00000 154 155#define CRTCOFFSET_MASK 0xFFFF 156 157#define CRTCSTATUS_HORZCLOCKS_MASK 0xFF 158#define CRTCSTATUS_HORZ_MASK 0x600 159#define CRTCSTATUS_HORZ_FPORCH 0x200 160#define CRTCSTATUS_HORZ_SYNC 0x600 161#define CRTCSTATUS_HORZ_BPORCH 0x400 162#define CRTCSTATUS_HORZ_ACTIVE 0x000 163#define CRTCSTATUS_SCANLINESLEFT_MASK 0x003FF800 164#define CRTCSTATUS_VERT_MASK 0xC00000 165#define CRTCSTATUS_VERT_FPORCH 0x400000 166#define CRTCSTATUS_VERT_SYNC 0xC00000 167#define CRTCSTATUS_VERT_BPORCH 0x800000 168#define CRTCSTATUS_VERT_ACTIVE 0x000000 169 170/* RAMDAC registers - avail through I/O space */ 171 172#define DACRAMWRITEADR 0xb0 173#define DACRAMDATA 0xb1 174#define DACPIXELMSK 0xb2 175#define DACRAMREADADR 0xb3 176#define DACOVSWRITEADR 0xb4 177#define DACOVSDATA 0xb5 178#define DACCOMMAND0 0xb6 179#define DACOVSREADADR 0xb7 180#define DACCOMMAND1 0xb8 181#define DACCOMMAND2 0xb9 182#define DACSTATUS 0xba 183#define DACCOMMAND3 0xba /* accessed via unlocking/indexing */ 184#define DACCURSORDATA 0xbb 185#define DACCURSORXLOW 0xbc 186#define DACCURSORXHIGH 0xbd 187#define DACCURSORYLOW 0xbe 188#define DACCURSORYHIGH 0xbf 189 190/* values for DACCOMMAND3 */ 191#define DACCOMMAND3_INIT 0x00 192#define DAC_CLK_DOUBLER 0x8 193 194#define PLLDEV DEVICE0 195 196/* Some state indices */ 197#define STATEINDEX_IR 128 198#define STATEINDEX_PC 129 199#define STATEINDEX_S1 130 200 201/* PCI configuration registers. */ 202#define CONFIGIOREG 0xE0000014 203#define CONFIGENABLE 0xE0000004 204#ifdef USEROM 205#define CONFIGROMREG 0xE0000030 206#endif 207 208/* Cache parameters. */ 209#define ICACHESIZE 2048 /* I cache size. */ 210#define ICACHELINESIZE 32 /* I cache line size. */ 211#define ICACHE_ONOFF_MASK (((vu32)1<<17)|(1<<3)) 212#define ICACHE_ON ((0<<17)|(0<<3)) 213#define ICACHE_OFF (((vu32)1<<17)|(1<<3)) 214 215 216 217#endif /* __COMMONREGS_H__ */ 218