v2kregs.h revision 72313efb
1#ifndef __V2KREGS_H__ 2#define __V2KREGS_H__ 3 4/* New registers and values found from V2K and on */ 5#define STATUS 0x4A /* specifies which blocks of the V2000 are busy */ 6#define XBUSCTL 0x4B /* XBus control register */ 7 8#define SCLKPLL 0x68 /* system clock PLL control register */ 9#define SCRATCH 0x70 /* 16-bit BIOS scratch space */ 10 11#define MEMDIAG 0xa4 /* Memory diagnostic register #1 */ 12#define CURSORBASE 0xac /* cursor base address bits [23:10] aligne to 1024 byte boundary */ 13 14#define PCLKPLL 0xc0 /* external device 0 */ 15#define VINEVENBASE 0xd0 /* video input even field base address */ 16#define VINODDBASE 0xd4 /* video input odd field base address */ 17#define WRITEINTR0ADDR 0xd8 /* Memory write interrupt address0 */ 18#define WRITEINTR1ADDR 0xdc /* Memory write interrupt address1 */ 19#define DEVICE0_V2x000 0xf0 /* external device 1 (PLL) */ 20 21/* 22 * PCLKPLL/SCLKPLL register bit defn 23 */ 24#define PCLKPLLPMASK 0xffffe1ff 25#define SCLKPLLPMASK 0xffffe1ff 26#define MCLKPLLPMASK 0xfffe1fff 27#define PLLPCLKP 9 28#define PLLSCLKP 9 29#define PLLMCLKP 13 30#define PLLPCLKN 13 31#define PLLSCLKN 17 32#define PLLPCLKDOUBLE 26 /* bit 26 in PClkPLL register */ 33 34#define DIRECTPCLKMASK 0x00400000 35#define DIRECTMCLKMASK 0x00800000 36 37#define VGASTDCLOCK 0x100000 38#define EXTRADIV2 0x200000 39 40#define PLLINCLKFREQ 14318 /* PLL input clk freq in KHz */ 41 42/* 43 * memory controller 44 */ 45#define MCLK_BYPASSEDGEFREQ 90000 /* in KHz */ 46 47/* 48 * Microcode commands 49 */ 50#define CMD_SETPALETTE 0x21 51 52/* 53 * MMIO registers 54 */ 55 56#define MMIO_FIFOINFREE 0x20040 57#define MMIO_COMM 0x20042 58#define MMIO_FIFOOUTVALID 0x20041 59#define MMIO_INTR 0x20044 /* which interrupts occurred */ 60#define MMIO_DMACMDPTR 0x20050 61#define MMIO_CRTCHORZ 0x20088 /* CRTC horizontal timing */ 62#define MMIO_CRTCVERT 0x2008c /* CRTC vertical timing */ 63#define MMIO_CRTCSTATUS 0x2009c 64#define MMIO_DACRAMWRITEADR 0x200b0 /* Palette Write Index */ 65#define MMIO_DACRAMDATA 0x200b1 /* Palette Data */ 66#define MMIO_VINEVENBASE 0x200d0 /* video input even field base address */ 67#define MMIO_VINODDBASE 0x200d4 /* video input odd field base address */ 68#define MMIO_WRITEINTR0ADDR 0x200d8 /* Memory write interrupt address0 */ 69#define MMIO_WRITEINTR1ADDR 0x200dc /* Memory write interrupt address1 */ 70 71#define HOST_INTERRUPT_MUTEX 1 72 73/* memory mapped IO register structure */ 74typedef struct _v_mem_io { 75 vu32 fifo_swap_no[0x2000]; /* 0x0 */ 76 vu32 fifo_swap_end[0x2000]; /* 0x4000 */ 77 vu32 fifo_swap_inhw[0x2000]; /* 0x8000 */ 78 vu32 fifo_swap_hw[0x2000]; /* 0xC000 */ 79 vu32 reserved0[0x10]; /* 0x10000 */ 80 vu8 fifoinFree; /* 0x10040 */ 81 vu8 fifooutvalid; /* 0x10041 */ 82 vu8 comm; /* 0x10042 */ 83 vu8 memendian; /* 0x10043 */ 84 vu8 intr; /* 0x10044 */ 85 vu8 reserved1; /* 0x10045 */ 86 vu8 intren; /* 0x10046 */ 87 vu8 reserved2; /* 0x10047 */ 88 vu8 debugreg; /* 0x10048 */ 89 vu8 lowwatermark; /* 0x10049 */ 90 vu8 status; /* 0x1004a */ 91 vu8 xbusctl; /* 0x1004b */ 92 vu8 pcitest; /* 0x1004c */ 93 vu8 reserved3[3]; /* 0x1004d */ 94 vu32 dmacmdptr; /* 0x10050 */ 95 vu32 dma_address; /* 0x10054 */ 96 vu32 dma_count; /* 0x10058 */ 97 vu8 vga_extend; /* 0x1005c */ 98 vu8 reserved4; /* 0x1005d */ 99 vu8 membase; /* 0x1005e */ 100 vu8 reserved5; /* 0x1005f */ 101 vu32 stateindex; /* 0x10060 */ 102 vu32 statedata; /* 0x10064 */ 103 vu8 sclkpll; /* 0x10068 */ 104 vu8 reserved6[7]; /* 0x10069 */ 105 vu16 scratch; /* 0x10070 */ 106 vu8 mode; /* 0x10072 */ 107 vu8 scratch1; /* 0x10073 */ 108 vu8 bankselect; /* 0x10074 */ 109 vu8 reserved7[11]; /* 0x10075 */ 110 vu32 crtctest; /* 0x10080 */ 111 vu32 crtcctl; /* 0x10084 */ 112 vu32 crtchorz; /* 0x10088 */ 113 vu32 crtcvert; /* 0x1008c */ 114 vu32 framebaseb; /* 0x10090 */ 115 vu32 framebasea; /* 0x10094 */ 116 vu32 crtcoffset; /* 0x10098 */ 117 vu32 crtcstatus; /* 0x1009c */ 118 vu32 memctl; /* 0x100a0 */ 119 vu32 memdiag; /* 0x100a4 */ 120 vu32 memcmd; /* 0x100a8 */ 121 vu32 cursorbase; /* 0x100ac */ 122 vu8 dacramwriteadr; /* 0x100b0 */ 123 vu8 dacramdata; /* 0x100b1 */ 124 vu8 dacpixelmsk; /* 0x100b2 */ 125 vu8 dacramreadadr; /* 0x100b3 */ 126 vu8 dacovswriteadr; /* 0x100b4 */ 127 vu8 dacovsdata; /* 0x100b5 */ 128 vu8 daccommand0; /* 0x100b6 */ 129 vu8 dacovsreadadr; /* 0x100b7 */ 130 vu8 daccommand1; /* 0x100b8 */ 131 vu8 daccommand2; /* 0x100b9 */ 132 vu8 daccommand3; /* 0x100ba */ 133 vu8 daccursordata; /* 0x100bb */ 134 vu8 daccursorxlow; /* 0x100bc */ 135 vu8 daccursorxhigh; /* 0x100bd */ 136 vu8 daccursorylow; /* 0x100be */ 137 vu8 daccursoryhigh; /* 0x100bf */ 138 vu8 pclkpll; /* 0x100c0 */ 139} v_mem_io; 140 141/* IO register flag bits */ 142/* _MASK defined for multi-bit values */ 143/* _ADDR defined for registers accessible from RISC */ 144 145/* COMM */ 146#define SYSSTATUS_MASK 0x0f /* host->RISC comm */ 147#define SYSSTATUS_SHIFT 0 148#define RISCSTATUS_MASK 0xf0 /* RISC->host comm r/o */ 149#define RISCSTATUS_SHIFT 4 150 151/* MEMENDIAN */ 152#define MEMENDIAN_NO 0 /* No byte swap. */ 153#define MEMENDIAN_END 1 /* Swap bytes 3<>0, 2<>1. */ 154#define MEMENDIAN_INHW 2 /* Swap bytes 3<>2, 1<>0. */ 155#define MEMENDIAN_HW 3 /* Swap half-words. */ 156#define MEMENDIAN_MASK 3 157#define MEMENDIAN_SHIFT 0 158 159#define DMABUSY 0x80 /* DMA busy r/o */ 160#define DMACMDPTR_DMABUSY 0x1 /* corresponding bit in other reg */ 161 162/* INTR */ 163#define VERTINTR 0x01 /* vert retrace */ 164#define FIFOLOWINTR 0x02 /* free entries rose above low water */ 165#define RISCINTR 0x04 /* RISC firmware interrupt */ 166#define HALTINTR 0x08 /* RISC halted */ 167#define FIFOERRORINTR 0x10 /* FIFO under/over flow */ 168#define DMAERRORINTR 0x20 /* PCI error during DMA */ 169#define DMAINTR 0x40 /* DMA done interrupt */ 170#define XINTR 0x80 /* external device pass thru intr */ 171#define VIDEOINEVENINTR 0x100 /* Video input even field interrupt */ 172#define VIDEOINODDINTR 0x100 /* Video input even field interrupt */ 173 174/* INTREN */ 175#define VERTINTREN 0x01 /* vert retrace */ 176#define FIFOLOWINTREN 0x02 /* free entries rose above low water */ 177#define RISCINTREN 0x04 /* RISC firmware interrupt */ 178#define HALTINTREN 0x08 /* RISC halted */ 179#define FIFOERRORINTREN 0x10 /* FIFO under/over flow */ 180#define DMAERRORINTREN 0x20 /* PCI error during DMA */ 181#define DMAINTREN 0x40 /* DMA done interrupt */ 182#define XINTREN 0x80 /* external device pass thru intr */ 183 184/* DEBUG */ 185#define SOFTRESET 0x01 /* soft reset chip */ 186#define HOLDRISC 0x02 /* stop RISC when set */ 187#define STEPRISC 0x04 /* single step RISC */ 188#define DIRECTSCLK 0x08 /* disable internal divide by 2 for sys clk */ 189#define SOFTVGARESET 0x10 /* assert VGA reset */ 190#define SOFTXRESET 0x20 /* assert XReset output to ext devices */ 191 192/* MODE_ register */ 193#define VESA_MODE 0x01 /* enable 0xA0000 in native mode */ 194#define VGA_MODE 0x02 /* VGA mode if set else native mode */ 195#define VGA_32 0x04 /* enable VGA 32 bit accesses */ 196#define DMA_EN 0x08 /* enable DMA accesses */ 197 198#define NATIVE_MODE 0 /* not VESA and not VGA */ 199 200/* DRAM register */ 201#define DRAMCTL_ADDR 0xffe00500 202 203/* CRTC registers */ 204#define CRTCTEST_ADDR 0xffe00400 205#define CRTCCTL_ADDR 0xffe00420 206#define CRTCHORZ_ADDR 0xffe00440 207#define CRTCVERT_ADDR 0xffe00460 208#define FRAMEBASEB_ADDR 0xffe00480 209#define FRAMEBASEA_ADDR 0xffe004a0 210#define CRTCOFFSET_ADDR 0xffe004c0 211#define CRTCSTATUS_ADDR 0xffe004e0 212 213#define CRTCTEST_VIDEOLATENCY_MASK 0x1F 214#define CRTCTEST_NOTVBLANK 0x10000 215#define CRTCTEST_VBLANK 0x40000 216 217#define CRTCCTL_SCRNFMT_MASK 0xF 218#define CRTCCTL_VIDEOFIFOSIZE128 0x10 219#define CRTCCTL_ENABLEDDC 0x20 220#define CRTCCTL_DDCOUTPUT 0x40 221#define CRTCCTL_DDCDATA 0x80 222#define CRTCCTL_VSYNCHI 0x100 223#define CRTCCTL_HSYNCHI 0x200 224#define CRTCCTL_VSYNCENABLE 0x400 225#define CRTCCTL_HSYNCENABLE 0x800 226#define CRTCCTL_VIDEOENABLE 0x1000 227#define CRTCCTL_STEREOSCOPIC 0x2000 228#define CRTCCTL_FRAMEDISPLAYED 0x4000 229#define CRTCCTL_FRAMEBUFFERBGR 0x8000 230#define CRTCCTL_EVENFRAME 0x10000 231#define CRTCCTL_LINEDOUBLE 0x20000 232#define CRTCCTL_FRAMESWITCHED 0x40000 233#define CRTCCTL_VIDEOFIFOSIZE256 0x800000 234 235#define CRTCHORZ_ACTIVE_MASK 0xFF 236#define CRTCHORZ_ACTIVE_SHIFT 0 237#define CRTCHORZ_BACKPORCH_MASK 0x7E00 238#define CRTCHORZ_BACKPORCH_SHIFT 11 239#define CRTCHORZ_SYNC_MASK 0x1F0000L 240#define CRTCHORZ_SYNC_SHIFT 16 241#define CRTCHORZ_FRONTPORCH_MASK 0xE00000L 242#define CRTCHORZ_FRONTPORCH_SHIFT 20 243 244#define CRTCVERT_ACTIVE_MASK 0x7FF 245#define CRTCVERT_BACKPORCH_MASK 0x1F800 246#define CRTCVERT_SYNC_MASK 0xE0000 247#define CRTCVERT_FRONTPORCH_MASK 0x03F00000 248 249#define CRTCOFFSET_MASK 0xFFFF 250 251#define CRTCSTATUS_HORZCLOCKS_MASK 0xFF 252#define CRTCSTATUS_HORZ_MASK 0x600 253#define CRTCSTATUS_HORZ_FPORCH 0x200 254#define CRTCSTATUS_HORZ_SYNC 0x600 255#define CRTCSTATUS_HORZ_BPORCH 0x400 256#define CRTCSTATUS_HORZ_ACTIVE 0x000 257#define CRTCSTATUS_SCANLINESLEFT_MASK 0x003FF800 258#define CRTCSTATUS_VERT_MASK 0xC00000 259#define CRTCSTATUS_VERT_FPORCH 0x400000 260#define CRTCSTATUS_VERT_SYNC 0xC00000 261#define CRTCSTATUS_VERT_BPORCH 0x800000 262#define CRTCSTATUS_VERT_ACTIVE 0x000000 263 264/* RAMDAC registers - avail through I/O space */ 265 266#define DACRAMWRITEADR 0xb0 267#define DACRAMDATA 0xb1 268#define DACPIXELMSK 0xb2 269#define DACRAMREADADR 0xb3 270#define DACOVSWRITEADR 0xb4 271#define DACOVSDATA 0xb5 272#define DACCOMMAND0 0xb6 273#define DACOVSREADADR 0xb7 274#define DACCOMMAND1 0xb8 275#define DACCOMMAND2 0xb9 276#define DACSTATUS 0xba 277#define DACCOMMAND3 0xba /* accessed via unlocking/indexing */ 278#define DACCURSORDATA 0xbb 279#define DACCURSORXLOW 0xbc 280#define DACCURSORXHIGH 0xbd 281#define DACCURSORYLOW 0xbe 282#define DACCURSORYHIGH 0xbf 283 284#define BT_CO_COLORWR_ADDR DACOVSWRITEADR 285#define BT_CO_COLORDATA DACOVSDATA 286#define BT_PTR_ROWOFFSET 32 287#define BT_PTR_COLUMNOFFSET 32 288 289/* PCLKPLL register */ 290#define PLLDEV DEVICE0 291#define VOUTEN 0x00080000L /* bit 19 */ 292#define VGASCLKOVER2 0x00100000L /* bit 20 */ 293#define PCLKSTARTEN 0x00800000L /* bit 23 */ 294 295/* Some state indices */ 296#define STATEINDEX_IR 128 297#define STATEINDEX_PC 129 298#define STATEINDEX_S1 130 299 300/* PCI configuration registers. */ 301#define CONFIGIOREG 0xE0000014 302#define CONFIGENABLE 0xE0000004 303#ifdef USEROM 304#define CONFIGROMREG 0xE0000030 305#endif 306 307/* Cache parameters. */ 308#define ICACHESIZE 2048 /* I cache size. */ 309#define ICACHELINESIZE 32 /* I cache line size. */ 310#ifndef ICACHE_ONOFF_MASK 311#define ICACHE_ONOFF_MASK (((v_u32)1<<17)|(1<<3)) 312#define ICACHE_ON ((0<<17)|(0<<3)) 313#define ICACHE_OFF (((v_u32)1<<17)|(1<<3)) 314#endif 315 316/* Video registers */ 317#define BT829_DEV DEVICE0 318#define VIDEO_DECODER_DEV_ENABLE 0x4 319#define VIDEO_DECODER_DEV_DISABLE 0x0 320 321#define VINBASE_MASK 0x1FFFFFL 322#define VINMAXVERT_SHIFT 24 323#define VINSTRIDE_SHIFT 27 324#define VINQSIZE_SHIFT 30 325 326#define VINORDER_SHIFT 24 327#define ACTIVE_LOW 0 328#define ACTIVE_HI 1L 329#define VINHSYNCHI_SHIFT 26 330#define VINVSYNCHI_SHIFT 27 331#define VINACTIVE_SHIFT 28 332#define VINNOODD_SHIFT 29 333#define VINENABLE_SHIFT 30 334 335#endif /* __V2KREGS_H__ */ 336