newmmio.h revision ba85709e
1 2/* 3Copyright (C) 1994-1999 The XFree86 Project, Inc. All Rights Reserved. 4 5Permission is hereby granted, free of charge, to any person obtaining a copy of 6this software and associated documentation files (the "Software"), to deal in 7the Software without restriction, including without limitation the rights to 8use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 9of the Software, and to permit persons to whom the Software is furnished to do 10so, subject to the following conditions: 11 12The above copyright notice and this permission notice shall be included in all 13copies or substantial portions of the Software. 14 15THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FIT- 17NESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 20WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 22Except as contained in this notice, the name of the XFree86 Project shall not 23be used in advertising or otherwise to promote the sale, use or other dealings 24in this Software without prior written authorization from the XFree86 Project. 25*/ 26 27/*************************************************************************** 28 * 29 * typedefs and macros for MMIO mode, S3 ViRGE 30 * 31 * who when vers 32 * HK 9609126 0.0 33 * 34 * based on: 35 * 36 * typedefs and macros for old and new MMIO mode, Trio64V+ and 868/968 37 * 38 * who when vers 39 * BL 0300296 0.1 40 * SM 200497 0.2 Added Caching version of register macros. 41 * KJB 9/98 0.3 Added S3V_MMIO_REGSIZE 42 ***************************************************************************/ 43 44#ifndef _NEWMMIO_H 45#define _NEWMMIO_H 46 47/* base for S3_OUTW macro */ 48#define S3_NEWMMIO_REGBASE 0x1000000 /* 16MB */ 49#define S3_NEWMMIO_REGSIZE 0x10000 /* 64KB */ 50#define S3V_MMIO_REGSIZE 0x8000 /* 32KB */ 51 52 53/* #include <Xmd.h> */ 54 55 56#define int16 CARD16 57#define int32 CARD32 58 59#define S3_NEWMMIO_VGABASE (S3_NEWMMIO_REGBASE + 0x8000) 60 61#if 0 62typedef struct { int16 vendor_ID; int16 device_ID; } pci_id; 63typedef struct { int16 cmd; int16 devsel; } cmd_devsel; 64 65typedef struct { 66 pci_id pci_ident; 67 cmd_devsel cmd_device_sel; 68 int32 class_code; 69 char dummy_0c; 70 char latnecy_timer; 71 int16 dummy_0e; 72 int32 base0; 73 char dummy_14[0x20-sizeof(int32)]; 74 int32 bios_base; 75 int32 dummy_34; 76 int32 dummy_38; 77 char int_line; 78 char int_pin; 79 int16 latency_grant; 80} pci_conf_regs; 81 82 83typedef struct { 84 int32 prim_stream_cntl; 85 int32 col_chroma_key_cntl; 86 char dummy1[0x8190 - 0x8184-sizeof(int32)]; 87 int32 second_stream_cntl; 88 int32 chroma_key_upper_bound; 89 int32 second_stream_stretch; 90 char dummy2[0x81a0 - 0x8198-sizeof(int32)]; 91 int32 blend_cntl; 92 char dummy3[0x81c0 - 0x81a0-sizeof(int32)]; 93 int32 prim_fbaddr0; 94 int32 prim_fbaddr1; 95 int32 prim_stream_stride; 96 int32 double_buffer; 97 int32 second_fbaddr0; 98 int32 second_fbaddr1; 99 int32 second_stream_stride; 100 int32 opaq_overlay_cntl; 101 int32 k1; 102 int32 k2; 103 int32 dda_vert; 104 int32 streams_fifo; 105 int32 prim_start_coord; 106 int32 prim_window_size; 107 int32 second_start_coord; 108 int32 second_window_size; 109} streams_proc_regs; 110 111typedef struct { 112 int32 fifo_control; 113 int32 miu_control; 114 int32 streams_timeout; 115 int32 misc_timeout; 116 int32 dummy_8210, dummy_8214, dummy_8218, dummy_821c; 117 int32 dma_read_base_addr; 118 int32 dma_read_stride_width; 119} memport_proc_regs; 120 121typedef struct { 122 int32 subsystem_csr; 123 int32 dummy_8508; 124 int32 adv_func_cntl; 125} subsys_regs; 126 127typedef struct { 128 int32 start_sysmem_addr; 129 int32 transfer_length; 130 int32 transfer_enable; 131} video_dma_regs; 132 133typedef struct { 134 int32 base_addr; 135 int32 write_pointer; 136 int32 read_pointer; 137 int32 dma_enable; 138} cmd_dma_regs; 139 140typedef struct { 141 video_dma_regs video; 142 int32 dummy_858c; 143 cmd_dma_regs cmd; 144} dma_regs; 145 146typedef struct { 147 int32 lpb_mode; 148 int32 lpb_fifostat; 149 int32 lpb_intflags; 150 int32 lpb_fb0addr; 151 int32 lpb_fb1addr; 152 int32 lpb_direct_addr; 153 int32 lpb_direct_data; 154 int32 lpb_gpio; 155 int32 lpb_serial_port; 156 int32 lpb_input_winsize; 157 int32 lpb_data_offsets; 158 int32 lpb_hor_decimctl; 159 int32 lpb_vert_decimctl; 160 int32 lpb_line_stride; 161 int32 lpb_output_fifo; 162} lpbus_regs; 163 164 165typedef struct { char atr_cntl_ind; char attr_cntl_dat; char misc_out; 166 char viseo_enable; } v3c0; 167typedef struct { char seq_index; char seq_data; char dac_mask; 168 char dac_rd_index; } v3c4; 169typedef struct { char dac_wr_index; char dac_data; char feature_cntl; 170 char filler; } v3c8; 171typedef struct v3cc { char misc_out; char filler; char graph_cntl_index; 172 char graph_cntl_data; } v3cc; 173typedef struct { 174 v3c0 v3c0_regs; 175 v3c4 v3c4_regs; 176 v3c8 v3c8_regs; 177 v3cc v3cc_regs; 178} vga_3c_regs; 179 180typedef struct { char crt_index; char crt_data; int16 filler; } v3d4; 181typedef struct { int16 filler1; char feature_cntl; char filler2;} v3d8; 182 183typedef struct { 184 int32 filler; 185 v3d4 v3d4_regs; 186 v3d8 v3d8_regs; 187} vga_3bd_regs ; 188 189 190 191typedef struct { 192 char filler1[-(0xa000-0xa100)]; 193 int32 patt[-(0xa100-0xa1bc) / sizeof(int32) + 1]; 194} colpatt_regs; 195 196typedef struct { 197 char filler1[-(0xa400-0xa4d4)]; 198 int32 src_base; 199 int32 dest_base; 200 int32 clip_l_r; 201 int32 clip_t_b; 202 int32 dest_src_str; 203 int32 mono_pat0; 204 int32 mono_pat1; 205 int32 pat_bg_clr; 206 int32 pat_fg_clr; 207 int32 src_bg_clr; 208 int32 src_fg_clr; 209 int32 cmd_set; 210 int32 rwidth_height; 211 int32 rsrc_xy; 212 int32 rdest_xy; 213} bltfill_regs; 214 215typedef struct { 216 char filler1[-(0xa800-0xa8d4)]; 217 int32 src_base; 218 int32 dest_base; 219 int32 clip_l_r; 220 int32 clip_t_b; 221 int32 dest_src_str; 222 int32 dummy1; 223 int32 dummy2; 224 int32 dummy3; 225 int32 pat_fg_clr; 226 int32 dummy4; 227 int32 dummy5; 228 int32 cmd_set; 229 char filler2[-(0xa904-0xa96c)]; 230 int32 lxend0_end1; 231 int32 ldx; 232 int32 lxstart; 233 int32 lystart; 234 int32 lycnt; 235} line_regs; 236 237typedef struct { 238 char filler1[-(0xac00-0xacd4)]; 239 int32 src_base; 240 int32 dest_base; 241 int32 clip_l_r; 242 int32 clip_t_b; 243 int32 dest_src_str; 244 int32 mono_pat0; 245 int32 mono_pat1; 246 int32 pat_bg_clr; 247 int32 pat_fg_clr; 248 int32 dummy1; 249 int32 dummy2; 250 int32 cmd_set; 251 char filler2[-(0xad04-0xad68)]; 252 int32 prdx; 253 int32 prxstart; 254 int32 pldx; 255 int32 plxstart; 256 int32 pystart; 257 int32 pycnt; 258} polyfill_regs; 259 260typedef struct { 261 char filler1[-(0xb000-0xb0d4)]; 262 int32 z_base; 263 int32 dest_base; 264 int32 clip_l_r; 265 int32 clip_t_b; 266 int32 dest_src_str; 267 int32 z_stride; 268 int32 dummy1; 269 int32 dummy2; 270 int32 fog_clr; 271 int32 dummy3; 272 int32 dummy4; 273 int32 cmd_set; 274 char filler2[-(0xb104-0xb144)]; 275 int32 dgdy_dbdy; 276 int32 dady_drdy; 277 int32 gs_bs; 278 int32 as_rs; 279 int32 dummy5; 280 int32 dz; 281 int32 zstart; 282 int32 dummy6; 283 int32 dummy7; 284 int32 dummy8; 285 int32 xend0_end1; 286 int32 dx; 287 int32 xstart; 288 int32 ystart; 289 int32 ycnt; 290} line3d_regs; 291 292typedef struct { 293 char filler1[-(0xb400-0xb4d4)]; 294 int32 z_base; 295 int32 dest_base; 296 int32 clip_l_r; 297 int32 clip_t_b; 298 int32 dest_src_str; 299 int32 z_stride; 300 int32 tex_base; 301 int32 tex_bdr_clr; 302 int32 fog_clr; 303 int32 color0; 304 int32 color1; 305 int32 cmd_set; 306 int32 bv; 307 int32 bu; 308 int32 dwdx; 309 int32 dwdy; 310 int32 ws; 311 int32 dddx; 312 int32 dvdx; 313 int32 dudx; 314 int32 dddy; 315 int32 dvdy; 316 int32 dudy; 317 int32 ds; 318 int32 vs; 319 int32 us; 320 int32 dgdx_dbdx; 321 int32 dadx_drdx; 322 int32 dgdy_dbdy; 323 int32 dady_drdy; 324 int32 gs_bs; 325 int32 as_rs; 326 int32 dzdx; 327 int32 dzdy; 328 int32 zs; 329 int32 dxdy12; 330 int32 xend12; 331 int32 dxdy01; 332 int32 xend01; 333 int32 dxdy02; 334 int32 xstart02; 335 int32 ystart; 336 int32 y01_y12; 337} triangle3d_regs; 338 339 340typedef struct { 341 int32 img[0x8000/4]; 342 union { pci_conf_regs regs; 343 char dummy[-(0x8000 - 0x8180)]; 344 } pci_regs; 345 union { streams_proc_regs regs; 346 char dummy[-(0x8180 - 0x8200)]; 347 } streams_regs; 348 union { memport_proc_regs regs; 349 char dummy[-(0x8200 - 0x83b0)]; 350 } memport_regs; 351 union { vga_3bd_regs regs; 352 char dummy[-(0x83b0 - 0x83c0)]; 353 } v3b_regs; 354 union { vga_3c_regs regs; 355 char dummy[-(0x83c0 - 0x83d0)]; 356 } v3c_regs; 357 union { vga_3bd_regs regs; 358 char dummy[-(0x83d0 - 0x8504)]; 359 } v3d_regs; 360 union { subsys_regs regs; 361 char dummy[-(0x8504 - 0x8580)]; 362 } subsys_regs; 363 union { dma_regs regs; 364 char dummy[-(0x8580 - 0xa000)]; 365 } dma_regs; 366 union { colpatt_regs regs; 367 char dummy[-(0xa000 - 0xa400)]; 368 } colpatt_regs; 369 union { bltfill_regs regs; 370 char dummy[-(0xa400 - 0xa800)]; 371 } bltfill_regs; 372 union { line_regs regs; 373 char dummy[-(0xa800 - 0xac00)]; 374 } line_regs; 375 union { polyfill_regs regs; 376 char dummy[-(0xac00 - 0xb000)]; 377 } polyfill_regs; 378 union { line3d_regs regs; 379 char dummy[-(0xb000 - 0xb400)]; 380 } line3d_regs; 381 union { triangle3d_regs regs; 382 char dummy[-(0xb400 - 0xff00)]; 383 } triangle3d_regs; 384 union { lpbus_regs regs; 385 char dummy[-(0xff00 - 0xff5c)]; 386 } lbp_regs; 387} mm_virge_regs ; 388 389 390 391#define mmtr volatile mm_virge_regs * 392 393#define SET_WRT_MASK(msk) /* */ 394#define SET_RD_MASK(msk) /* */ 395#define SET_FRGD_COLOR(col) /* */ 396#define SET_BKGD_COLOR(col) /* */ 397#define SET_FRGD_MIX(fmix) /* */ 398#define SET_BKGD_MIX(bmix) /* */ 399#define SET_PIX_CNTL(val) /* */ 400#define SET_MIN_AXIS_PCNT(min) /* */ 401#define SET_MAJ_AXIS_PCNT(maj) /* */ 402#define SET_CURPT(c_x, c_y) /* */ 403#define SET_CUR_X(c_x) /* */ 404#define SET_CUR_Y(c_y) /* */ 405#define SET_DESTSTP(x,y) /* */ 406#define SET_AXIS_PCNT(maj, min) /* */ 407#define SET_CMD(c_d) /* */ 408#define SET_ERR_TERM(e) /* */ 409#define SET_SCISSORS(x1,y1,x2,y2) /* */ 410#define SET_SCISSORS_RB(x,y) /* */ 411#define SET_MULT_MISC(val) /* */ 412 413#define SET_PIX_TRANS_W(val) /* */ 414#define SET_PIX_TRANS_L(val) /* */ 415#define SET_MIX(fmix,bmix) /* */ 416 417#endif /* 0 */ 418 419/* 420 * reads from SUBSYS_STAT 421 */ 422#define IN_SUBSYS_STAT() (INREG(SUBSYS_STAT_REG)) 423#define SET_SUBSYS_CRTL(val) do { write_mem_barrier();\ 424OUTREG((val), SUBSYS_STAT_REG);\ 425write_mem_barrier(); } while (0) 426 427 428#if 0 429#define SET_DAC_W_INDEX(index) OUTREG8(DAC_W_INDEX, index) 430#define SET_DAC_DATA(val) OUTREG8(DAC_DATA,val) 431#endif 432 433#if 0 434 435#define IMG_TRANS (((mmtr)s3vMmioMem)->img) 436#define SET_PIXTRANS(a,v) IMG_TRANS[a] = (v) 437#define COLOR_PATTERN (((mmtr)s3vMmioMem)->colpatt_regs.regs) 438 439#define CMD_DMA_BASE(val) (((mmtr)s3vMmioMem)->dma_regs.regs.cmd.base_addr) = (val) 440#define CMD_DMA_WRITEP(val) (((mmtr)s3vMmioMem)->dma_regs.regs.cmd.write_pointer) = (val) 441#define CMD_DMA_READP(val) (((mmtr)s3vMmioMem)->dma_regs.regs.cmd.read_pointer) = (val) 442#define CMD_DMA_ENABLE(val) (((mmtr)s3vMmioMem)->dma_regs.regs.cmd.dma_enable) = (val) 443 444#define SETB_SRC_BASE(val) ((mmtr)s3vMmioMem)->bltfill_regs.regs.src_base = (val) 445#define SETB_DEST_BASE(val) ((mmtr)s3vMmioMem)->bltfill_regs.regs.dest_base = (val) 446#define SETB_CLIP_L_R(l,r) ((mmtr)s3vMmioMem)->bltfill_regs.regs.clip_l_r = ((l)<<16 | (r)) 447#define SETB_CLIP_T_B(t,b) ((mmtr)s3vMmioMem)->bltfill_regs.regs.clip_t_b = ((t)<<16 | (b)) 448/* #define SETB_DEST_SRC_STR(d,s) ((mmtr)s3vMmioMem)->bltfill_regs.regs.dest_src_str = ((d)<<16 | (s)) */ 449 450#define SETB_DEST_SRC_STR(d, s) (OUTREG(DEST_SRC_STR, ((d) << 16 | (s)))) 451 452#define SETB_MONO_PAT0(val) ((mmtr)s3vMmioMem)->bltfill_regs.regs.mono_pat0 = (val) 453#define SETB_MONO_PAT1(val) ((mmtr)s3vMmioMem)->bltfill_regs.regs.mono_pat1 = (val) 454#define SETB_PAT_BG_CLR(val) ((mmtr)s3vMmioMem)->bltfill_regs.regs.pat_bg_clr = (val) 455#define SETB_PAT_FG_CLR(val) ((mmtr)s3vMmioMem)->bltfill_regs.regs.pat_fg_clr = (val) 456#define SETB_SRC_BG_CLR(val) ((mmtr)s3vMmioMem)->bltfill_regs.regs.src_bg_clr = (val) 457#define SETB_SRC_FG_CLR(val) ((mmtr)s3vMmioMem)->bltfill_regs.regs.src_fg_clr = (val) 458#define SETB_CMD_SET(val) do { write_mem_barrier(); ((mmtr)s3vMmioMem)->bltfill_regs.regs.cmd_set = (val); write_mem_barrier(); } while (0) 459#define SETB_RWIDTH_HEIGHT(w,h) ((mmtr)s3vMmioMem)->bltfill_regs.regs.rwidth_height = ((w)<<16 | (h)) 460#define SETB_RSRC_XY(x,y) ((mmtr)s3vMmioMem)->bltfill_regs.regs.rsrc_xy = ((x)<<16 | (y)) 461#define SETB_RDEST_XY(x,y) do { write_mem_barrier(); ((mmtr)s3vMmioMem)->bltfill_regs.regs.rdest_xy = ((x)<<16 | (y)); write_mem_barrier(); } while (0) 462 463/* Caching version of the same MACROs */ 464 465#define CACHE_SETB_CLIP_L_R(l,r) do { unsigned int clip = ((l)<<16 | (r)); if (s3vCached_CLIP_LR != clip) { ((mmtr)s3vMmioMem)->bltfill_regs.regs.clip_l_r = clip; s3vCached_CLIP_LR = clip; s3vCacheMiss++;} else s3vCacheHit++;} while(0) 466#define CACHE_SETB_CLIP_T_B(t,b) do { unsigned int clip = ((t)<<16 | (b)); if (s3vCached_CLIP_TB != clip) { ((mmtr)s3vMmioMem)->bltfill_regs.regs.clip_t_b = clip; s3vCached_CLIP_TB = clip; s3vCacheMiss++;} else s3vCacheHit++;} while(0) 467#define CACHE_SETB_RSRC_XY(x,y) do { unsigned int src = ((x)<<16 | (y)); if (s3vCached_RSRC_XY != src) { ((mmtr)s3vMmioMem)->bltfill_regs.regs.rsrc_xy = src; s3vCached_RSRC_XY = src; s3vCacheMiss++;} else s3vCacheHit++;} while(0) 468#define CACHE_SETB_RWIDTH_HEIGHT(w,h) do { unsigned int rwh = ((w)<<16 | (h)); if (s3vCached_RWIDTH_HEIGHT != rwh) { ((mmtr)s3vMmioMem)->bltfill_regs.regs.rwidth_height = rwh; s3vCached_RWIDTH_HEIGHT = rwh; s3vCacheMiss++;} else s3vCacheHit++;} while(0) 469#define CACHE_SETB_MONO_PAT0(val) do { \ 470 if (s3vCached_MONO_PATTERN0 != (val)) { \ 471 ((mmtr)s3vMmioMem)->bltfill_regs.regs.mono_pat0 = (val); \ 472 s3vCached_MONO_PATTERN0 = (val); \ 473 s3vCacheMiss++; \ 474 } else s3vCacheHit++; \ 475} while(0) 476#define CACHE_SETB_MONO_PAT1(val) do { \ 477 if (s3vCached_MONO_PATTERN1 != (val)) { \ 478 ((mmtr)s3vMmioMem)->bltfill_regs.regs.mono_pat1 = (val); \ 479 s3vCached_MONO_PATTERN1 = (val); \ 480 s3vCacheMiss++; \ 481 } else s3vCacheHit++;\ 482} while(0) 483#define CACHE_SETB_PAT_FG_CLR(val) do { \ 484 if (s3vCached_PAT_FGCLR != (val)) { \ 485 ((mmtr)s3vMmioMem)->bltfill_regs.regs.pat_fg_clr = (val); \ 486 s3vCached_PAT_FGCLR = (val); \ 487 s3vCacheMiss++; \ 488 } else s3vCacheHit++; \ 489} while(0) 490#define CACHE_SETB_PAT_BG_CLR(val) do { \ 491 if (s3vCached_PAT_BGCLR != (val)) { \ 492 ((mmtr)s3vMmioMem)->bltfill_regs.regs.pat_bg_clr = (val); \ 493 s3vCached_PAT_BGCLR = (val); \ 494 s3vCacheMiss++; \ 495 } else s3vCacheHit++; \ 496} while(0) 497#define CACHE_SETB_CMD_SET(val) do { \ 498 if (s3vCached_CMD_SET != (val)) { \ 499 write_mem_barrier(); \ 500 ((mmtr)s3vMmioMem)->bltfill_regs.regs.cmd_set = (val); \ 501 s3vCached_CMD_SET = (val); \ 502 s3vCacheMiss++; \ 503 write_mem_barrier(); \ 504 } else s3vCacheHit++; \ 505} while(0) 506#define SETL_SRC_BASE(val) ((mmtr)s3vMmioMem)->line_regs.regs.src_base = (val) 507#define SETL_DEST_BASE(val) ((mmtr)s3vMmioMem)->line_regs.regs.dest_base = (val) 508#define SETL_CLIP_L_R(l,r) ((mmtr)s3vMmioMem)->line_regs.regs.clip_l_r = ((l)<<16 | (r)) 509#define SETL_CLIP_T_B(t,b) ((mmtr)s3vMmioMem)->line_regs.regs.clip_t_b = ((t)<<16 | (b)) 510#define SETL_DEST_SRC_STR(d,s) ((mmtr)s3vMmioMem)->line_regs.regs.dest_src_str = ((d)<<16 | (s)) 511#define SETL_PAT_FG_CLR(val) ((mmtr)s3vMmioMem)->line_regs.regs.pat_fg_clr = (val) 512#define SETL_CMD_SET(val) do { write_mem_barrier(); ((mmtr)s3vMmioMem)->line_regs.regs.cmd_set = (val); write_mem_barrier(); } while (0) 513#define SETL_LXEND0_END1(e0,e1) ((mmtr)s3vMmioMem)->line_regs.regs.lxend0_end1 = ((e0)<<16 | (e1)) 514#define SETL_LDX(val) ((mmtr)s3vMmioMem)->line_regs.regs.ldx = (val) 515#define SETL_LXSTART(val) ((mmtr)s3vMmioMem)->line_regs.regs.lxstart = (val) 516#define SETL_LYSTART(val) ((mmtr)s3vMmioMem)->line_regs.regs.lystart = (val) 517#define SETL_LYCNT(val) do { write_mem_barrier(); ((mmtr)s3vMmioMem)->line_regs.regs.lycnt = (val); write_mem_barrier(); } while (0) 518 519/* Cache version */ 520#define CACHE_SETL_CMD_SET(val) do { if (s3vCached_CMD_SET != val) { write_mem_barrier(); ((mmtr)s3vMmioMem)->line_regs.regs.cmd_set = val; s3vCached_CMD_SET = val; s3vCacheMiss++; write_mem_barrier(); } else s3vCacheHit++;} while(0) 521 522 523 524#define SETP_SRC_BASE(val) ((mmtr)s3vMmioMem)->polyfill_regs.regs.src_base = (val) 525#define SETP_DEST_BASE(val) ((mmtr)s3vMmioMem)->polyfill_regs.regs.dest_base = (val) 526#define SETP_CLIP_L_R(l,r) ((mmtr)s3vMmioMem)->polyfill_regs.regs.clip_l_r = ((l)<<16 | (r)) 527#define SETP_CLIP_T_B(t,b) ((mmtr)s3vMmioMem)->polyfill_regs.regs.clip_t_b = ((t)<<16 | (b)) 528#define SETP_DEST_SRC_STR(d,s) ((mmtr)s3vMmioMem)->polyfill_regs.regs.dest_src_str = ((d)<<16 | (s)) 529#define SETP_MONO_PAT0(val) ((mmtr)s3vMmioMem)->polyfill_regs.regs.mono_pat0 = (val) 530#define SETP_MONO_PAT1(val) ((mmtr)s3vMmioMem)->polyfill_regs.regs.mono_pat1 = (val) 531#define SETP_PAT_BG_CLR(val) ((mmtr)s3vMmioMem)->polyfill_regs.regs.pat_bg_clr = (val) 532#define SETP_PAT_FG_CLR(val) ((mmtr)s3vMmioMem)->polyfill_regs.regs.pat_fg_clr = (val) 533#define SETP_CMD_SET(val) do { write_mem_barrier(); ((mmtr)s3vMmioMem)->polyfill_regs.regs.cmd_set = (val); write_mem_barrier(); } while (0) 534#define SETP_RWIDTH_HEIGHT(w,h) ((mmtr)s3vMmioMem)->polyfill_regs.regs.rwidth_height = ((w)<<16 | (h)) 535#define SETP_PRDX(val) ((mmtr)s3vMmioMem)->polyfill_regs.regs.prdx = (val) 536#define SETP_PRXSTART(val) ((mmtr)s3vMmioMem)->polyfill_regs.regs.prxstart = (val) 537#define SETP_PLDX(val) ((mmtr)s3vMmioMem)->polyfill_regs.regs.pldx = (val) 538#define SETP_PLXSTART(val) ((mmtr)s3vMmioMem)->polyfill_regs.regs.plxstart = (val) 539#define SETP_PYSTART(val) ((mmtr)s3vMmioMem)->polyfill_regs.regs.pystart = (val) 540#define SETP_PYCNT(val) do { write_mem_barrier(); ((mmtr)s3vMmioMem)->polyfill_regs.regs.pycnt = (val); write_mem_barrier(); } while (0) 541 542/* Cache version */ 543#define CACHE_SETP_CMD_SET(val) do { if (s3vCached_CMD_SET != val) { write_mem_barrier(); ((mmtr)s3vMmioMem)->polyfill_regs.regs.cmd_set = val; s3vCached_CMD_SET = val; s3vCacheMiss++; write_mem_barrier(); } else s3vCacheHit++;} while(0) 544 545 546#define SETL3_Z_BASE(val) ((mmtr)s3vMmioMem)->line3d_regs.regs.z_base = (val) 547#define SETL3_DEST_BASE(val) ((mmtr)s3vMmioMem)->line3d_regs.regs.dest_base = (val) 548#define SETL3_CLIP_L_R(l,r) ((mmtr)s3vMmioMem)->line3d_regs.regs.clip_l_r = ((l)<<16 | (r)) 549#define SETL3_CLIP_T_B(t,b) ((mmtr)s3vMmioMem)->line3d_regs.regs.clip_t_b = ((t)<<16 | (b)) 550#define SETL3_DEST_SRC_STR(d,s) ((mmtr)s3vMmioMem)->line3d_regs.regs.dest_src_str = ((d)<<16 | (s)) 551#define SETL3_Z_STRIDE(val) ((mmtr)s3vMmioMem)->line3d_regs.regs.z_stride = (val) 552#define SETL3_FOG_CLR(val) ((mmtr)s3vMmioMem)->line3d_regs.regs.fog_clr = (val) 553#define SETL3_CMD_SET(val) do { write_mem_barrier(); ((mmtr)s3vMmioMem)->line3d_regs.regs.cmd_set = (val); write_mem_barrier(); } while (0) 554#define SETL3_DGDY_DBDY(dg,db) ((mmtr)s3vMmioMem)->line3d_regs.regs.dgdy_dbdy = ((dg)<<16 | (db)) 555#define SETL3_DADY_DRDY(da,dr) ((mmtr)s3vMmioMem)->line3d_regs.regs.dady_drdy = ((da)<<16 | (dr)) 556#define SETL3_GS_BS(gs,bs) ((mmtr)s3vMmioMem)->line3d_regs.regs.gs_bs = ((gs)<<16 | (bs)) 557#define SETL3_AS_RS(as,rs) ((mmtr)s3vMmioMem)->line3d_regs.regs.as_rs = ((as)<<16 | (rs)) 558#define SETL3_DZ(val) ((mmtr)s3vMmioMem)->line3d_regs.regs.dz = (val) 559#define SETL3_ZSTART(val) ((mmtr)s3vMmioMem)->line3d_regs.regs.zstart = (val) 560#define SETL3_XEND0_END1(e0,e1) ((mmtr)s3vMmioMem)->line3d_regs.regs.xend0_end1 = ((e0)<<16 | (e1)) 561#define SETL3_DX(val) ((mmtr)s3vMmioMem)->line3d_regs.regs.dx = (val) 562#define SETL3_XSTART(val) ((mmtr)s3vMmioMem)->line3d_regs.regs.xstart = (val) 563#define SETL3_YSTART(val) ((mmtr)s3vMmioMem)->line3d_regs.regs.ystart = (val) 564#define SETL3_YCNT(val) do { write_mem_barrier(); ((mmtr)s3vMmioMem)->line3d_regs.regs.ycnt = (val); write_mem_barrier(); } while (0) 565 566 567 568#define SETT3_Z_BASE(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.z_base = (val) 569#define SETT3_DEST_BASE(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dest_base = (val) 570#define SETT3_CLIP_L_R(l,r) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.clip_l_r = ((l)<<16 | (r)) 571#define SETT3_CLIP_T_B(t,b) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.clip_t_b = ((t)<<16 | (b)) 572#define SETT3_DEST_SRC_STR(d,s) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dest_src_str = ((d)<<16 | (s)) 573#define SETT3_Z_STRIDE(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.z_stride = (val) 574#define SETT3_TEX_BASE(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.tex_base = (val) 575#define SETT3_TEX_BDR_CLR(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.tex_bdr_clr = (val) 576#define SETT3_FOG_CLR(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.fog_clr = (val) 577#define SETT3_COLOR0(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.color0 = (val) 578#define SETT3_COLOR1(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.color1 = (val) 579#define SETT3_CMD_SET(val) do { write_mem_barrier(); ((mmtr)s3vMmioMem)->triangle3d_regs.regs.cmd_set = (val); write_mem_barrier(); } while (0) 580#define SETT3_BV(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.bv = (val) 581#define SETT3_BU(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.bu = (val) 582#define SETT3_DWDX(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dwdx = (val) 583#define SETT3_DWDY(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dwdy = (val) 584#define SETT3_WS(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.ws = (val) 585#define SETT3_DDDX(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dddx = (val) 586#define SETT3_DVDX(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dvdx = (val) 587#define SETT3_DUDX(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dudx = (val) 588#define SETT3_DDDY(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dddy = (val) 589#define SETT3_DVDY(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dvdy = (val) 590#define SETT3_DUDY(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dudy = (val) 591#define SETT3_DS(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.ds = (val) 592#define SETT3_VS(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.vs = (val) 593#define SETT3_US(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.us = (val) 594#define SETT3_DGDX_DBDX(gx,bx) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dgdx_dbdx = ((gx)<<16 | (bx)) 595#define SETT3_DADX_DRDX(ax,rx) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dadx_drdx = ((ax)<<16 | (rx)) 596#define SETT3_DGDY_DBDY(gy,by) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dgdy_dbdy = ((gy)<<16 | (by)) 597#define SETT3_DADY_DRDY(ay,ry) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dady_drdy = ((ay)<<16 | (ry)) 598#define SETT3_GS_BS(gs,bs) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.gs_bs = ((gs)<<16 | (bs)) 599#define SETT3_AS_RS(as,rs) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.as_rs = ((as)<<16 | (rs)) 600#define SETT3_DZDX(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dzdx = (val) 601#define SETT3_DZDY(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dzdy = (val) 602#define SETT3_ZS(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.zs = (val) 603#define SETT3_DXDY12(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dxdy12 = (val) 604#define SETT3_XEND12(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.xend12 = (val) 605#define SETT3_DXDY01(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dxdy01 = (val) 606#define SETT3_XEND01(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.xend01 = (val) 607#define SETT3_DXDY02(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.dxdy02 = (val) 608#define SETT3_XSTART02(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.xstart02 = (val) 609#define SETT3_YSTART(val) ((mmtr)s3vMmioMem)->triangle3d_regs.regs.ystart = (val) 610#define SETT3_Y01_Y12(y01,y12) do { write_mem_barrier(); ((mmtr)s3vMmioMem)->triangle3d_regs.regs.y01_y12 = ((y01)<<16 | (y12)); write_mem_barrier(); } while (0) 611 612 613 614#define DBGOUT(p) /* OUTREG8(0x3bc,p) */ 615 616#endif /* 0 */ 617 618#endif /* _NEWMMIO_H */ 619