sis300_accel.h revision 72b676d7
1/* $XFree86$ */ 2/* $XdotOrg$ */ 3/* 4 * 2D Acceleration for SiS 530, 620, 300, 540, 630, 730. 5 * Definitions for the SIS engine communication 6 * 7 * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1) Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2) Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3) The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Authors: Thomas Winischhofer <thomas@winischhofer.net> 32 * Can-Ru Yeou, SiS Inc. (code base) 33 * 34 */ 35 36#define PATREGSIZE 384 /* Pattern register size. 384 bytes @ 0x8300 */ 37#define BR(x) (0x8200 | (x) << 2) 38#define PBR(x) (0x8300 | (x) << 2) 39 40/* SiS300 engine commands */ 41#define BITBLT 0x00000000 /* Blit */ 42#define COLOREXP 0x00000001 /* Color expand */ 43#define ENCOLOREXP 0x00000002 /* Enhanced color expand */ 44#define MULTIPLE_SCANLINE 0x00000003 /* ? */ 45#define LINE 0x00000004 /* Draw line */ 46#define TRAPAZOID_FILL 0x00000005 /* Fill trapezoid */ 47#define TRANSPARENT_BITBLT 0x00000006 /* Transparent Blit */ 48 49/* source select */ 50#define SRCVIDEO 0x00000000 /* source is video RAM */ 51#define SRCSYSTEM 0x00000010 /* source is system memory */ 52#define SRCCPUBLITBUF SRCSYSTEM /* source is CPU-driven BitBuffer (for color expand) */ 53#define SRCAGP 0x00000020 /* source is AGP memory (?) */ 54 55/* Pattern flags */ 56#define PATFG 0x00000000 /* foreground color */ 57#define PATPATREG 0x00000040 /* pattern in pattern buffer (0x8300) */ 58#define PATMONO 0x00000080 /* mono pattern */ 59 60/* blitting direction */ 61#define X_INC 0x00010000 62#define X_DEC 0x00000000 63#define Y_INC 0x00020000 64#define Y_DEC 0x00000000 65 66/* Clipping flags */ 67#define NOCLIP 0x00000000 68#define NOMERGECLIP 0x04000000 69#define CLIPENABLE 0x00040000 70#define CLIPWITHOUTMERGE 0x04040000 71 72/* Transparency */ 73#define OPAQUE 0x00000000 74#define TRANSPARENT 0x00100000 75 76/* Trapezoid */ 77#define T_XISMAJORL 0x00800000 /* X axis is driving axis (left) */ 78#define T_XISMAJORR 0x01000000 /* X axis is driving axis (right) */ 79#define T_L_Y_INC Y_INC /* left edge direction Y */ 80#define T_L_X_INC X_INC /* left edge direction X */ 81#define T_R_Y_INC 0x00400000 /* right edge direction Y */ 82#define T_R_X_INC 0x00200000 /* right edge direction X */ 83 84/* ? */ 85#define DSTAGP 0x02000000 86#define DSTVIDEO 0x02000000 87 88/* Line */ 89#define LINE_STYLE 0x00800000 90#define NO_RESET_COUNTER 0x00400000 91#define NO_LAST_PIXEL 0x00200000 92 93 94/* Macros to do useful things with the SIS BitBLT engine */ 95 96/* BR(16) (0x8240): 97 98 bit 31 2D engine: 1 is idle, 99 bit 30 3D engine: 1 is idle, 100 bit 29 Command queue: 1 is empty 101 102 bits 28:24: Current CPU driven BitBlt buffer stage bit[4:0] 103 104 bits 15:0: Current command queue length (530/620: 12:0) 105 106*/ 107 108/* BR(16)+2 = 0x8242 */ 109 110/* As sis_dri.c relocated the cmd-q len to the sarea, don't use it directly here */ 111/* #define CmdQueLen pSiS->cmdQueueLen */ 112#define CmdQueLen (*(pSiS->cmdQueueLenPtr)) 113 114#define SiSIdle \ 115 { \ 116 while( (SIS_MMIO_IN16(pSiS->IOBase, BR(16)+2) & 0xE000) != 0xE000){}; \ 117 while( (SIS_MMIO_IN16(pSiS->IOBase, BR(16)+2) & 0xE000) != 0xE000){}; \ 118 while( (SIS_MMIO_IN16(pSiS->IOBase, BR(16)+2) & 0xE000) != 0xE000){}; \ 119 CmdQueLen = (SIS_MMIO_IN16(pSiS->IOBase, 0x8240) & pSiS->CmdQueLenMask) - pSiS->CmdQueLenFix; \ 120 } 121/* (do three times, because 2D engine seems quite unsure about whether or not it's idle) */ 122 123#define SiSSetupSRCBase(base) \ 124 if (CmdQueLen <= 0) SiSIdle;\ 125 SIS_MMIO_OUT32(pSiS->IOBase, BR(0), base);\ 126 CmdQueLen--; 127 128#define SiSSetupSRCPitch(pitch) \ 129 if (CmdQueLen <= 0) SiSIdle;\ 130 SIS_MMIO_OUT16(pSiS->IOBase, BR(1), pitch);\ 131 CmdQueLen--; 132 133#define SiSSetupSRCXY(x,y) \ 134 if (CmdQueLen <= 0) SiSIdle;\ 135 SIS_MMIO_OUT32(pSiS->IOBase, BR(2), (x)<<16 | (y) );\ 136 CmdQueLen--; 137 138#define SiSSetupDSTBase(base) \ 139 if (CmdQueLen <= 0) SiSIdle;\ 140 SIS_MMIO_OUT32(pSiS->IOBase, BR(4), base);\ 141 CmdQueLen--; 142 143#define SiSSetupDSTXY(x,y) \ 144 if (CmdQueLen <= 0) SiSIdle;\ 145 SIS_MMIO_OUT32(pSiS->IOBase, BR(3), (x)<<16 | (y) );\ 146 CmdQueLen--; 147 148#define SiSSetupDSTRect(x,y) \ 149 if (CmdQueLen <= 0) SiSIdle;\ 150 SIS_MMIO_OUT32(pSiS->IOBase, BR(5), (y)<<16 | (x) );\ 151 CmdQueLen--; 152 153#define SiSSetupDSTColorDepth(bpp) \ 154 if(pSiS->VGAEngine != SIS_530_VGA) { \ 155 if (CmdQueLen <= 0) SiSIdle;\ 156 SIS_MMIO_OUT16(pSiS->IOBase, BR(1)+2, bpp);\ 157 CmdQueLen--; \ 158 } 159 160#define SiSSetupRect(w,h) \ 161 if (CmdQueLen <= 0) SiSIdle;\ 162 SIS_MMIO_OUT32(pSiS->IOBase, BR(6), (h)<<16 | (w) );\ 163 CmdQueLen--; 164 165#define SiSSetupPATFG(color) \ 166 if (CmdQueLen <= 0) SiSIdle;\ 167 SIS_MMIO_OUT32(pSiS->IOBase, BR(7), color);\ 168 CmdQueLen--; 169 170#define SiSSetupPATBG(color) \ 171 if (CmdQueLen <= 0) SiSIdle;\ 172 SIS_MMIO_OUT32(pSiS->IOBase, BR(8), color);\ 173 CmdQueLen--; 174 175#define SiSSetupSRCFG(color) \ 176 if (CmdQueLen <= 0) SiSIdle;\ 177 SIS_MMIO_OUT32(pSiS->IOBase, BR(9), color);\ 178 CmdQueLen--; 179 180#define SiSSetupSRCBG(color) \ 181 if (CmdQueLen <= 0) SiSIdle;\ 182 SIS_MMIO_OUT32(pSiS->IOBase, BR(10), color);\ 183 CmdQueLen--; 184 185/* 0x8224 src colorkey high */ 186/* 0x8228 src colorkey low */ 187/* 0x821c dest colorkey high */ 188/* 0x8220 dest colorkey low */ 189#define SiSSetupSRCTrans(color) \ 190 if (CmdQueLen <= 1) SiSIdle;\ 191 SIS_MMIO_OUT32(pSiS->IOBase, 0x8224, color);\ 192 SIS_MMIO_OUT32(pSiS->IOBase, 0x8228, color);\ 193 CmdQueLen -= 2; 194 195#define SiSSetupDSTTrans(color) \ 196 if (CmdQueLen <= 1) SiSIdle;\ 197 SIS_MMIO_OUT32(pSiS->IOBase, 0x821C, color); \ 198 SIS_MMIO_OUT32(pSiS->IOBase, 0x8220, color); \ 199 CmdQueLen -= 2; 200 201#define SiSSetupMONOPAT(p0,p1) \ 202 if (CmdQueLen <= 1) SiSIdle;\ 203 SIS_MMIO_OUT32(pSiS->IOBase, BR(11), p0);\ 204 SIS_MMIO_OUT32(pSiS->IOBase, BR(12), p1);\ 205 CmdQueLen -= 2; 206 207#define SiSSetupClipLT(left,top) \ 208 if (CmdQueLen <= 0) SiSIdle;\ 209 SIS_MMIO_OUT32(pSiS->IOBase, BR(13), ((left) & 0xFFFF) | (top)<<16 );\ 210 CmdQueLen--; 211 212#define SiSSetupClipRB(right,bottom) \ 213 if (CmdQueLen <= 0) SiSIdle;\ 214 SIS_MMIO_OUT32(pSiS->IOBase, BR(14), ((right) & 0xFFFF) | (bottom)<<16 );\ 215 CmdQueLen--; 216 217/* General */ 218#define SiSSetupROP(rop) \ 219 pSiS->CommandReg = (rop) << 8; 220 221#define SiSSetupCMDFlag(flags) \ 222 pSiS->CommandReg |= (flags); 223 224#define SiSDoCMD \ 225 if (CmdQueLen <= 1) SiSIdle;\ 226 SIS_MMIO_OUT32(pSiS->IOBase, BR(15), pSiS->CommandReg); \ 227 CmdQueLen--; \ 228 if(pSiS->VGAEngine != SIS_530_VGA) { \ 229 SIS_MMIO_OUT32(pSiS->IOBase, BR(16), 0);\ 230 CmdQueLen--; \ 231 } else { \ 232 unsigned long temp; \ 233 temp = SIS_MMIO_IN32(pSiS->IOBase, BR(16)); \ 234 (void) temp; \ 235 } \ 236 237/* Line */ 238#define SiSSetupX0Y0(x,y) \ 239 if (CmdQueLen <= 0) SiSIdle;\ 240 SIS_MMIO_OUT32(pSiS->IOBase, BR(2), (y)<<16 | (x) );\ 241 CmdQueLen--; 242 243#define SiSSetupX1Y1(x,y) \ 244 if (CmdQueLen <= 0) SiSIdle;\ 245 SIS_MMIO_OUT32(pSiS->IOBase, BR(3), (y)<<16 | (x) );\ 246 CmdQueLen--; 247 248#define SiSSetupLineCount(c) \ 249 if (CmdQueLen <= 0) SiSIdle;\ 250 SIS_MMIO_OUT16(pSiS->IOBase, BR(6), c);\ 251 CmdQueLen--; 252 253#define SiSSetupStylePeriod(p) \ 254 if (CmdQueLen <= 0) SiSIdle;\ 255 SIS_MMIO_OUT16(pSiS->IOBase, BR(6)+2, p);\ 256 CmdQueLen--; 257 258#define SiSSetupStyleLow(ls) \ 259 if (CmdQueLen <= 0) SiSIdle;\ 260 SIS_MMIO_OUT32(pSiS->IOBase, BR(11), ls);\ 261 CmdQueLen--; 262 263#define SiSSetupStyleHigh(ls) \ 264 if (CmdQueLen <= 0) SiSIdle;\ 265 SIS_MMIO_OUT32(pSiS->IOBase, BR(12), ls);\ 266 CmdQueLen--; 267 268/* Trapezoid */ 269#define SiSSetupYH(y,h) \ 270 if (CmdQueLen <= 0) SiSIdle;\ 271 SIS_MMIO_OUT32(pSiS->IOBase, 0x8208, (y)<<16 | (h) );\ 272 CmdQueLen--; 273 274#define SiSSetupLR(left,right) \ 275 if (CmdQueLen <= 0) SiSIdle;\ 276 SIS_MMIO_OUT32(pSiS->IOBase, 0x820C, (right)<<16 | (left) );\ 277 CmdQueLen--; 278 279#define SiSSetupdL(dxL,dyL) \ 280 if (CmdQueLen <= 0) SiSIdle;\ 281 SIS_MMIO_OUT32(pSiS->IOBase, 0x8244, (dyL)<<16 | (dxL) );\ 282 CmdQueLen--; 283 284#define SiSSetupdR(dxR,dyR) \ 285 if (CmdQueLen <= 0) SiSIdle;\ 286 SIS_MMIO_OUT32(pSiS->IOBase, 0x8248, (dyR)<<16 | (dxR) );\ 287 CmdQueLen--; 288 289#define SiSSetupEL(eL) \ 290 if (CmdQueLen <= 0) SiSIdle;\ 291 SIS_MMIO_OUT32(pSiS->IOBase, 0x824C, eL);\ 292 CmdQueLen--; 293 294#define SiSSetupER(eR) \ 295 if (CmdQueLen <= 0) SiSIdle;\ 296 SIS_MMIO_OUT32(pSiS->IOBase, 0x8250, eR);\ 297 CmdQueLen--; 298 299 300/* Set Pattern register */ 301#define SiSSetPattern(num, value) \ 302 if (CmdQueLen <= 0) SiSIdle; \ 303 SIS_MMIO_OUT32(pSiS->IOBase, (PATTERN_REG + (num * 4)), value); \ 304 CmdQueLen--; 305 306 307/* 3D stuff (used for RENDER) */ 308 309/* 310 * Register Addresses of 300/630/730/(540?) 311 */ 312#define REG_3D_TSFSa 0x8800 313#define REG_3D_TSZa 0x8804 314#define REG_3D_TSXa 0x8808 315#define REG_3D_TSYa 0x880C 316#define REG_3D_TSARGBa 0x8810 317#define REG_3D_TSWGa 0x8814 318#define REG_3D_TSUAa 0x8818 319#define REG_3D_TSVAa 0x881C 320#define REG_3D_TSUBa 0x8820 321#define REG_3D_TSVBa 0x8824 322#define REG_3D_TSUCa 0x8828 323#define REG_3D_TSVCa 0x882C 324 325#define REG_3D_TSFSb 0x8830 326#define REG_3D_TSZb 0x8834 327#define REG_3D_TSXb 0x8838 328#define REG_3D_TSYb 0x883C 329#define REG_3D_TSARGBb 0x8840 330#define REG_3D_TSWGb 0x8844 331#define REG_3D_TSUAb 0x8848 332#define REG_3D_TSVAb 0x884C 333#define REG_3D_TSUBb 0x8850 334#define REG_3D_TSVBb 0x8854 335#define REG_3D_TSUCb 0x8858 336#define REG_3D_TSVCb 0x885C 337 338#define REG_3D_TSFSc 0x8860 339#define REG_3D_TSZc 0x8864 340#define REG_3D_TSXc 0x8868 341#define REG_3D_TSYc 0x886C 342#define REG_3D_TSARGBc 0x8870 343#define REG_3D_TSWGc 0x8874 344#define REG_3D_TSUAc 0x8878 345#define REG_3D_TSVAc 0x887C 346#define REG_3D_TSUBc 0x8880 347#define REG_3D_TSVBc 0x8884 348#define REG_3D_TSUCc 0x8888 349#define REG_3D_TSVCc 0x888C 350 351/* 352 * REG_3D_AGPCmdSetting (89e4h-89f7) 353 */ 354#define REG_3D_AGPCmBase 0x89E4 355#define REG_3D_AGPRmDwNum 0x89E8 356#define REG_3D_AGPTtDwNum 0x89EC 357#define REG_3D_AGPCmFire 0x89F0 358 359#define REG_3D_ParsingSet 0x89F4 360#define REG_3D_PrimitiveSet 0x89F8 361#define REG_3D_ShadeMode 0x89F8 362#define REG_3D_EngineFire 0x89FC 363#define REG_3D_EngineStatus 0x89FC 364#define REG_3D_TEnable 0x8A00 365#define REG_3D_TEnable2 0x8A04 366 367#define REG_3D_ZSet 0x8A08 368#define REG_3D_ZBias 0x8A0C 369#define REG_3D_ZStWriteMask 0x8A10 370 371#define REG_3D_ZAddress 0x8A14 372#define REG_3D_AlphaSet 0x8A18 373#define REG_3D_AlphaAddress 0x8A1C 374#define REG_3D_DstSet 0x8A20 375#define REG_3D_DstAlphaWriteMask 0x8A24 376 377#define REG_3D_DstAddress 0x8A28 378 379#define REG_3D_LinePattern 0x8A2C 380 381#define REG_3D_FogSet 0x8A30 382 383#define REG_3D_FogFarDistance 0x8A34 384#define REG_3D_FogInverseDistance 0x8A38 385#define REG_3D_FogFactorDensity 0x8A3C 386 387#define REG_3D_StencilSet 0x8A44 388#define REG_3D_StencilSet2 0x8A48 389#define REG_3D_StencilAddress 0x8A4C 390 391#define REG_3D_DstBlendMode 0x8A50 392#define REG_3D_SrcBlendMode 0x8A50 393#define REG_3D_ClipTopBottom 0x8A54 394#define REG_3D_ClipLeftRight 0x8A58 395 396#define REG_3D_Brightness 0x8A5C 397 398#define REG_3D_BumpMapSet 0x8A68 399#define REG_3D_BumpMapAddress 0x8A6C 400#define REG_3D_BumpMapPitch 0x8A70 401#define REG_3D_BumpMapMatrix0 0x8A74 402#define REG_3D_BumpMapMatrix1 0x8A78 403 404/* 405 * Texture Registers 406 */ 407#define REG_3D_TextureSet 0x8A7C 408#define REG_3D_TextureWidthHeight 0x8A7C 409#define REG_3D_TextureMip 0x8A80 410 411#define REG_3D_TextureTransparencyColorHigh 0x8A84 412#define REG_3D_TextureTransparencyColorLow 0x8A88 413#define REG_3D_TextureBorderColor 0x8A8C 414#define REG_3D_TextureAddress0 0x8A90 415#define REG_3D_TextureAddress1 0x8A94 416#define REG_3D_TextureAddress2 0x8A98 417#define REG_3D_TextureAddress3 0x8A9C 418#define REG_3D_TextureAddress4 0x8AA0 419#define REG_3D_TextureAddress5 0x8AA4 420#define REG_3D_TextureAddress6 0x8AA8 421#define REG_3D_TextureAddress7 0x8AAC 422#define REG_3D_TextureAddress8 0x8AB0 423#define REG_3D_TextureAddress9 0x8AB4 424#define REG_3D_TextureAddress10 0x8AB8 425#define REG_3D_TextureAddress11 0x8ABC 426#define REG_3D_TexturePitch0 0x8AC0 427#define REG_3D_TexturePitch1 0x8AC0 428#define REG_3D_TexturePitch2 0x8AC4 429#define REG_3D_TexturePitch3 0x8AC4 430#define REG_3D_TexturePitch4 0x8AC8 431#define REG_3D_TexturePitch5 0x8AC8 432#define REG_3D_TexturePitch6 0x8ACC 433#define REG_3D_TexturePitch7 0x8ACC 434#define REG_3D_TexturePitch8 0x8AD0 435#define REG_3D_TexturePitch9 0x8AD0 436#define REG_3D_TexturePitch10 0x8AD4 437 438#define REG_3D_Texture1Set 0x8ADC 439#define REG_3D_Texture1WidthHeight 0x8ADC 440#define REG_3D_Texture1Mip 0x8AE0 441 442#define REG_3D_Texture1TransparencyColorHigh 0x8AE4 443#define REG_3D_Texture1TransparencyColorLow 0x8AE8 444#define REG_3D_Texture1BorderColor 0x8AEC 445#define REG_3D_Texture1Address0 0x8AF0 446#define REG_3D_Texture1Address1 0x8AF4 447#define REG_3D_Texture1Address2 0x8AF8 448#define REG_3D_Texture1Address3 0x8AFC 449#define REG_3D_Texture1Address4 0x8B00 450#define REG_3D_Texture1Address5 0x8B04 451#define REG_3D_Texture1Address6 0x8B08 452#define REG_3D_Texture1Address7 0x8B0C 453#define REG_3D_Texture1Address8 0x8B10 454#define REG_3D_Texture1Address9 0x8B14 455#define REG_3D_Texture1Address10 0x8B18 456#define REG_3D_Texture1Address11 0x8B1C 457#define REG_3D_Texture1Pitch0 0x8B20 458#define REG_3D_Texture1Pitch1 0x8B20 459#define REG_3D_Texture1Pitch2 0x8B24 460#define REG_3D_Texture1Pitch3 0x8B24 461#define REG_3D_Texture1Pitch4 0x8B28 462#define REG_3D_Texture1Pitch5 0x8B28 463#define REG_3D_Texture1Pitch6 0x8B2C 464#define REG_3D_Texture1Pitch7 0x8B2C 465#define REG_3D_Texture1Pitch8 0x8B30 466#define REG_3D_Texture1Pitch9 0x8B30 467#define REG_3D_Texture1Pitch10 0x8B34 468 469#define REG_3D_TextureBlendFactor 0x8B3C 470#define REG_3D_TextureColorBlendSet0 0x8B40 471#define REG_3D_TextureColorBlendSet1 0x8B44 472#define REG_3D_TextureAlphaBlendSet0 0x8B48 473#define REG_3D_TextureAlphaBlendSet1 0x8B4C 474 475#define REG_3D_EndPrimitiveList 0x8B50 476 477#define REG_3D_Stipple0 0x8B60 478 479#define REG_3D_TexturePalette 0x8C00 480 481/* 482 * REG_3D_ParsingSet - Parsing Mask (89F4h-89F7h) 483 */ 484#define MASK_VertexDWSize 0xF0000000 485#define MASK_VertexDataFormat 0x0FFF0000 486#define MASK_PsVertex_HAS_RHW 0x08000000 487#define MASK_PsVertex_HAS_NORMALXYZ 0x04000000 488#define MASK_PsVertex_HAS_DIFFUSE 0x02000000 489#define MASK_PsVertex_HAS_SPECULAR 0x01000000 490#define MASK_PsUVSet 0x00FF0000 491#define MASK_PsVertex_HAS_1SetUV 0x00800000 492#define MASK_PsVertex_HAS_2SetUV 0x00C00000 493#define MASK_PsVertex_HAS_3SetUV 0x00E00000 494#define MASK_PsVertex_HAS_UVSet1 0x00800000 495#define MASK_PsVertex_HAS_UVSet2 0x00400000 496#define MASK_PsVertex_HAS_UVSet3 0x00200000 497#define MASK_PsCullDirection_CCW 0x00008000 498#define MASK_PsShadingMode 0x00007000 499#define MASK_PsTextureFrom 0x000003F0 500#define MASK_PsTexture0FromA 0x00000000 501#define MASK_PsTexture1FromA 0x00000000 502#define MASK_PsTexture1FromB 0x00000040 503#define MASK_PsBumpTextureFromA 0x00000000 504#define MASK_PsBumpTextureFromB 0x00000010 505#define MASK_PsBumpTextureFromC 0x00000020 506#define MASK_PsDataType 0x0000000F 507#define MASK_PsPointList 0x00000000 508#define MASK_PsLineList 0x00000004 509#define MASK_PsLineStrip 0x00000005 510#define MASK_PsTriangleList 0x00000008 511#define MASK_PsTriangleStrip 0x00000009 512#define MASK_PsTriangleFan 0x0000000A 513/* 514 * REG_3D_PrimitiveSet - Fire Primitive Mask (89F8h-89FBh) 515 */ 516#define MASK_DrawPrimitiveCommand 0x00000007 517#define MASK_SetFirePosition 0x00001F00 518#define MASK_BumpTextureFrom 0x00030000 519#define MASK_Texture1From 0x000C0000 520#define MASK_Texture0From 0x00300000 521#define MASK_ShadingMode 0x07000000 522#define MASK_CullDirection 0x08000000 523/* 524 * Command Queue Length Mask (89FCh-89FF) 525 */ 526#define MASK_CmdQueueLen 0x0FFF0000 527 528/* 529 * REG_3D_TEnable - Capability Enable Mask (8A00h-8A03h) 530 */ 531#define MASK_DitherEnable 0x00000001 532#define MASK_BlendEnable 0x00000002 533#define MASK_FogTestEnable 0x00000004 534#define MASK_FogEnable 0x00000008 535#define MASK_SpecularEnable 0x00000010 536#define MASK_FogPerspectiveEnable 0x00000020 537#define MASK_TextureCacheClear 0x00000040 538#define MASK_TextureCacheEnable 0x00000080 539#define MASK_BumpMapEnable 0x00000100 540#define MASK_TexturePerspectiveEnable 0x00000200 541#define MASK_TextureEnable 0x00000400 542#define MASK_CullEnable 0x00000800 543#define MASK_TextureNumUsed 0x0000F000 544#define MASK_AlphaBufferEnable 0x00010000 545#define MASK_AlphaTestEnable 0x00020000 546#define MASK_AlphaWriteEnable 0x00040000 547#define MASK_ZTestEnable 0x00080000 548#define MASK_ZWriteEnable 0x00100000 549#define MASK_StencilBufferEnable 0x00200000 550#define MASK_StencilTestEnable 0x00400000 551#define MASK_StencilWriteEnable 0x00800000 552#define MASK_Texture0TransparencyEnable 0x01000000 553#define MASK_Texture1TransparencyEnable 0x02000000 554#define MASK_TextureAWrapUCorrection 0x04000000 555#define MASK_TextureAWrapVCorrection 0x08000000 556#define MASK_TextureBWrapUCorrection 0x10000000 557#define MASK_TextureBWrapVCorrection 0x20000000 558#define MASK_TextureCWrapUCorrection 0x40000000 559#define MASK_TextureCWrapVCorrection 0x80000000 560 561/* 562 * REG_3D_TEnable2 - Capability Enable Mask2 (8A04h-8A07h) 563 */ 564#define MASK_Texture0BlockTextureEnable 0x00000001 565#define MASK_Texture1BlockTextureEnable 0x00000002 566#define MASK_Texture0AnisotropicEnable 0x00000010 567#define MASK_Texture1AnisotropicEnable 0x00000020 568#define MASK_TextureMipmapBiasEnable 0x00000040 569#define MASK_LinePatternEnable 0x00000100 570#define MASK_StippleAlphaEnable 0x00000200 571#define MASK_StippleEnable 0x00000400 572#define MASK_AntiAliasEnable 0x00000800 573#define MASK_ZMaskWriteEnable 0x00001000 574#define MASK_StencilMaskWriteEnable 0x00002000 575#define MASK_AlphaMaskWriteEnable 0x00004000 576#define MASK_ColorMaskWriteEnable 0x00008000 577#define MASK_ZCacheClear 0x00010000 578#define MASK_ZCacheEnable 0x00020000 579#define MASK_StencilCacheClear 0x00040000 580#define MASK_StencilCacheEnable 0x00080000 581#define MASK_AlphaCacheClear 0x00100000 582#define MASK_AlphaCacheEnable 0x00200000 583#define MASK_ColorCacheClear 0x00400000 584#define MASK_ColorCacheEnable 0x00800000 585 586/* 587 * REG_3D_ZSet -- Define Z Buffer Setting Mask (8A08h-8A0Bh) 588 */ 589#define MASK_ZBufferPitch 0x00000FFF 590#define MASK_ZTestMode 0x00070000 591#define MASK_ZBufferInSystem 0x00080000 592#define MASK_ZBufferFormat 0x01F00000 593 594/* 595 * REG_3D_ZBias -- Define Z Buffer Setting Mask (8A0Ch-8A0Fh) 596 */ 597#define MASK_ZBias 0xFFFFFFFF 598 599/* 600 * REG_3D_ZStWriteMask -- Define Z and Stencil Buffer Mask (8A10h-8A13h) 601 */ 602#define MASK_ZWriteMask 0x00FFFFFF 603 604/* 605 * REG_3D_ZAddress -- Define Z Buffer Base Address(8A14h-8A17h) 606 */ 607#define MASK_ZAddress 0xFFFFFFFF 608 609/* 610 * REG_3D_AlphaSet -- Define Alpha Buffer Setting Mask (8A18h-8A1Bh) 611 */ 612#define MASK_AlphaBufferPitch 0x000003FF 613#define MASK_AlphaRefValue 0x00FF0000 614#define MASK_AlphaTestMode 0x07000000 615#define MASK_AlphaBufferInSystem 0x08000000 616#define MASK_AlphaBufferFormat 0x30000000 617 618/* 619 * REG_3D_AlphaAddress -- Define Alpha Buffer Base Address(8A1Ch-8A1Fh) 620 */ 621#define MASK_AlphaAddress 0xFFFFFFFF 622 623/* 624 * REG_3D_DstSet -- Define Destination Buffer Setting Mask (8A20h-8A23h) 625 */ 626#define MASK_DstBufferPitch 0x00000FFF 627#define MASK_DstBufferFormat 0x000F0000 628#define MASK_DstBufferBitDepth 0x00300000 629#define MASK_DstBufferRgbOrder 0x00400000 630#define MASK_DstBufferInSystem 0x00800000 631#define MASK_Dst7BitFormat 0x007F0000 632#define MASK_ROP2 0x0F000000 633 634/* 635 * REG_3D_DstAlphaWriteMask -- Define Destination/Alpha Buffer Write Mask (8A24h-8A27h) 636 */ 637#define MASK_ColorWriteMask 0x00FFFFFF 638#define MASK_AlphaWriteMask 0xFF000000 639 640/* 641 * REG_3D_DstAddress -- Define Destination Buffer Base Address(8A1Ch-8A1Fh) 642 */ 643#define MASK_DstAddress 0xFFFFFFFF 644 645/* 646 * REG_3D_LinePattern -- Define Line Pattern (8A2Ch-8A2Fh) 647 */ 648#define MASK_LinePatternRepeatFactor 0x00007FFF 649#define MASK_LinePatternLastPixelFlag 0x00008000 650#define MASK_LinePattern 0xFFFF0000 651 652/* 653 * REG_3D_FogSet -- Define Fog Mask (8A30h-8A33h) 654 */ 655#define MASK_FogColor 0x00FFFFFF 656#define MASK_FogMode 0x07000000 657#define MASK_FogZLookup 0x08000000 658 659/* 660 * REG_3D_FogStartEnd -- Define Fog Start End Setting (8A34h-8A37h) 661 */ 662#define MASK_FogFarDistance 0x0007FFFF 663 664/* 665 * REG_3D_FogStartEnd -- Define Fog End Setting (8A38h-8A3Bh) 666 */ 667#define MASK_FogInvFarDistance 0x0007FFFF 668 669#define MASK_FogDensity 0x0003FFFF 670#define MASK_FogFactor 0xFF000000 671 672#define MASK_StencilMaskValue 0x000000FF 673#define MASK_StencilReferenceValue 0x0000FF00 674#define MASK_StencilTestMode 0x07000000 675#define MASK_StencilBufferInSystem 0x08000000 676#define MASK_StencilFormat 0x30000000 677 678#define MASK_StencilMode_ALWAYS 0x07000000 679#define MASK_StencilBufferPitch 0x00000FFF 680#define MASK_StencilZPassOp 0x00007000 681#define MASK_StencilZFailOp 0x00070000 682#define MASK_StencilFailOp 0x00700000 683#define MASK_StencilWriteMask 0xFF000000 684 685#define MASK_StencilZPassOp_REPLACE 0x00002000 686#define MASK_StencilZFailOp_REPLACE 0x00020000 687#define MASK_StencilFailOp_REPLACE 0x00200000 688#define MASK_StencilAddress 0xFFFFFFFF 689 690#define MASK_SrcBlendMode 0x0000000F 691#define MASK_DstBlendMode 0x000000F0 692#define MASK_DSTBLEND_ZERO 0x00000000 693#define MASK_DSTBLEND_ONE 0x00000010 694#define MASK_DSTBLEND_SRC_COLOR 0x00000020 695#define MASK_DSTBLEND_INV_SRC_COLOR 0x00000030 696#define MASK_DSTBLEND_SRC_ALPHA 0x00000040 697#define MASK_DSTBLEND_INV_SRC_ALPHA 0x00000050 698#define MASK_DSTBLEND_DST_ALPHA 0x00000060 699#define MASK_DSTBLEND_INV_DST_ALPHA 0x00000070 700#define MASK_DSTBLEND_DST_COLOR 0x00000080 701#define MASK_DSTBLEND_INV_DST_COLOR 0x00000090 702#define MASK_DSTBLEND_SRC_ALPHA_SAT 0x000000A0 703 704#define MASK_SRCBLEND_ZERO 0x00000000 705#define MASK_SRCBLEND_ONE 0x00000001 706#define MASK_SRCBLEND_SRC_COLOR 0x00000002 707#define MASK_SRCBLEND_INV_SRC_COLOR 0x00000003 708#define MASK_SRCBLEND_SRC_ALPHA 0x00000004 709#define MASK_SRCBLEND_INV_SRC_ALPHA 0x00000005 710#define MASK_SRCBLEND_DST_ALPHA 0x00000006 711#define MASK_SRCBLEND_INV_DST_ALPHA 0x00000007 712#define MASK_SRCBLEND_DST_COLOR 0x00000008 713#define MASK_SRCBLEND_INV_DST_COLOR 0x00000009 714#define MASK_SRCBLEND_SRC_ALPHA_SAT 0x0000000A 715#define MASK_SRCBLEND_BOTH_SRC_ALPHA 0x0000000B 716#define MASK_SRCBLEND_BOTH_INV_SRC_ALPHA 0x0000000C 717 718#define MASK_BottomClip 0x00001FFF 719#define MASK_TopClip 0x03FFE000 720 721#define MASK_RightClip 0x00001FFF 722#define MASK_LeftClip 0x03FFE000 723 724#define MASK_BMMemoryInSystem 0x00000080 725#define MASK_BMHeight 0x00000F00 726#define MASK_BMWidth 0x0000F000 727#define MASK_BMFilter 0x00010000 728#define MASK_BMMappingMode 0x007E0000 729#define MASK_BMFormat 0x07800000 730#define MASK_BMTxBumpmap 0x08000000 731 732#define MASK_BMAddress 0xFFFFFFFC 733 734#define MASK_BMOffset 0xFF800000 735#define MASK_BMScale 0x007FE000 736#define MASK_BMPitch 0x00001FFF 737 738#define MASK_BMMatrix00 0x000007FF 739#define MASK_BMMatrix01 0x07FF0000 740#define MASK_BMMatrix10 0x000007FF 741#define MASK_BMMatrix11 0x07FF0000 742 743#define MASK_TextureHeight 0x0000000F 744#define MASK_TextureWidth 0x000000F0 745#define MASK_TextureLevel 0x00000F00 746#define MASK_TextureSignYUVFormat 0x00001000 747#define MASK_TextureMappingMode 0x00FF0000 748#define MASK_TextureWrapU 0x00010000 749#define MASK_TextureWrapV 0x00020000 750#define MASK_TextureMirrorU 0x00040000 751#define MASK_TextureMirrorV 0x00080000 752#define MASK_TextureClampU 0x00100000 753#define MASK_TextureClampV 0x00200000 754#define MASK_TextureBorderU 0x00400000 755#define MASK_TextureBorderV 0x00800000 756#define MASK_TextureFormat 0xFF000000 757#define MASK_TextureBitDepth 0x70000000 758#define MASK_TextureRgbOrder 0x80000000 759 760#define MASK_TextureAnisotropyRatio 0x0000000F 761#define MASK_TextureMipmapLodBias 0x00003FF0 762#define MASK_TextureFilterMin 0x0001C000 763#define MASK_TextureFilterMag 0x00020000 764#define MASK_TextureFilter 0x0003C000 765#define MASK_TextureLevelInSystem 0x3FFC0000 766#define MASK_TextureLevel0InSystem 0x00040000 767#define MASK_TextureBlockLength 0xF0000000 768 769#define MASK_TextureTransparencyColorHighB 0x000000FF 770#define MASK_TextureTransparencyColorHighG 0x0000FF00 771#define MASK_TextureTransparencyColorHighR 0x00FF0000 772#define MASK_TextureAlphaTransparencyMode 0x08000000 773 774#define MASK_TextureTransparencyColorLowB 0x000000FF 775#define MASK_TextureTransparencyColorLowG 0x0000FF00 776#define MASK_TextureTransparencyColorLowR 0x00FF0000 777#define MASK_TextureBlockHeight 0x07000000 778#define MASK_TextureBlockWidth 0x70000000 779 780#define MASK_TextureBorderColorB 0x000000FF 781#define MASK_TextureBorderColorG 0x0000FF00 782#define MASK_TextureBorderColorR 0x00FF0000 783#define MASK_TextureBorderColorA 0xFF000000 784 785#define MASK_TexturePitchOdd 0x000003FF 786#define MASK_TexturePitchEven 0x03FF0000 787#define SHIFT_TexturePitchEven 16 788 789#define MASK_TextureRealInSystem 0x00000001 790#define MASK_TextureDowngrade 0x00000002 791 792#define OP_3D_POINT_DRAW 0x00000000 793#define OP_3D_LINE_DRAW 0x00000001 794#define OP_3D_TRIANGLE_DRAW 0x00000002 795 796#define OP_3D_DIRECTION_RIGHT 0x00000000 797#define OP_3D_DIRECTION_LEFT 0x00000100 798#define OP_3D_DIRECTION_HORIZONTAL 0x00000000 799#define OP_3D_DIRECTION_VERTICAL 0x00000100 800 801#define OP_3D_FIRE_TFIRE 0x00000000 802#define OP_3D_FIRE_TSARGBa 0x00000100 803#define OP_3D_FIRE_TSWa 0x00000200 804#define OP_3D_FIRE_TSVAa 0x00000300 805#define OP_3D_FIRE_TSVBa 0x00000400 806#define OP_3D_FIRE_TSVCa 0x00000500 807 808#define OP_3D_FIRE_TSARGBb 0x00000900 809#define OP_3D_FIRE_TSWb 0x00000a00 810#define OP_3D_FIRE_TSVAb 0x00000b00 811#define OP_3D_FIRE_TSVBb 0x00000c00 812#define OP_3D_FIRE_TSVCb 0x00000d00 813 814#define OP_3D_FIRE_TSARGBc 0x00001100 815#define OP_3D_FIRE_TSWc 0x00001200 816#define OP_3D_FIRE_TSVAc 0x00001300 817#define OP_3D_FIRE_TSVBc 0x00001400 818#define OP_3D_FIRE_TSVCc 0x00001500 819 820#define OP_3D_Texture0FromA 0x00000000 821#define OP_3D_Texture0FromB 0x00100000 822#define OP_3D_Texture0FromC 0x00200000 823#define OP_3D_Texture1FromA 0x00000000 824#define OP_3D_Texture1FromB 0x00040000 825#define OP_3D_Texture1FromC 0x00080000 826#define OP_3D_TextureBumpFromA 0x00000000 827#define OP_3D_TextureBumpFromB 0x00010000 828#define OP_3D_TextureBumpFromC 0x00020000 829 830#define SHADE_FLAT_VertexA 0x01000000 831#define SHADE_FLAT_VertexB 0x02000000 832#define SHADE_FLAT_VertexC 0x03000000 833#define SHADE_GOURAUD 0x04000000 834 835#define Z_BUFFER_FORMAT_Z16 0x00000000 836#define Z_BUFFER_FORMAT_Z16_INT 0x00100000 837#define Z_BUFFER_FORMAT_S1Z15 0x00400000 838#define Z_BUFFER_FORMAT_S1Z15_INT 0x00500000 839#define Z_BUFFER_FORMAT_Z32 0x00800000 840#define Z_BUFFER_FORMAT_S1Z31 0x00C00000 841#define Z_BUFFER_FORMAT_S2Z30 0x00D00000 842#define Z_BUFFER_FORMAT_S4Z28 0x00E00000 843#define Z_BUFFER_FORMAT_S8Z24 0x00F00000 844#define Z_BUFFER_FORMAT_FZ30 0x01800000 845#define Z_BUFFER_FORMAT_FS1Z30 0x01C00000 846#define Z_BUFFER_FORMAT_FS2Z30 0x01D00000 847#define MASK_Z_BUFFER_FORMAT 0x01F00000 848 849#define ALPHA_BUFFER_FORMAT_1 0x00000000 850#define ALPHA_BUFFER_FORMAT_2 0x10000000 851#define ALPHA_BUFFER_FORMAT_4 0x20000000 852#define ALPHA_BUFFER_FORMAT_8 0x30000000 853 854#define DST_FORMAT_RGB_555 0x00100000 855#define DST_FORMAT_RGB_565 0x00110000 856#define DST_FORMAT_ARGB_1555 0x00120000 857#define DST_FORMAT_ARGB_4444 0x00130000 858#define DST_FORMAT_ARGB_1888 0x00300000 859#define DST_FORMAT_ARGB_2888 0x00310000 860#define DST_FORMAT_ARGB_4888 0x00320000 861#define DST_FORMAT_ARGB_8888 0x00330000 862#define DST_FORMAT_ARGB_0888 0x00340000 863 864#define DST_FORMAT_BGR_555 0x00500000 865#define DST_FORMAT_BGR_565 0x00510000 866#define DST_FORMAT_ABGR_1555 0x00520000 867#define DST_FORMAT_ABGR_4444 0x00530000 868#define DST_FORMAT_ABGR_1888 0x00700000 869#define DST_FORMAT_ABGR_2888 0x00710000 870#define DST_FORMAT_ABGR_4888 0x00720000 871#define DST_FORMAT_ABGR_8888 0x00730000 872#define DST_FORMAT_ABGR_0888 0x00740000 873 874#define MASK_TEXTURE_FORMAT 0xFF000000 875 876#define TEXEL_INDEX1 0x00000000 877#define TEXEL_INDEX2 0x01000000 878#define TEXEL_INDEX4 0x02000000 879#define TEXEL_INDEX8 0x03000000 880 881#define TEXEL_INDEX1WithAlpha 0x04000000 882#define TEXEL_INDEX2WithAlpha 0x05000000 883#define TEXEL_INDEX4WithAlpha 0x06000000 884#define TEXEL_INDEX8WithAlpha 0x07000000 885 886#define TEXEL_I1 0x10000000 887#define TEXEL_I2 0x11000000 888#define TEXEL_I4 0x12000000 889#define TEXEL_I8 0x13000000 890 891#define TEXEL_DXT1 0x19000000 892#define TEXEL_DXT2 0x1A000000 893#define TEXEL_DXT3 0x1B000000 894 895#define TEXEL_YUV422 0x20000000 896#define TEXEL_YVU422 0x21000000 897#define TEXEL_UVY422 0x22000000 898#define TEXEL_VUY422 0x23000000 899#define TEXEL_YUV411 0x24000000 900 901#define TEXEL_L1 0x30000000 902#define TEXEL_L2 0x31000000 903#define TEXEL_L4 0x32000000 904#define TEXEL_L8 0x33000000 905 906#define TEXEL_AL11 0x34000000 907#define TEXEL_AL44 0x35000000 908#define TEXEL_AL26 0x37000000 909#define TEXEL_AL88 0x38000000 910 911#define TEXEL_A1 0x40000000 912#define TEXEL_A2 0x41000000 913#define TEXEL_A4 0x42000000 914#define TEXEL_A8 0x43000000 915 916#define TEXEL_RGB_332_8 0x50000000 917#define TEXEL_RGB_233_8 0x51000000 918#define TEXEL_RGB_232_8 0x52000000 919#define TEXEL_ARGB_1232_8 0x53000000 920#define TEXEL_ARGB_2222_8 0x54000000 921 922#define TEXEL_RGB_555_16 0x60000000 923#define TEXEL_RGB_565_16 0x61000000 924#define TEXEL_ARGB_1555_16 0x62000000 925#define TEXEL_ARGB_4444_16 0x63000000 926 927#define TEXEL_ARGB_1888_32 0x70000000 928#define TEXEL_ARGB_2888_32 0x71000000 929#define TEXEL_ARGB_4888_32 0x72000000 930#define TEXEL_ARGB_8888_32 0x73000000 931#define TEXEL_ARGB_0888_32 0x74000000 932 933#define TEXEL_BGR_332_8 0xD0000000 934#define TEXEL_BGR_233_8 0xD1000000 935#define TEXEL_BGR_232_8 0xD2000000 936#define TEXEL_ABGR_1232_8 0xD3000000 937#define TEXEL_ABGR_2222_8 0xD4000000 938 939#define TEXEL_BGR_555_16 0xE0000000 940#define TEXEL_BGR_565_16 0xE1000000 941#define TEXEL_ABGR_1555_16 0xE2000000 942#define TEXEL_ABGR_4444_16 0xE3000000 943 944#define TEXEL_ABGR_1888_32 0xF0000000 945#define TEXEL_ABGR_2888_32 0xF1000000 946#define TEXEL_ABGR_4888_32 0xF2000000 947#define TEXEL_ABGR_8888_32 0xF3000000 948#define TEXEL_ABGR_0888_32 0xF4000000 949 950#define TEXEL_VU88 0x00000000 951#define TEXEL_LVU655 0x00800000 952#define TEXEL_LVU888 0x01000000 953#define TEXEL_UV88 0x02000000 954#define TEXEL_LUV655 0x02800000 955#define TEXEL_LUV888 0x03000000 956 957#define FOGMODE_CHEAP 0x04000000 958#define FOGMODE_LINEAR 0x05000000 959#define FOGMODE_EXP 0x06000000 960#define FOGMODE_EXP2 0x07000000 961 962#define Z_16 0x00000000 963#define S_1_Z_15 0x00400000 964#define Z_32 0x00800000 965#define S_1_Z_31 0x00c00000 966#define S_2_Z_30 0x00d00000 967#define S_4_Z_28 0x00e00000 968#define S_8_Z_24 0x00f00000 969 970#define S_1 0x00000000 971#define S_2 0x10000000 972#define S_4 0x20000000 973#define S_8 0x30000000 974 975#define TEXTURE_FILTER_NEAREST 0x00000000 976#define TEXTURE_FILTER_LINEAR 0x00004000 977#define TEXTURE_FILTER_NEAREST_MIP_NEAREST 0x00008000 978#define TEXTURE_FILTER_NEAREST_MIP_LINEAR 0x00010000 979#define TEXTURE_FILTER_LINEAR_MIP_NEAREST 0x0000c000 980#define TEXTURE_FILTER_LINEAR_MIP_LINEAR 0x00014000 981 982#define A_REPLACE_RGB_STAGE0 0xa1485000 983#define A_REPLACE_A_STAGE0 0xc3230000 984#define L_REPLACE__RGB_STAGE0 0xc1485000 985#define L_REPLACE__A_STAGE0 0x63230000 986#define LA_REPLACE__RGB_STAGE0 0xc1485000 987#define LA_REPLACE__A_STAGE0 0xc3230000 988#define I_REPLACE__RGB_STAGE0 0xc1485000 989#define I_REPLACE__A_STAGE0 0xc3230000 990#define RGB_REPLACE__RGB_STAGE0 0xc1485000 991#define RGB_REPLACE__A_STAGE0 0x63230000 992#define RGBA_REPLACE__RGB_STAGE0 0xc1485000 993#define RGBA_REPLACE__A_STAGE0 0xc3230000 994 995#define A_MODULATE_RGB_STAGE0 0xa1485000 996#define A_MODULATE_A_STAGE0 0x63c30000 997#define L_MODULATE__RGB_STAGE0 0xa1705000 998#define L_MODULATE__A_STAGE0 0x63230000 999#define LA_MODULATE__RGB_STAGE0 0xa1705000 1000#define LA_MODULATE__A_STAGE0 0x63c30000 1001#define I_MODULATE__RGB_STAGE0 0xa1705000 1002#define I_MODULATE__A_STAGE0 0x63c30000 1003#define RGB_MODULATE__RGB_STAGE0 0xa1705000 1004#define RGB_MODULATE__A_STAGE0 0x63230000 1005#define RGBA_MODULATE__RGB_STAGE0 0xa1705000 1006#define RGBA_MODULATE__A_STAGE0 0x63c30000 1007 1008#define RGB_DECAL__RGB_STAGE0 0xc1485000 1009#define RGB_DECAL__A_STAGE0 0x63230000 1010#define RGBA_DECAL__RGB_STAGE0 0xc534c001 1011#define RGBA_DECAL__A_STAGE0 0x63230000 1012 1013#define A_BLEND_RGB_STAGE0 0xa1485000 1014#define A_BLEND_A_STAGE0 0x63c30000 1015#define L_BLEND__RGB_STAGE0 0x4530c001 1016#define L_BLEND__A_STAGE0 0x63230000 1017#define LA_BLEND__RGB_STAGE0 0x4530c001 1018#define LA_BLEND__A_STAGE0 0x63c30000 1019#define I_BLEND__RGB_STAGE0 0x4530c001 1020#define I_BLEND__A_STAGE0 0x46c60001 1021#define RGB_BLEND__RGB_STAGE0 0x4530c001 1022#define RGB_BLEND__A_STAGE0 0x63230000 1023#define RGBA_BLEND__RGB_STAGE0 0x4530c001 1024#define RGBA_BLEND__A_STAGE0 0x63c30000 1025 1026#define RGB_STAGE1 0xa1485000 1027#define A_STAGE1 0xa3230000 1028 1029#define A_REPLACE_RGB_STAGE1 0xa1485000 1030#define A_REPLACE_A_STAGE1 0xe3230000 1031#define L_REPLACE__RGB_STAGE1 0xe1485000 1032#define L_REPLACE__A_STAGE1 0xa3230000 1033#define LA_REPLACE__RGB_STAGE1 0xe1485000 1034#define LA_REPLACE__A_STAGE1 0xe3230000 1035#define I_REPLACE__RGB_STAGE1 0xe1485000 1036#define I_REPLACE__A_STAGE1 0xe3230000 1037#define RGB_REPLACE__RGB_STAGE1 0xe1485000 1038#define RGB_REPLACE__A_STAGE1 0xa3230000 1039#define RGBA_REPLACE__RGB_STAGE1 0xe1485000 1040#define RGBA_REPLACE__A_STAGE1 0xe3230000 1041 1042#define A_MODULATE_RGB_STAGE1 0xa1485000 1043#define A_MODULATE_A_STAGE1 0xa3e30000 1044#define L_MODULATE__RGB_STAGE1 0xa1785000 1045#define L_MODULATE__A_STAGE1 0xa3230000 1046#define LA_MODULATE__RGB_STAGE1 0xa1785000 1047#define LA_MODULATE__A_STAGE1 0xa3e30000 1048#define I_MODULATE__RGB_STAGE1 0xa1785000 1049#define I_MODULATE__A_STAGE1 0xa3e30000 1050#define RGB_MODULATE__RGB_STAGE1 0xa1785000 1051#define RGB_MODULATE__A_STAGE1 0xa3230000 1052#define RGBA_MODULATE__RGB_STAGE1 0xa1785000 1053#define RGBA_MODULATE__A_STAGE1 0xa3e30000 1054 1055#define RGB_DECAL__RGB_STAGE1 0xe1485000 1056#define RGB_DECAL__A_STAGE1 0xa3230000 1057#define RGBA_DECAL__RGB_STAGE1 0xe5394001 1058#define RGBA_DECAL__A_STAGE1 0xa3230000 1059 1060#define A_BLEND_RGB_STAGE1 0xa1485000 1061#define A_BLEND_A_STAGE1 0xa3e30000 1062#define L_BLEND__RGB_STAGE1 0x45394001 1063#define L_BLEND__A_STAGE1 0xa3230000 1064#define LA_BLEND__RGB_STAGE1 0x45394001 1065#define LA_BLEND__A_STAGE1 0xa3e30000 1066#define I_BLEND__RGB_STAGE1 0x45394001 1067#define I_BLEND__A_STAGE1 0x4aea0001 1068#define RGB_BLEND__RGB_STAGE1 0x45394001 1069#define RGB_BLEND__A_STAGE1 0xa3230000 1070#define RGBA_BLEND__RGB_STAGE1 0x45394001 1071#define RGBA_BLEND__A_STAGE1 0xa3e30000 1072 1073 1074#define INIT_6327_CapsEnable 0x00000080 1075#define INIT_6327_CapsEnable2 0x00000000 1076 1077#define INIT_6327_ZSet 0x00030000 1078#define INIT_6327_ZMask 0xffffffff 1079#define INIT_6327_AlphaSet 0x07000000 1080#define INIT_6327_DstSet 0x0C000000 1081#define INIT_6327_DstMask 0xffffffff 1082#define INIT_6327_FogSet 0x04000000 1083#define INIT_6327_BlendMode 0x00000001 1084#define INIT_6327_TextureSet 0x00030000 1085#define INIT_6327_TextureMip 0x00000000 1086#define INIT_6327_TextureColorBlend0 0xC1485000 1087#define INIT_6327_TextureAlphaBlend0 0x333A0000 1088#define INIT_6327_Texture1Set 0x00030000 1089#define INIT_6327_Texture1Set2 0x00000000 1090#define INIT_6327_TextureColorBlend1 0x294B4000 1091#define INIT_6327_TextureAlphaBlend1 0x333A0000 1092#define INIT_6327_ParsingSet 0x00000060 1093 1094#define SiS_Z_COMP_NEVER 0x00000000 1095#define SiS_Z_COMP_S_LT_B 0x00010000 1096#define SiS_Z_COMP_S_EQ_B 0x00020000 1097#define SiS_Z_COMP_S_LE_B 0x00030000 1098#define SiS_Z_COMP_S_GT_B 0x00040000 1099#define SiS_Z_COMP_S_NE_B 0x00050000 1100#define SiS_Z_COMP_S_GE_B 0x00060000 1101#define SiS_Z_COMP_ALWAYS 0x00070000 1102 1103#define SiS_ALPHA_NEVER 0x00000000 1104#define SiS_ALPHA_LESS 0x01000000 1105#define SiS_ALPHA_EQUAL 0x02000000 1106#define SiS_ALPHA_LEQUAL 0x03000000 1107#define SiS_ALPHA_GREATER 0x04000000 1108#define SiS_ALPHA_NOTEQUAL 0x05000000 1109#define SiS_ALPHA_GEQUAL 0x06000000 1110#define SiS_ALPHA_ALWAYS 0x07000000 1111 1112#define SiS_STENCIL_NEVER 0x00000000 1113#define SiS_STENCIL_LESS 0x01000000 1114#define SiS_STENCIL_EQUAL 0x02000000 1115#define SiS_STENCIL_LEQUAL 0x03000000 1116#define SiS_STENCIL_GREATER 0x04000000 1117#define SiS_STENCIL_NOTEQUAL 0x05000000 1118#define SiS_STENCIL_GEQUAL 0x06000000 1119#define SiS_STENCIL_ALWAYS 0x07000000 1120 1121#define SiS_SFAIL_KEEP 0x00000000 1122#define SiS_SFAIL_ZERO 0x00100000 1123#define SiS_SFAIL_REPLACE 0x00200000 1124#define SiS_SFAIL_INVERT 0x00500000 1125#define SiS_SFAIL_INCR 0x00600000 1126#define SiS_SFAIL_DECR 0x00700000 1127 1128#define SiS_SPASS_ZFAIL_KEEP 0x00000000 1129#define SiS_SPASS_ZFAIL_ZERO 0x00010000 1130#define SiS_SPASS_ZFAIL_REPLACE 0x00020000 1131#define SiS_SPASS_ZFAIL_INVERT 0x00050000 1132#define SiS_SPASS_ZFAIL_INCR 0x00060000 1133#define SiS_SPASS_ZFAIL_DECR 0x00070000 1134 1135#define SiS_SPASS_ZPASS_KEEP 0x00000000 1136#define SiS_SPASS_ZPASS_ZERO 0x00001000 1137#define SiS_SPASS_ZPASS_REPLACE 0x00002000 1138#define SiS_SPASS_ZPASS_INVERT 0x00005000 1139#define SiS_SPASS_ZPASS_INCR 0x00006000 1140#define SiS_SPASS_ZPASS_DECR 0x00007000 1141 1142#define SiS_D_ZERO 0x00000000 1143#define SiS_D_ONE 0x00000010 1144#define SiS_D_SRC_COLOR 0x00000020 1145#define SiS_D_ONE_MINUS_SRC_COLOR 0x00000030 1146#define SiS_D_SRC_ALPHA 0x00000040 1147#define SiS_D_ONE_MINUS_SRC_ALPHA 0x00000050 1148#define SiS_D_DST_ALPHA 0x00000060 1149#define SiS_D_ONE_MINUS_DST_ALPHA 0x00000070 1150 1151#define SiS_S_ZERO 0x00000000 1152#define SiS_S_ONE 0x00000001 1153#define SiS_S_SRC_ALPHA 0x00000004 1154#define SiS_S_ONE_MINUS_SRC_ALPHA 0x00000005 1155#define SiS_S_DST_ALPHA 0x00000006 1156#define SiS_S_ONE_MINUS_DST_ALPHA 0x00000007 1157#define SiS_S_DST_COLOR 0x00000008 1158#define SiS_S_ONE_MINUS_DST_COLOR 0x00000009 1159#define SiS_S_SRC_ALPHA_SATURATE 0x0000000a 1160 1161/* Logic Op */ 1162#define LOP_CLEAR 0x00000000 1163#define LOP_NOR 0x01000000 1164#define LOP_AND_INVERTED 0x02000000 1165#define LOP_COPY_INVERTED 0x03000000 1166#define LOP_AND_REVERSE 0x04000000 1167#define LOP_INVERT 0x05000000 1168#define LOP_XOR 0x06000000 1169#define LOP_NAND 0x07000000 1170#define LOP_AND 0x08000000 1171#define LOP_EQUIV 0x09000000 1172#define LOP_NOOP 0x0a000000 1173#define LOP_OR_INVERTED 0x0b000000 1174#define LOP_COPY 0x0c000000 1175#define LOP_OR_REVERSE 0x0d000000 1176#define LOP_OR 0x0e000000 1177#define LOP_SET 0x0f000000 1178 1179#define SiSWait3DCmdQueue(wLen)\ 1180do{ \ 1181 while ( CmdQueLen < (int)(wLen)) { \ 1182 CmdQueLen = (SIS_MMIO_IN16(pSiS->IOBase, 0x8240) & pSiS->CmdQueLenMask) - pSiS->CmdQueLenFix; \ 1183 } \ 1184 CmdQueLen -= (int)(wLen); \ 1185} while(0) 1186 1187