sis_regs.h revision 72b676d7
1/* $XFree86$ */ 2/* $XdotOrg$ */ 3/* 4 * Register access macros and register definitions 5 * 6 * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1) Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2) Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3) The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 */ 31 32#ifndef _SIS_REGS_H_ 33#define _SIS_REGS_H_ 34 35/* 36#define SIS_NEED_inSISREG 37#define SIS_NEED_inSISREGW 38#define SIS_NEED_inSISREGL 39#define SIS_NEED_outSISREG 40#define SIS_NEED_outSISREGW 41#define SIS_NEED_outSISREGL 42#define SIS_NEED_orSISREG 43#define SIS_NEED_andSISREG 44#define SIS_NEED_inSISIDXREG 45#define SIS_NEED_outSISIDXREG 46#define SIS_NEED_orSISIDXREG 47#define SIS_NEED_andSISIDXREG 48#define SIS_NEED_setSISIDXREG 49#define SIS_NEED_setSISIDXREGmask 50*/ 51 52/* Video RAM access macros */ 53 54/* (Currently, these are use on all platforms; USB2VGA is handled 55 * entirely different in a dedicated driver) 56 */ 57 58/* dest is video RAM, src is system RAM */ 59#define sisfbwritel(dest, data) *(dest) = (data) 60#define sisfbwritelinc(dest, data) *((dest)++) = (data) 61#define sisfbwritelp(dest, dataptr) *(dest) = *(dataptr) 62#define sisfbwritelpinc(dest, dataptr) *((dest)++) = *((dataptr)++) 63 64#define sisfbwritew(dest, data) *(dest) = (data) 65#define sisfbwritewinc(dest, data) *((dest)++) = (data) 66#define sisfbwritewp(dest, dataptr) *(dest) = *(dataptr) 67#define sisfbwritewpinc(dest, dataptr) *((dest)++) = *((dataptr)++) 68 69#define sisfbwriteb(dest, data) *(dest) = (data) 70#define sisfbwritebinc(dest, data) *((dest)++) = (data) 71#define sisfbwritebp(dest, dataptr) *(dest) = *(dataptr) 72#define sisfbwritebpinc(dest, dataptr) *((dest)++) = *((dataptr)++) 73 74/* Source is video RAM */ 75#define sisfbreadl(src) *(src) 76#define sisfbreadlinc(src) *((src)++) 77 78#define sisfbreadw(src) *(src) 79#define sisfbreadwinc(src) *((src)++) 80 81#define sisfbreadb(src) *(src) 82#define sisfbreadbinc(src) *((src)++) 83 84/* Register access macros --------------- */ 85 86#ifndef SISUSEDEVPORT 87 88#define inSISREG(base) inb(base) 89#define inSISREGW(base) inw(base) 90#define inSISREGL(base) inl(base) 91 92#define outSISREG(base,val) outb(base,val) 93#define outSISREGW(base,val) outw(base,val) 94#define outSISREGL(base,val) outl(base,val) 95 96#define orSISREG(base,val) \ 97 do { \ 98 UChar __Temp = inSISREG(base); \ 99 outSISREG(base, __Temp | (val)); \ 100 } while (0) 101 102#define andSISREG(base,val) \ 103 do { \ 104 UChar __Temp = inSISREG(base); \ 105 outSISREG(base, __Temp & (val)); \ 106 } while (0) 107 108#define inSISIDXREG(base,idx,var) \ 109 do { \ 110 outSISREG(base, idx); \ 111 var = inSISREG((base)+1); \ 112 } while (0) 113 114#define outSISIDXREG(base,idx,val) \ 115 do { \ 116 outSISREG(base, idx); \ 117 outSISREG((base)+1, val); \ 118 } while (0) 119 120#define orSISIDXREG(base,idx,val) \ 121 do { \ 122 UChar __Temp; \ 123 outSISREG(base, idx); \ 124 __Temp = inSISREG((base)+1) | (val); \ 125 outSISREG((base)+1, __Temp); \ 126 } while (0) 127 128#define andSISIDXREG(base,idx,and) \ 129 do { \ 130 UChar __Temp; \ 131 outSISREG(base, idx); \ 132 __Temp = inSISREG((base)+1) & (and); \ 133 outSISREG((base)+1, __Temp); \ 134 } while (0) 135 136#define setSISIDXREG(base,idx,and,or) \ 137 do { \ 138 UChar __Temp; \ 139 outSISREG(base, idx); \ 140 __Temp = (inSISREG((base)+1) & (and)) | (or); \ 141 outSISREG((base)+1, __Temp); \ 142 } while (0) 143 144#define setSISIDXREGmask(base,idx,data,mask) \ 145 do { \ 146 UChar __Temp; \ 147 outSISREG(base, idx); \ 148 __Temp = (inSISREG((base)+1)) & (~(mask));\ 149 __Temp |= ((data) & (mask)); \ 150 outSISREG((base)+1, __Temp); \ 151 } while(0) 152 153#else /* USEDEVPORT */ 154 155extern int sisdevport; 156 157/* Note to self: SEEK_SET is faster than SEEK_CUR */ 158 159#ifdef SIS_NEED_inSISREG 160static UChar inSISREG(ULong base) 161{ 162 UChar tmp; 163 lseek(sisdevport, base, SEEK_SET); 164 read(sisdevport, &tmp, 1); 165 return tmp; 166} 167#endif 168 169#ifdef SIS_NEED_inSISREGW 170static __inline UShort inSISREGW(ULong base) 171{ 172 UShort tmp; 173 lseek(sisdevport, base, SEEK_SET); 174 read(sisdevport, &tmp, 2); 175 return tmp; 176} 177#endif 178 179#ifdef SIS_NEED_inSISREGL 180static __inline unsigned int inSISREGL(ULong base) 181{ 182 ULong tmp; 183 lseek(sisdevport, base, SEEK_SET); 184 read(sisdevport, &tmp, 4); 185 return tmp; 186} 187#endif 188 189#ifdef SIS_NEED_outSISREG 190static void outSISREG(ULong base, UChar val) 191{ 192 lseek(sisdevport, base, SEEK_SET); 193 write(sisdevport, &val, 1); 194} 195#endif 196 197#ifdef SIS_NEED_outSISREGW 198static __inline void outSISREGW(ULong base, UShort val) 199{ 200 lseek(sisdevport, base, SEEK_SET); 201 write(sisdevport, &val, 2); 202} 203#endif 204 205#ifdef SIS_NEED_outSISREGL 206static __inline void outSISREGL(ULong base, unsigned int val) 207{ 208 lseek(sisdevport, base, SEEK_SET); 209 write(sisdevport, &val, 4); 210} 211#endif 212 213#ifdef SIS_NEED_orSISREG 214static void orSISREG(ULong base, UChar val) 215{ 216 UChar tmp; 217 lseek(sisdevport, base, SEEK_SET); 218 read(sisdevport, &tmp, 1); 219 tmp |= val; 220 lseek(sisdevport, base, SEEK_SET); 221 write(sisdevport, &tmp, 1); 222} 223#endif 224 225#ifdef SIS_NEED_andSISREG 226static void andSISREG(ULong base, UChar val) 227{ 228 UChar tmp; 229 lseek(sisdevport, base, SEEK_SET); 230 read(sisdevport, &tmp, 1); 231 tmp &= val; 232 lseek(sisdevport, base, SEEK_SET); 233 write(sisdevport, &tmp, 1); 234} 235#endif 236 237#ifdef SIS_NEED_outSISIDXREG 238static void outSISIDXREG(ULong base, UChar idx, UChar val) 239{ 240 UChar value[2]; 241 value[0] = idx; /* sic! reads/writes bytewise! */ 242 value[1] = val; 243 lseek(sisdevport, base, SEEK_SET); 244 write(sisdevport, &value[0], 2); 245} 246#endif 247 248#ifdef SIS_NEED_inSISIDXREG 249static UChar __inSISIDXREG(ULong base, UChar idx) 250{ 251 UChar tmp; 252 lseek(sisdevport, base, SEEK_SET); 253 write(sisdevport, &idx, 1); 254 read(sisdevport, &tmp, 1); 255 return tmp; 256} 257#define inSISIDXREG(base,idx,var) var = __inSISIDXREG(base, idx); 258#endif 259 260#ifdef SIS_NEED_orSISIDXREG 261static void orSISIDXREG(ULong base, UChar idx, UChar val) 262{ 263 UChar tmp; 264 lseek(sisdevport, base, SEEK_SET); 265 write(sisdevport, &idx, 1); 266 read(sisdevport, &tmp, 1); 267 tmp |= val; 268 lseek(sisdevport, base + 1, SEEK_SET); 269 write(sisdevport, &tmp, 1); 270} 271#endif 272 273#ifdef SIS_NEED_andSISIDXREG 274static void andSISIDXREG(ULong base, UChar idx, UChar val) 275{ 276 UChar tmp; 277 lseek(sisdevport, base, SEEK_SET); 278 write(sisdevport, &idx, 1); 279 read(sisdevport, &tmp, 1); 280 tmp &= val; 281 lseek(sisdevport, base + 1, SEEK_SET); 282 write(sisdevport, &tmp, 1); 283} 284#endif 285 286#ifdef SIS_NEED_setSISIDXREG 287static void setSISIDXREG(ULong base, UChar idx, 288 UChar myand, UChar myor) 289{ 290 UChar tmp; 291 lseek(sisdevport, base, SEEK_SET); 292 write(sisdevport, &idx, 1); 293 read(sisdevport, &tmp, 1); 294 tmp &= myand; 295 tmp |= myor; 296 lseek(sisdevport, base + 1, SEEK_SET); 297 write(sisdevport, &tmp, 1); 298} 299#endif 300 301#ifdef SIS_NEED_setSISIDXREGmask 302static void setSISIDXREGmask(ULong base, UChar idx, 303 UChar data, UChar mask) 304{ 305 UChar tmp; 306 lseek(sisdevport, base, SEEK_SET); 307 write(sisdevport, &idx, 1); 308 read(sisdevport, &tmp, 1); 309 tmp &= ~(mask); 310 tmp |= (data & mask); 311 lseek(sisdevport, base + 1, SEEK_SET); 312 write(sisdevport, &tmp, 1); 313} 314#endif 315 316#endif /* SISUSEDEVPORT */ 317 318/* Video RAM and MMIO access macros ----- */ 319 320#define sisclearvram(where, howmuch) bzero(where, howmuch) 321 322/* MMIO */ 323#define SIS_MMIO_OUT8 MMIO_OUT8 324#define SIS_MMIO_OUT16 MMIO_OUT16 325#define SIS_MMIO_OUT32 MMIO_OUT32 326 327#define SIS_MMIO_IN8 MMIO_IN8 328#define SIS_MMIO_IN16 MMIO_IN16 329#define SIS_MMIO_IN32 MMIO_IN32 330 331/* VRAM queue acceleration */ 332 333#define SiSWriteQueue(tt) 334 335#define SIS_WQINDEX(i) ((CARD32 *)(tt))[(i)] 336 337#define SIS_RQINDEX(i) ((volatile CARD32 *)(tt))[(i)] 338 339/* Port offsets --------------- */ 340 341#define AROFFSET 0x40 342#define ARROFFSET 0x41 343#define GROFFSET 0x4e 344#define SROFFSET 0x44 345#define CROFFSET 0x54 346#define MISCROFFSET 0x4c 347#define MISCWOFFSET 0x42 348#define INPUTSTATOFFSET 0x5A 349#define PART1OFFSET 0x04 350#define PART2OFFSET 0x10 351#define PART3OFFSET 0x12 352#define PART4OFFSET 0x14 353#define PART5OFFSET 0x16 354#define CAPTUREOFFSET 0x00 355#define VIDEOOFFSET 0x02 356#define COLREGOFFSET 0x48 357#define PELMASKOFFSET 0x46 358 359#define SISAR pSiS->RelIO + AROFFSET 360#define SISARR pSiS->RelIO + ARROFFSET 361#define SISGR pSiS->RelIO + GROFFSET 362#define SISSR pSiS->RelIO + SROFFSET 363#define SISCR pSiS->RelIO + CROFFSET 364#define SISMISCR pSiS->RelIO + MISCROFFSET 365#define SISMISCW pSiS->RelIO + MISCWOFFSET 366#define SISINPSTAT pSiS->RelIO + INPUTSTATOFFSET 367#define SISPART1 pSiS->RelIO + PART1OFFSET 368#define SISPART2 pSiS->RelIO + PART2OFFSET 369#define SISPART3 pSiS->RelIO + PART3OFFSET 370#define SISPART4 pSiS->RelIO + PART4OFFSET 371#define SISPART5 pSiS->RelIO + PART5OFFSET 372#define SISCAP pSiS->RelIO + CAPTUREOFFSET 373#define SISVID pSiS->RelIO + VIDEOOFFSET 374#define SISCOLIDXR pSiS->RelIO + COLREGOFFSET - 1 375#define SISCOLIDX pSiS->RelIO + COLREGOFFSET 376#define SISCOLDATA pSiS->RelIO + COLREGOFFSET + 1 377#define SISCOL2IDX SISPART5 378#define SISCOL2DATA SISPART5 + 1 379#define SISPEL pSiS->RelIO + PELMASKOFFSET 380 381/* Video registers (300/315/330/340 series only) --------------- */ 382#define Index_VI_Passwd 0x00 383 384/* Video overlay horizontal start/end, unit=screen pixels */ 385#define Index_VI_Win_Hor_Disp_Start_Low 0x01 386#define Index_VI_Win_Hor_Disp_End_Low 0x02 387#define Index_VI_Win_Hor_Over 0x03 /* Overflow */ 388 389/* Video overlay vertical start/end, unit=screen pixels */ 390#define Index_VI_Win_Ver_Disp_Start_Low 0x04 391#define Index_VI_Win_Ver_Disp_End_Low 0x05 392#define Index_VI_Win_Ver_Over 0x06 /* Overflow */ 393 394/* Y Plane (4:2:0) or YUV (4:2:2) buffer start address, unit=word */ 395#define Index_VI_Disp_Y_Buf_Start_Low 0x07 396#define Index_VI_Disp_Y_Buf_Start_Middle 0x08 397#define Index_VI_Disp_Y_Buf_Start_High 0x09 398 399/* U Plane (4:2:0) buffer start address, unit=word */ 400#define Index_VI_U_Buf_Start_Low 0x0A 401#define Index_VI_U_Buf_Start_Middle 0x0B 402#define Index_VI_U_Buf_Start_High 0x0C 403 404/* V Plane (4:2:0) buffer start address, unit=word */ 405#define Index_VI_V_Buf_Start_Low 0x0D 406#define Index_VI_V_Buf_Start_Middle 0x0E 407#define Index_VI_V_Buf_Start_High 0x0F 408 409/* Pitch for Y, UV Planes, unit=word */ 410#define Index_VI_Disp_Y_Buf_Pitch_Low 0x10 411#define Index_VI_Disp_UV_Buf_Pitch_Low 0x11 412#define Index_VI_Disp_Y_UV_Buf_Pitch_Middle 0x12 413 414/* What is this ? */ 415#define Index_VI_Disp_Y_Buf_Preset_Low 0x13 416#define Index_VI_Disp_Y_Buf_Preset_Middle 0x14 417 418#define Index_VI_UV_Buf_Preset_Low 0x15 419#define Index_VI_UV_Buf_Preset_Middle 0x16 420#define Index_VI_Disp_Y_UV_Buf_Preset_High 0x17 421 422/* Scaling control registers */ 423#define Index_VI_Hor_Post_Up_Scale_Low 0x18 424#define Index_VI_Hor_Post_Up_Scale_High 0x19 425#define Index_VI_Ver_Up_Scale_Low 0x1A 426#define Index_VI_Ver_Up_Scale_High 0x1B 427#define Index_VI_Scale_Control 0x1C 428 429/* Playback line buffer control */ 430#define Index_VI_Play_Threshold_Low 0x1D 431#define Index_VI_Play_Threshold_High 0x1E 432#define Index_VI_Line_Buffer_Size 0x1F 433 434/* Destination color key */ 435#define Index_VI_Overlay_ColorKey_Red_Min 0x20 436#define Index_VI_Overlay_ColorKey_Green_Min 0x21 437#define Index_VI_Overlay_ColorKey_Blue_Min 0x22 438#define Index_VI_Overlay_ColorKey_Red_Max 0x23 439#define Index_VI_Overlay_ColorKey_Green_Max 0x24 440#define Index_VI_Overlay_ColorKey_Blue_Max 0x25 441 442/* Source color key, YUV color space */ 443#define Index_VI_Overlay_ChromaKey_Red_Y_Min 0x26 444#define Index_VI_Overlay_ChromaKey_Green_U_Min 0x27 445#define Index_VI_Overlay_ChromaKey_Blue_V_Min 0x28 446#define Index_VI_Overlay_ChromaKey_Red_Y_Max 0x29 447#define Index_VI_Overlay_ChromaKey_Green_U_Max 0x2A 448#define Index_VI_Overlay_ChromaKey_Blue_V_Max 0x2B 449 450/* Contrast enhancement and brightness control */ 451#define Index_VI_Contrast_Factor 0x2C /* obviously unused/undefined */ 452#define Index_VI_Brightness 0x2D 453#define Index_VI_Contrast_Enh_Ctrl 0x2E 454 455#define Index_VI_Key_Overlay_OP 0x2F 456 457#define Index_VI_Control_Misc0 0x30 458#define Index_VI_Control_Misc1 0x31 459#define Index_VI_Control_Misc2 0x32 460 461/* Subpicture registers */ 462#define Index_VI_SubPict_Buf_Start_Low 0x33 463#define Index_VI_SubPict_Buf_Start_Middle 0x34 464#define Index_VI_SubPict_Buf_Start_High 0x35 465 466/* What is this ? */ 467#define Index_VI_SubPict_Buf_Preset_Low 0x36 468#define Index_VI_SubPict_Buf_Preset_Middle 0x37 469 470/* Subpicture pitch, unit=16 bytes */ 471#define Index_VI_SubPict_Buf_Pitch 0x38 472 473/* Subpicture scaling control */ 474#define Index_VI_SubPict_Hor_Scale_Low 0x39 475#define Index_VI_SubPict_Hor_Scale_High 0x3A 476#define Index_VI_SubPict_Vert_Scale_Low 0x3B 477#define Index_VI_SubPict_Vert_Scale_High 0x3C 478 479#define Index_VI_SubPict_Scale_Control 0x3D 480/* (0x40 = enable/disable subpicture) */ 481 482/* Subpicture line buffer control */ 483#define Index_VI_SubPict_Threshold 0x3E 484 485/* What is this? */ 486#define Index_VI_FIFO_Max 0x3F 487 488/* Subpicture palette; 16 colors, total 32 bytes address space */ 489#define Index_VI_SubPict_Pal_Base_Low 0x40 490#define Index_VI_SubPict_Pal_Base_High 0x41 491 492/* I wish I knew how to use these ... */ 493#define Index_MPEG_Read_Ctrl0 0x60 /* MPEG auto flip */ 494#define Index_MPEG_Read_Ctrl1 0x61 /* MPEG auto flip */ 495#define Index_MPEG_Read_Ctrl2 0x62 /* MPEG auto flip */ 496#define Index_MPEG_Read_Ctrl3 0x63 /* MPEG auto flip */ 497 498/* MPEG AutoFlip scale */ 499#define Index_MPEG_Ver_Up_Scale_Low 0x64 500#define Index_MPEG_Ver_Up_Scale_High 0x65 501 502#define Index_MPEG_Y_Buf_Preset_Low 0x66 503#define Index_MPEG_Y_Buf_Preset_Middle 0x67 504#define Index_MPEG_UV_Buf_Preset_Low 0x68 505#define Index_MPEG_UV_Buf_Preset_Middle 0x69 506#define Index_MPEG_Y_UV_Buf_Preset_High 0x6A 507 508/* The following registers only exist on the 315/330/340 series */ 509 510/* Bit 16:24 of Y_U_V buf start address */ 511#define Index_VI_Y_Buf_Start_Over 0x6B 512#define Index_VI_U_Buf_Start_Over 0x6C 513#define Index_VI_V_Buf_Start_Over 0x6D 514 515#define Index_VI_Disp_Y_Buf_Pitch_High 0x6E 516#define Index_VI_Disp_UV_Buf_Pitch_High 0x6F 517 518/* Hue and saturation */ 519#define Index_VI_Hue 0x70 520#define Index_VI_Saturation 0x71 521 522#define Index_VI_SubPict_Start_Over 0x72 523#define Index_VI_SubPict_Buf_Pitch_High 0x73 524 525#define Index_VI_Control_Misc3 0x74 526 527/* 340 and later: */ 528/* DDA registers 0x75 - 0xb4 */ 529/* threshold high 0xb5, 0xb6 */ 530#define Index_VI_Line_Buffer_Size_High 0xb7 531 532 533/* Bits in Scale control (0x1c) */ 534#define VI_Scale_Ctrl_Horiz_DDA 0x20 535#define VI_Scale_Ctrl_Vert_DDA 0x40 536 537/* Bits (and helpers) for Index_VI_Control_Misc0 */ 538#define VI_Misc0_Enable_Capture_AutoFlip 0x01 /* 340 only? */ 539#define VI_Misc0_Enable_Overlay 0x02 540#define VI_Misc0_420_Plane_Enable 0x04 /* Select Plane or Packed mode */ 541#define VI_Misc0_422_Enable 0x20 /* Select 422 or 411 mode */ 542#define VI_Misc0_Fmt_YVU420P 0x0C /* YUV420 Planar (I420, YV12) */ 543#define VI_Misc0_Fmt_YUYV 0x28 /* YUYV Packed (=YUY2) */ 544#define VI_Misc0_Fmt_UYVY 0x08 /* (UYVY) */ 545#define VI_Misc0_Fmt_YVYU 0x38 /* (YVYU) (315 series only?) */ 546#define VI_Misc0_Fmt_NV21 0x5c /* (330 series only?) */ 547#define VI_Misc0_Fmt_NV12 0x4c /* (330 series only?) */ 548#define VI_Misc0_ChromaKeyRGBYUV 0x40 /* 300 series only: 0 = RGB, 1 = YUV */ 549 550/* Bits for Index_VI_Control_Misc1 */ 551#define VI_Misc1_DisableGraphicsAtOverlay 0x01 /* Disables graphics display in overlay area */ 552#define VI_Misc1_BOB_Enable 0x02 /* Enable BOB de-interlacer */ 553#define VI_Misc1_Line_Merge 0x04 554#define VI_Misc1_Field_Mode 0x08 /* ? Assume even/odd fields interleaved in memory ? */ 555#define VI_Misc1_Non_Interleave 0x10 /* ? Odd and Even fields are not interleaved ? */ 556#define VI_Misc1_Buf_Addr_Lock 0x20 /* 315 series only? */ 557/* #define VI_Misc1_? 0x40 */ 558/* #define VI_Misc1_? 0x80 */ 559 560/* Bits for Index_VI_Control_Misc2 */ 561#define VI_Misc2_Select_Video2 0x01 562#define VI_Misc2_Video2_On_Top 0x02 563#define VI_Misc2_DisableGraphics 0x04 /* Disable graphics display entirely (<= 650 only, not >= M650, 651) */ 564#define VI_Misc2_Vertical_Interpol 0x08 565#define VI_Misc2_Dual_Line_Merge 0x10 /* dual-overlay chips only; "dual video windows relative line buffer merge" */ 566#define VI_Misc2_All_Line_Merge 0x20 /* > 315 only */ 567#define VI_Misc2_Auto_Flip_Enable 0x40 568#define VI_Misc2_Video_Reg_Write_Enable 0x80 /* 315 series only? */ 569 570/* Bits for Index_VI_Control_Misc3 */ 571#define VI_Misc3_Submit_Video_1 0x01 /* AKA "address ready" */ 572#define VI_Misc3_Submit_Video_2 0x02 /* AKA "address ready" */ 573#define VI_Misc3_Submit_SubPict 0x04 /* AKA "address ready" */ 574 575/* Values for Index_VI_Key_Overlay_OP (0x2F) */ 576#define VI_ROP_Never 0x00 577#define VI_ROP_DestKey 0x03 578#define VI_ROP_ChromaKey 0x05 579#define VI_ROP_NotChromaKey 0x0A 580#define VI_ROP_Always 0x0F 581 582 583/* Video registers (559x, 6326 and 530/620) --------------- */ 584#define Index_VI6326_Passwd 0x80 585 586/* Video overlay horizontal start/end, unit=screen pixels */ 587#define Index_VI6326_Win_Hor_Disp_Start_Low 0x81 588#define Index_VI6326_Win_Hor_Disp_End_Low 0x82 589#define Index_VI6326_Win_Hor_Over 0x83 /* Overflow */ 590 591/* Video overlay vertical start/end, unit=screen pixels */ 592#define Index_VI6326_Win_Ver_Disp_Start_Low 0x84 593#define Index_VI6326_Win_Ver_Disp_End_Low 0x85 594#define Index_VI6326_Win_Ver_Over 0x86 /* Overflow */ 595 596/* Y Plane (4:2:0) or YUV (4:2:2) buffer start address, unit=dword */ 597#define Index_VI6326_Disp_Y_Buf_Start_Low 0x8A 598#define Index_VI6326_Disp_Y_Buf_Start_Middle 0x8B 599#define Index_VI6326_Disp_Capt_Y_Buf_Start_High 0x89 /* 6326: 7:4 display, 3:0 capture */ 600 /* 530/620: 7:3 display. 2:0 reserved */ 601/* End address of Y plane (in 16k unit) - 6326 ONLY */ 602#define Index_VI6326_Disp_Y_End 0x8D 603 604/* U Plane (4:2:0) buffer start address, unit=dword */ 605#define Index_VI6326_U_Buf_Start_Low 0xB7 606#define Index_VI6326_U_Buf_Start_Middle 0xB8 607 608/* V Plane (4:2:0) buffer start address, unit=dword */ 609#define Index_VI6326_V_Buf_Start_Low 0xBA 610#define Index_VI6326_V_Buf_Start_Middle 0xBB 611 612/* U/V plane start address overflow bits 19:16 */ 613#define Index_VI6326_UV_Buf_Start_High 0xB9 614 615/* Pitch for Y, UV Planes, unit=dword(6326 & 530/620) */ 616#define Index_VI6326_Disp_Y_Buf_Pitch_Low 0x8C /* 7:0 */ 617#define Index_VI6326_Disp_Y_Buf_Pitch_High 0x8E /* 11:8 (3:0 here) */ 618 619#define Index_VI6326_Disp_UV_Buf_Pitch_Low 0xBC /* 7:0 */ 620#define Index_VI6326_Disp_UV_Buf_Pitch_High 0xBD /* 11:8 (3:0 here) */ 621 622/* Scaling control registers */ 623#define Index_VI6326_Hor_Scale 0x92 624#define Index_VI6326_Hor_Scale_Integer 0x94 625#define Index_VI6326_Ver_Scale 0x93 626 627/* Playback line buffer control */ 628#define Index_VI6326_Play_Threshold_Low 0x9E 629#define Index_VI6326_Play_Threshold_High 0x9F 630#define Index_VI6326_Line_Buffer_Size 0xA0 /* 530 & 6326: quad-word */ 631 632/* Destination color key */ 633#define Index_VI6326_Overlay_ColorKey_Red_Min 0x97 634#define Index_VI6326_Overlay_ColorKey_Green_Min 0x96 635#define Index_VI6326_Overlay_ColorKey_Blue_Min 0x95 636#define Index_VI6326_Overlay_ColorKey_Red_Max 0xA3 637#define Index_VI6326_Overlay_ColorKey_Green_Max 0xA2 638#define Index_VI6326_Overlay_ColorKey_Blue_Max 0xA1 639 640/* Source color key */ 641#define Index_VI6326_Overlay_ChromaKey_Red_Y_Min 0x9C 642#define Index_VI6326_Overlay_ChromaKey_Green_U_Min 0x9B 643#define Index_VI6326_Overlay_ChromaKey_Blue_V_Min 0x9A 644#define Index_VI6326_Overlay_ChromaKey_Red_Y_Max 0xA6 645#define Index_VI6326_Overlay_ChromaKey_Green_U_Max 0xA5 646#define Index_VI6326_Overlay_ChromaKey_Blue_V_Max 0xA4 647 648/* Contrast enhancement and brightness control */ 649#define Index_VI6326_Contrast_Factor 0xB3 650#define Index_VI6326_Brightness 0xB4 651#define Index_VI6326_Contrast_Enh_Ctrl 0xB5 652 653/* Alpha */ 654#define Index_VI6326_AlphaGraph 0xA7 655#define Index_VI6326_AlphaVideo 0xA8 656 657#define Index_VI6326_Key_Overlay_OP 0xA9 658 659#define Index_VI6326_Control_Misc0 0x98 660#define Index_VI6326_Control_Misc1 0x99 /* (Datasheet: 6326 ONLY - not correct?) */ 661#define Index_VI6326_Control_Misc3 0x9D 662#define Index_VI6326_Control_Misc4 0xB6 663#define Index_VI6326_VideoFormatSelect Index_VI6326_Ver_Scale 664#define Index_VI6326_Control_Misc5 0xBE /* (Datasheet: 530/620 ONLY - not correct) */ 665#define Index_VI6326_Control_Misc6 0xB2 /* 5597 and 6326 only! */ 666 667/* What is this? not a register, obviously */ 668#define Index_VI6326_FIFO_Max 0x3F 669 670/* Bits (and helpers) for Index_VI6326_Control_Misc0 */ 671#define VI6326_Misc0_EnableCapture 0x01 /* 1 = on, 0 = off (6326 only) */ 672#define VI6326_Misc0_EnableOverlay 0x02 /* 1 = on, 0 = off */ 673#define VI6326_Misc0_VideoOnly 0x10 /* 1 = video only, 0 = gfx + video */ 674#define VI6326_Misc0_CaptureInterlace 0x20 /* 1 = capture data is interlace, 0 = not (6326 only) */ 675#define VI6326_Misc0_VideoFormat 0x40 /* 1 = YUV, 0 = RGB */ 676#define VI6326_Misc0_FieldPolarity 0x80 /* 1 = *Odd / Even, 0 = Odd / *Even (6326 only) */ 677 678/* Bits for Index_VI6326_Control_Misc1 (ALL 6326 ONLY) */ 679#define VI6326_Misc1_EnableYUVCapture 0x01 /* 0 = RGB, 1 = YUV */ 680#define VI6326_Misc1_EnableCaptureDithering 0x02 /* 0 = disable, 1 = enable */ 681#define VI6326_Misc1_CaptureFormat555 0x04 /* 1 = 555, 0 = 565 */ 682#define VI6326_Misc1_FilterModeMask 0x38 683#define VI6326_Misc1_FilterMode0 0x00 /* 1 */ 684#define VI6326_Misc1_FilterMode1 0x08 /* 1/8(1+3z^-1+3z^-2+z^-3)*/ 685#define VI6326_Misc1_FilterMode2 0x10 /* 1/4(1+2z^-1+z^-2) */ 686#define VI6326_Misc1_FilterMode3 0x18 /* 1/2(1+z^-1) */ 687#define VI6326_Misc1_FilterMode4 0x20 /* 1/8(1+2z^-1+2z^-2+2z^-3+z^-4) */ 688#define VI6326_Misc1_EnableVBSyncIRQ 0x40 /* 1 = Enable IRQ on vertical blank */ 689#define VI6326_Misc1_ClearVBSyncIRQ 0x80 /* Clear pending irq */ 690 691/* Bits for Index_VI6326_Control_Misc3 */ 692#define VI6326_Misc3_UVCaptureFormat 0x01 /* 1 = 2's complement, 0 = CCIR 601 (6326 only) */ 693#define VI6326_Misc3_UVOverlayFormat 0x02 /* 1 = 2's complement, 0 = CCIR 601 */ 694#define VI6326_Misc3_ChromaKeyFormat 0x04 /* 1 = YUV, 0 = RGB */ 695#define VI6326_Misc3_VMIAccess 0x08 /* 1 = enable, 0 = disable (6326 only) */ 696#define VI6326_Misc3_VMIEnable 0x10 /* 1 = enable, 0 = disable (6326 only) */ 697#define VI6326_Misc3_VMIIRQ 0x20 /* 1 = enable, 0 = disable (6326 only) */ 698#define VI6326_Misc3_BT819A 0x40 /* 1 = enable, 0 = disable (6326 only) */ 699#define VI6326_Misc3_SystemMemFB 0x80 /* 1 = enable, 0 = disable (6326 only) */ 700 701/* Bits for Index_VI6326_Control_Misc4 */ 702#define VI6326_Misc4_CPUVideoFormatMask 0x03 703#define VI6326_Misc4_CPUVideoFormatRGB555 0x00 704#define VI6326_Misc4_CPUVideoFormatYUV422 0x01 705#define VI6326_Misc4_CPUVideoFormatRGB565 0x02 706#define VI6326_Misc4_EnableYUV420 0x04 /* 1 = enable, 0 = disable */ 707/* #define WHATISTHIS 0x40 */ 708 709/* Bits for Index_VI6326_Control_Misc5 (all 530/620 only) */ 710#define VI6326_Misc5_LineBufferMerge 0x10 /* 0 = disable, 1=enable */ 711#define VI6326_Misc5_VPlaneBit20 0x04 712#define VI6326_Misc5_UPlaneBit20 0x02 713 714/* Bits for Index_VI6326_Control_Misc6 (5597 and 6326 only) */ 715#define VI6326_Misc6_Decimation 0x80 /* 0=disable 1=enable video decimation */ 716 717/* Video format selection */ 718#define VI_6326_VideoUYVY422 0x00 719#define VI_6326_VideoVYUY422 0x40 720#define VI_6326_VideoYUYV422 0x80 721#define VI_6326_VideoYVYU422 0xC0 722#define VI_6326_VideoRGB555 0x00 723#define VI_6326_VideoRGB565 0x40 724 725/* Values for Index_VI6326_Key_Overlay_OP */ 726#define VI6326_ROP_Never 0x00 727#define VI6326_ROP_DestKey 0x03 728#define VI6326_ROP_Always 0x0F 729 730/* --- end of 6326 video registers ---------------------------------- */ 731 732/* TV register base (6326 only) */ 733#define Index_TV6326_TVOutIndex 0xE0 734#define Index_TV6326_TVOutData 0xE1 735 736/* mmio registers for video */ 737#define REG_PRIM_CRT_COUNTER 0x8514 738 739/* MPEG MMIO registers (630 and later) ----------------------------------------- */ 740 741/* Not public (yet?) */ 742 743 744#endif /* SIS_REGS_H_ */ 745 746 747