tdfx_sli.c revision 02be438a
1/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/tdfx/tdfx_sli.c,v 1.6 2000/12/15 15:19:35 dawes Exp $ */ 2 3#ifdef HAVE_CONFIG_H 4#include "config.h" 5#endif 6 7#include "xf86.h" 8#include "xf86_OSproc.h" 9#include "xf86Pci.h" 10#include "tdfx.h" 11 12#define AACLKOUTDEL 0x2 13#define CFGSWAPALGORITHM 0x1 14 15/* #define RD_ABORT_ERROR */ 16#define H3VDD 17 18Bool TDFXDisableSLI(TDFXPtr pTDFX) 19{ 20 int i; 21 int v; 22 23 for (i=0; i<pTDFX->numChips; i++) { 24 v=pciReadLong(pTDFX->PciTag[i], CFG_INIT_ENABLE); 25 pciWriteLong(pTDFX->PciTag[i], CFG_INIT_ENABLE, 26 v&~(CFG_SNOOP_MEMBASE0 | CFG_SNOOP_EN | CFG_SNOOP_MEMBASE0_EN | 27 CFG_SNOOP_MEMBASE1_EN | CFG_SNOOP_SLAVE | 28 CFG_SNOOP_FBIINIT_WR_EN | CFG_SWAP_ALGORITHM | 29 CFG_SWAP_QUICK)); 30 v=pciReadLong(pTDFX->PciTag[i], CFG_SLI_LFB_CTRL); 31 pciWriteLong(pTDFX->PciTag[i], CFG_SLI_LFB_CTRL, 32 v&~(CFG_SLI_LFB_CPU_WR_EN | CFG_SLI_LFB_DPTCH_WR_EN | 33 CFG_SLI_RD_EN)); 34#ifdef H3VDD 35 pTDFX->writeChipLong(pTDFX, i, SST_3D_SLICTRL, 0); 36 pTDFX->writeChipLong(pTDFX, i, SST_3D_AACTRL, 0); 37#endif 38 v=pciReadLong(pTDFX->PciTag[i], CFG_AA_LFB_CTRL); 39 pciWriteLong(pTDFX->PciTag[i], CFG_AA_LFB_CTRL, 40 v&~(CFG_AA_LFB_CPU_WR_EN | CFG_AA_LFB_DPTCH_WR_EN | 41 CFG_AA_LFB_RD_EN)); 42 v=pciReadLong(pTDFX->PciTag[i], CFG_SLI_AA_MISC); 43 pciWriteLong(pTDFX->PciTag[i], CFG_SLI_AA_MISC, 44 (v&~CFG_VGA_VSYNC_OFFSET) | 45 (0 << CFG_VGA_VSYNC_OFFSET_PIXELS_SHIFT) | 46 (0 << CFG_VGA_VSYNC_OFFSET_CHARS_SHIFT) | 47 (0 << CFG_VGA_VSYNC_OFFSET_HXTRA_SHIFT)); 48 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 0); 49 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 0); 50 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 0); 51 52 if (pTDFX->numChips>1) { 53 v=pTDFX->readChipLong(pTDFX, i, PCIINIT0); 54 pTDFX->writeChipLong(pTDFX, i, PCIINIT0, 55 (v&~(SST_PCI_DISABLE_IO|SST_PCI_DISABLE_MEM| 56 SST_PCI_RETRY_INTERVAL)) | 57 (0<<SST_PCI_RETRY_INTERVAL_SHIFT) | 58 SST_PCI_FORCE_FB_HIGH); 59 } else { 60 v=pTDFX->readChipLong(pTDFX, i, PCIINIT0); 61 pTDFX->writeChipLong(pTDFX, i, PCIINIT0, 62 (v&~(SST_PCI_DISABLE_IO|SST_PCI_DISABLE_MEM| 63 SST_PCI_RETRY_INTERVAL)) | 64 (0<<SST_PCI_RETRY_INTERVAL_SHIFT)); 65 } 66 67#if 0 68 if (i>0) { 69 pTDFX->writeChipLong(pTDFX, i, DACMODE, 70 SST_DAC_DPMS_ON_VSYNC | SST_DAC_DPMS_ON_HSYNC); 71 v=pTDFX->readChipLong(pTDFX, i, VIDPROCCFG); 72 pTDFX->writeChipLong(pTDFX, i, VIDPROCCFG, v&~SST_VIDEO_PROCESSOR_EN); 73 } 74#endif 75 } 76 return TRUE; 77} 78 79Bool TDFXSetupSLI(ScrnInfoPtr pScrn, Bool sliEnable, int aaSamples) 80{ 81 TDFXPtr pTDFX; 82 int i, sliLines, sliLinesLog2, nChipsLog2, v; 83 int sli_renderMask, sli_compareMask, sli_scanMask; 84 int sliAnalog, dwFormat; 85 86 pTDFX=TDFXPTR(pScrn); 87 if (pScrn->depth == 24 || pScrn->depth==32) { 88 if ((aaSamples == 4) && (pTDFX->numChips>1)) { 89 pTDFX->pixelFormat=GR_PIXFMT_AA_4_ARGB_8888; 90 } else if (aaSamples >= 2) { 91 pTDFX->pixelFormat=GR_PIXFMT_AA_2_ARGB_8888; 92 } else { 93 pTDFX->pixelFormat=GR_PIXFMT_ARGB_8888; 94 } 95 } else if (pScrn->depth == 16) { 96 if ((aaSamples == 4) && (pTDFX->numChips>1)) { 97 pTDFX->pixelFormat=GR_PIXFMT_AA_4_RGB_565; 98 } else if (aaSamples >= 2) { 99 pTDFX->pixelFormat=GR_PIXFMT_AA_2_RGB_565; 100 } else { 101 pTDFX->pixelFormat=GR_PIXFMT_RGB_565; 102 } 103 } else if (pScrn->depth == 8) { 104 pTDFX->pixelFormat=GR_PIXFMT_I_8; 105 } 106 if (!sliEnable && !aaSamples) { /* Turn off */ 107 return TDFXDisableSLI(pTDFX); 108 } 109 110 if (pScrn->virtualY>768) sliLinesLog2=5; 111 else sliLinesLog2=4; 112 sliLines=1<<sliLinesLog2; 113 if (pScrn->virtualY*pScrn->virtualX>1600*1024) sliAnalog=1; 114 else sliAnalog=0; 115 /* XXX We need to avoid SLI in double scan modes somehow */ 116 117 switch (pTDFX->numChips) { 118 case 1: 119 nChipsLog2=0; 120 break; 121 case 2: 122 nChipsLog2=1; 123 break; 124 case 4: 125 nChipsLog2=2; 126 break; 127 default: 128 return FALSE; 129 /* XXX Huh? Unsupported configuration */ 130 } 131 132 for (i=0; i<pTDFX->numChips; i++) { 133 /* Do we want to set these differently for a VIA board? */ 134 v=pTDFX->readChipLong(pTDFX, i, PCIINIT0); 135 v=(v&~(SST_PCI_RETRY_INTERVAL|SST_PCI_FORCE_FB_HIGH)) | 136 SST_PCI_READ_WS | SST_PCI_WRITE_WS | 137 SST_PCI_DISABLE_IO | SST_PCI_DISABLE_MEM | 138 (5<<SST_PCI_RETRY_INTERVAL_SHIFT); 139 pTDFX->writeChipLong(pTDFX, i, PCIINIT0, 140 (v&~(SST_PCI_RETRY_INTERVAL|SST_PCI_FORCE_FB_HIGH)) | 141 SST_PCI_READ_WS | SST_PCI_WRITE_WS | 142 SST_PCI_DISABLE_IO | SST_PCI_DISABLE_MEM | 143 (5<<SST_PCI_RETRY_INTERVAL_SHIFT)); 144 v=pTDFX->readChipLong(pTDFX, i, TMUGBEINIT); 145 pTDFX->writeChipLong(pTDFX, i, TMUGBEINIT, 146 (v&~(SST_AA_CLK_DELAY | SST_AA_CLK_INVERT)) | 147 (AACLKOUTDEL<<SST_AA_CLK_DELAY_SHIFT) | 148 SST_AA_CLK_INVERT); 149 150 if (pTDFX->numChips>1) { 151 v=pciReadLong(pTDFX->PciTag[i], CFG_INIT_ENABLE); 152 pciWriteLong(pTDFX->PciTag[i], CFG_INIT_ENABLE, v | 153 (CFGSWAPALGORITHM << CFG_SWAPBUFFER_ALGORITHM_SHIFT) | 154 CFG_SWAP_ALGORITHM | ((!i)? CFG_SWAP_MASTER : 0)); 155 if (!i) { 156 v=pciReadLong(pTDFX->PciTag[i], CFG_INIT_ENABLE); 157 pciWriteLong(pTDFX->PciTag[i], CFG_INIT_ENABLE, 158 v | CFG_SNOOP_EN); 159 v=pciReadLong(pTDFX->PciTag[i], CFG_PCI_DECODE); 160 } else { 161 v=pciReadLong(pTDFX->PciTag[i], CFG_INIT_ENABLE); 162 v=(v & ~CFG_SNOOP_MEMBASE0) | CFG_SNOOP_EN | 163 CFG_SNOOP_MEMBASE0_EN | CFG_SNOOP_MEMBASE1_EN | 164 CFG_SNOOP_SLAVE | CFG_SNOOP_FBIINIT_WR_EN | 165 (((pTDFX->MMIOAddr[0]>>22)&0x3ff)<<CFG_SNOOP_MEMBASE0_SHIFT) | 166 ((pTDFX->numChips>2)? CFG_SWAP_QUICK : 0); 167 pciWriteLong(pTDFX->PciTag[i], CFG_INIT_ENABLE, v); 168 v=pciReadLong(pTDFX->PciTag[i], CFG_PCI_DECODE); 169 v=(v & ~CFG_SNOOP_MEMBASE1) | 170 ((pTDFX->LinearAddr[0]>>22)&0x3ff)<<CFG_SNOOP_MEMBASE1_SHIFT; 171 pciWriteLong(pTDFX->PciTag[i], CFG_PCI_DECODE, v); 172 } 173 } 174 175 if (sliEnable && aaSamples<4) { 176 /* SLI is on and we're using less than 4 AA samples */ 177 sli_renderMask = (pTDFX->numChips-1) << sliLinesLog2; 178 sli_compareMask = i << sliLinesLog2; 179 sli_scanMask = sliLines - 1; 180 v = (sli_renderMask << CFG_SLI_LFB_RENDERMASK_SHIFT) | 181 (sli_compareMask << CFG_SLI_LFB_COMPAREMASK_SHIFT) | 182 (sli_scanMask << CFG_SLI_LFB_SCANMASK_SHIFT) | 183 (nChipsLog2 << CFG_SLI_LFB_NUMCHIPS_LOG2_SHIFT) | 184 CFG_SLI_LFB_CPU_WR_EN | CFG_SLI_LFB_DPTCH_WR_EN; 185#ifndef RD_ABORT_ERROR 186 v|=CFG_SLI_RD_EN; 187#endif 188 pciWriteLong(pTDFX->PciTag[i], CFG_SLI_LFB_CTRL, v); 189 190#ifdef H3VDD 191 pTDFX->writeChipLong(pTDFX, i, SST_3D_SLICTRL, 192 (sli_renderMask << SLICTL_3D_RENDERMASK_SHIFT) | 193 (sli_compareMask << SLICTL_3D_COMPAREMASK_SHIFT) | 194 (sli_scanMask << SLICTL_3D_SCANMASK_SHIFT) | 195 (nChipsLog2 << SLICTL_3D_NUMCHIPS_LOG2_SHIFT) | 196 SLICTL_3D_EN); 197#endif 198 } else if (!sliEnable && aaSamples) { 199 /* SLI is off and AA is on */ 200 sli_renderMask = 0; 201 sli_compareMask = 0; 202 sli_scanMask = 0; 203 pciWriteLong(pTDFX->PciTag[i], CFG_SLI_LFB_CTRL, 204 (sli_renderMask << CFG_SLI_LFB_RENDERMASK_SHIFT) | 205 (sli_compareMask << CFG_SLI_LFB_COMPAREMASK_SHIFT) | 206 (sli_scanMask << CFG_SLI_LFB_SCANMASK_SHIFT) | 207 (0x0 << CFG_SLI_LFB_NUMCHIPS_LOG2_SHIFT)); 208#ifdef H3VDD 209 pTDFX->writeChipLong(pTDFX, i, SST_3D_SLICTRL, 210 (sli_renderMask << SLICTL_3D_RENDERMASK_SHIFT) | 211 (sli_compareMask << SLICTL_3D_COMPAREMASK_SHIFT) | 212 (sli_scanMask << SLICTL_3D_SCANMASK_SHIFT) | 213 (0 << SLICTL_3D_NUMCHIPS_LOG2_SHIFT)); 214#endif 215 } else { 216 /* SLI is on && aaSamples=4 */ 217 sli_renderMask = ((pTDFX->numChips>>1)-1) << sliLinesLog2; 218 sli_compareMask = (i>>1) << sliLinesLog2; 219 sli_scanMask = sliLines - 1; 220 v = (sli_renderMask << CFG_SLI_LFB_RENDERMASK_SHIFT) | 221 (sli_compareMask << CFG_SLI_LFB_COMPAREMASK_SHIFT) | 222 (sli_scanMask << CFG_SLI_LFB_SCANMASK_SHIFT) | 223 ((nChipsLog2-1) << CFG_SLI_LFB_NUMCHIPS_LOG2_SHIFT) | 224 CFG_SLI_LFB_CPU_WR_EN | CFG_SLI_LFB_DPTCH_WR_EN; 225#ifndef RD_ABORT_ERROR 226 v|=CFG_SLI_RD_EN; 227#endif 228 pciWriteLong(pTDFX->PciTag[i], CFG_SLI_LFB_CTRL, v); 229#ifdef H3VDD 230 pTDFX->writeChipLong(pTDFX, i, SST_3D_SLICTRL, 231 (sli_renderMask << SLICTL_3D_RENDERMASK_SHIFT) | 232 (sli_compareMask << SLICTL_3D_COMPAREMASK_SHIFT) | 233 (sli_scanMask << SLICTL_3D_SCANMASK_SHIFT) | 234 ((nChipsLog2-1) << SLICTL_3D_NUMCHIPS_LOG2_SHIFT) | 235 SLICTL_3D_EN); 236#endif 237 } 238 239 TDFXSetLFBConfig(pTDFX); 240 if (pTDFX->cpp==2) dwFormat = CFG_AA_LFB_RD_FORMAT_16BPP; 241 else dwFormat = CFG_AA_LFB_RD_FORMAT_32BPP; 242 if (pTDFX->numChips==2 && !sliEnable && aaSamples==2) 243 dwFormat|=CFG_AA_LFB_RD_DIVIDE_BY_4; 244 /* Thess are wrong, because we don't know where the secondary buffers 245 are located */ 246 pTDFX->writeChipLong(pTDFX, i, CFG_AA_LFB_CTRL, 247 (pScrn->videoRam<<10 /* 2nd buf */ << CFG_AA_BASEADDR_SHIFT) | 248 CFG_AA_LFB_CPU_WR_EN | CFG_AA_LFB_DPTCH_WR_EN | 249 CFG_AA_LFB_RD_EN | dwFormat | 250 ((aaSamples==4)?CFG_AA_LFB_RD_DIVIDE_BY_4:0)); 251 pTDFX->writeChipLong(pTDFX, i, CFG_AA_ZBUFF_APERTURE, 252 ((pTDFX->depthOffset>>12)<<CFG_AA_DEPTH_BUFFER_BEG_SHIFT) | 253 ((pScrn->videoRam>>2)<<CFG_AA_DEPTH_BUFFER_END_SHIFT)); 254 255 if (pTDFX->numChips>1 && i && (aaSamples || sliEnable)) { 256 int vsyncOffsetPixels, vsyncOffsetChars, vsyncOffsetHXtra; 257 258 if (aaSamples || (pTDFX->numChips==4 && sliEnable && aaSamples==4 && 259 sliAnalog && i==3)) { 260 vsyncOffsetPixels=7; 261 vsyncOffsetChars=4; 262 vsyncOffsetHXtra=0; 263 } else { 264 vsyncOffsetPixels=7; 265 vsyncOffsetChars=5; 266 vsyncOffsetHXtra=0; 267 } 268 v=pciReadLong(pTDFX->PciTag[i], CFG_SLI_AA_MISC); 269 pciWriteLong(pTDFX->PciTag[i], CFG_SLI_AA_MISC, 270 (v&~CFG_VGA_VSYNC_OFFSET) | 271 (vsyncOffsetPixels << CFG_VGA_VSYNC_OFFSET_PIXELS_SHIFT) | 272 (vsyncOffsetChars << CFG_VGA_VSYNC_OFFSET_CHARS_SHIFT) | 273 (vsyncOffsetHXtra << 274 CFG_VGA_VSYNC_OFFSET_HXTRA_SHIFT)); 275 } 276 if (pTDFX->numChips==1 && aaSamples) { 277 /* 1 chip 2 AA */ 278 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 279 CFG_ENHANCED_VIDEO_EN | 280 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 281 CFG_VIDEO_OTHERMUX_SEL_PIPE<<CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT | 282 CFG_DIVIDE_VIDEO_BY_2); 283 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 284 0x0 << CFG_SLI_RENDERMASK_FETCH_SHIFT | 285 0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT | 286 0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT | 287 0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT); 288 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 289 0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT | 290 0xff << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT); 291 } else if (pTDFX->numChips==2 && !sliEnable && aaSamples==4 && 292 !sliAnalog) { 293 /* 2 chips 4 digital AA */ 294 if (!i) { 295 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 296 CFG_ENHANCED_VIDEO_EN | 297 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 298 (CFG_VIDEO_OTHERMUX_SEL_PIPE_PLUS_AAFIFO << 299 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 300 CFG_DIVIDE_VIDEO_BY_4); 301 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 302 (0x0 << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 303 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 304 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 305 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 306 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 307 (0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 308 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 309 } else { 310 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 311 (CFG_ENHANCED_VIDEO_EN | 312 CFG_ENHANCED_VIDEO_SLV | 313 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 314 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 315 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 316 CFG_DIVIDE_VIDEO_BY_1)); 317 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 318 (0x0 << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 319 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 320 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 321 (0xff << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 322 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 323 (0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 324 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 325 } 326 } else if (pTDFX->numChips==2 && !sliEnable && aaSamples==4 && sliAnalog) { 327 /* 2 chips 4 analog AA */ 328 if (!i) { 329 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 330 (CFG_ENHANCED_VIDEO_EN | 331 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 332 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 333 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 334 CFG_DIVIDE_VIDEO_BY_4)); 335 } else { 336 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 337 CFG_ENHANCED_VIDEO_EN | 338 CFG_ENHANCED_VIDEO_SLV | 339 CFG_DAC_HSYNC_TRISTATE | 340 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 341 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 342 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 343 CFG_DIVIDE_VIDEO_BY_4); 344 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 345 (0x0 << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 346 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 347 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 348 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 349 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 350 (0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 351 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 352 } 353 } else if (pTDFX->numChips==2 && sliEnable && !aaSamples && !sliAnalog) { 354 /* 2 chips 2 digital SLI */ 355 if (!i) { 356 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 357 (CFG_ENHANCED_VIDEO_EN | 358 (CFG_VIDEO_OTHERMUX_SEL_AAFIFO << 359 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 360 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 361 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 362 CFG_DIVIDE_VIDEO_BY_1)); 363 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 364 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 365 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 366 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 367 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 368 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 369 ((0x0<<sliLinesLog2) << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 370 ((0x1<<sliLinesLog2) << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 371 } else { 372 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 373 CFG_ENHANCED_VIDEO_EN | 374 CFG_ENHANCED_VIDEO_SLV | 375 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 376 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 377 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 378 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 379 CFG_DIVIDE_VIDEO_BY_1); 380 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 381 (((pTDFX->numChips-1)<<sliLinesLog2) << 382 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 383 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 384 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 385 (0xff << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 386 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 387 (((pTDFX->numChips-1)<<sliLinesLog2) << 388 CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 389 ((i<<sliLinesLog2) << 390 CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 391 } 392 } else if (pTDFX->numChips>=2 && sliEnable && !aaSamples && sliAnalog) { 393 /* 2 or 4 chips 2/4 analog SLI */ 394 if (!i) { 395 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 396 CFG_ENHANCED_VIDEO_EN | 397 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 398 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 399 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 400 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 401 CFG_DIVIDE_VIDEO_BY_1); 402 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 403 (((pTDFX->numChips-1)<<sliLinesLog2) << 404 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 405 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 406 (((pTDFX->numChips-1)<<sliLinesLog2) << 407 CFG_SLI_RENDERMASK_CRT_SHIFT) | 408 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 409 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 410 (0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 411 (0xff << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 412 } else { 413 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 414 CFG_ENHANCED_VIDEO_EN | 415 CFG_ENHANCED_VIDEO_SLV | 416 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 417 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 418 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 419 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 420 CFG_DIVIDE_VIDEO_BY_1); 421 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 422 (((pTDFX->numChips-1)<<sliLinesLog2) << 423 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 424 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 425 (((pTDFX->numChips-1)<<sliLinesLog2) << 426 CFG_SLI_RENDERMASK_CRT_SHIFT) | 427 ((i<<sliLinesLog2) << 428 CFG_SLI_COMPAREMASK_CRT_SHIFT)); 429 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 430 (0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 431 (0xff << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 432 } 433 } else if (pTDFX->numChips==2 && sliEnable && aaSamples==2 && !sliAnalog) { 434 /* 2 chips 2 AA 2 digital SLI */ 435 if (!i) { 436 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 437 CFG_ENHANCED_VIDEO_EN | 438 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 439 (CFG_VIDEO_OTHERMUX_SEL_AAFIFO << 440 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 441 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 442 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 443 CFG_DIVIDE_VIDEO_BY_2); 444 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 445 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 446 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 447 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 448 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 449 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 450 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 451 ((0x1<<sliLinesLog2) << 452 CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 453 } else { 454 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 455 CFG_ENHANCED_VIDEO_EN | 456 CFG_ENHANCED_VIDEO_SLV | 457 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 458 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 459 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 460 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 461 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 462 CFG_DIVIDE_VIDEO_BY_1); 463 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 464 (((pTDFX->numChips-1)<<sliLinesLog2) << 465 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 466 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 467 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 468 (0xff << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 469 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 470 (((pTDFX->numChips-1)<<sliLinesLog2) << 471 CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 472 ((i<<sliLinesLog2) << 473 CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 474 } 475 } else if (pTDFX->numChips==2 && !sliEnable && aaSamples==2 && !sliAnalog) { 476 /* 2 chips 2 digital AA */ 477 if (!i) { 478 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 479 CFG_ENHANCED_VIDEO_EN | 480 (CFG_VIDEO_OTHERMUX_SEL_PIPE_PLUS_AAFIFO << 481 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 482 CFG_DIVIDE_VIDEO_BY_2); 483 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 484 (0x0 << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 485 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 486 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 487 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 488 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 489 (0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 490 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 491 } else { 492 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 493 CFG_ENHANCED_VIDEO_EN | 494 CFG_ENHANCED_VIDEO_SLV | 495 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 496 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 497 CFG_DIVIDE_VIDEO_BY_1); 498 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 499 (0x0 << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 500 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 501 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 502 (0xff << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 503 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 504 (0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 505 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 506 } 507 } else if (pTDFX->numChips==2 && !sliEnable && aaSamples==2 && sliAnalog) { 508 /* 2 chips 2 analog AA */ 509 if (!i) { 510 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 511 CFG_ENHANCED_VIDEO_EN | 512 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 513 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 514 CFG_DIVIDE_VIDEO_BY_2); 515 } else { 516 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 517 CFG_ENHANCED_VIDEO_EN | 518 CFG_ENHANCED_VIDEO_SLV | 519 CFG_DAC_HSYNC_TRISTATE | 520 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 521 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 522 CFG_DIVIDE_VIDEO_BY_2); 523 } 524 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 525 (0x0 << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 526 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 527 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 528 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 529 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 530 (0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 531 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 532 } else if (pTDFX->numChips>=2 && sliEnable && aaSamples==2 && sliAnalog) { 533 /* 2 or 4 chips 2 AA 2 or 4 analog SLI */ 534 if (!i) { 535 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 536 CFG_ENHANCED_VIDEO_EN | 537 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 538 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 539 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 540 CFG_DIVIDE_VIDEO_BY_2); 541 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 542 (((pTDFX->numChips-1)<<sliLinesLog2) << 543 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 544 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 545 (((pTDFX->numChips-1)<<sliLinesLog2) << 546 CFG_SLI_RENDERMASK_CRT_SHIFT) | 547 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 548 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 549 (0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 550 (0xff << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 551 } else { 552 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 553 CFG_ENHANCED_VIDEO_EN | 554 CFG_ENHANCED_VIDEO_SLV | 555 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 556 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 557 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 558 CFG_DIVIDE_VIDEO_BY_2); 559 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 560 (((pTDFX->numChips-1)<<sliLinesLog2) << 561 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 562 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 563 (((pTDFX->numChips-1)<<sliLinesLog2) << 564 CFG_SLI_RENDERMASK_CRT_SHIFT) | 565 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 566 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 567 (0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 568 (0xff << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 569 } 570 } else if (pTDFX->numChips==4 && sliEnable && !aaSamples && !sliAnalog) { 571 /* 4 chips 4 digital SLI */ 572 if (!i) { 573 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 574 CFG_ENHANCED_VIDEO_EN | 575 (CFG_VIDEO_OTHERMUX_SEL_AAFIFO << 576 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 577 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 578 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 579 CFG_SLI_AAFIFO_COMPARE_INV | 580 CFG_DIVIDE_VIDEO_BY_1); 581 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 582 (((pTDFX->numChips-1)<<sliLinesLog2) << 583 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 584 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 585 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 586 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 587 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 588 (((pTDFX->numChips-1)<<sliLinesLog2) << 589 CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 590 ((0x0<<sliLinesLog2) << 591 CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 592 } else { 593 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 594 CFG_ENHANCED_VIDEO_EN | 595 CFG_ENHANCED_VIDEO_SLV | 596 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 597 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 598 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 599 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 600 CFG_DIVIDE_VIDEO_BY_1); 601 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 602 (((pTDFX->numChips-1)<<sliLinesLog2) << 603 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 604 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 605 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 606 (0xff << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 607 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 608 (((pTDFX->numChips-1)<<sliLinesLog2) << 609 CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 610 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 611 } 612 } else if (pTDFX->numChips==4 && sliEnable && aaSamples==2 && !sliAnalog) { 613 /* 4 chips 2 AA 4 digital SLI */ 614 if (!i) { 615 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 616 CFG_ENHANCED_VIDEO_EN | 617 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 618 (CFG_VIDEO_OTHERMUX_SEL_AAFIFO << 619 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 620 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 621 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 622 CFG_SLI_AAFIFO_COMPARE_INV | 623 CFG_DIVIDE_VIDEO_BY_2); 624 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 625 (((pTDFX->numChips-1)<<sliLinesLog2) << 626 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 627 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 628 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 629 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 630 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 631 (((pTDFX->numChips-1)<<sliLinesLog2) << 632 CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 633 ((0x0<<sliLinesLog2) << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 634 } else { 635 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 636 CFG_ENHANCED_VIDEO_EN | 637 CFG_ENHANCED_VIDEO_SLV | 638 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 639 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 640 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 641 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 642 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 643 CFG_DIVIDE_VIDEO_BY_1); 644 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 645 (((pTDFX->numChips-1)<<sliLinesLog2) << 646 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 647 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 648 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 649 (0xff << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 650 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 651 (((pTDFX->numChips-1)<<sliLinesLog2) << 652 CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 653 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 654 } 655 } else if (pTDFX->numChips==4 && sliEnable && aaSamples==4 && !sliAnalog) { 656 /* 4 chips 4 AA 2 digital SLI */ 657 if (!i) { 658 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 659 CFG_ENHANCED_VIDEO_EN | 660 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 661 (CFG_VIDEO_OTHERMUX_SEL_PIPE_PLUS_AAFIFO << 662 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 663 CFG_DIVIDE_VIDEO_BY_4); 664 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 665 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 666 ((0x0<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 667 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_CRT_SHIFT) | 668 ((0x0<<sliLinesLog2) << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 669 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 670 (0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 671 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 672 } else if (i==1 || i==3) { 673 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 674 CFG_ENHANCED_VIDEO_EN | 675 CFG_ENHANCED_VIDEO_SLV | 676 CFG_DAC_HSYNC_TRISTATE | 677 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 678 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 679 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 680 CFG_DIVIDE_VIDEO_BY_1); 681 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 682 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 683 ((((i+1)>>2)<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 684 ((0x0<<sliLinesLog2) << CFG_SLI_RENDERMASK_CRT_SHIFT) | 685 ((0xff<<sliLinesLog2) << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 686 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 687 (0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 688 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 689 } else { 690 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 691 CFG_ENHANCED_VIDEO_EN | 692 CFG_ENHANCED_VIDEO_SLV | 693 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 694 (CFG_VIDEO_OTHERMUX_SEL_PIPE_PLUS_AAFIFO << 695 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 696 CFG_DIVIDE_VIDEO_BY_4); 697 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 698 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 699 ((0x1<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 700 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_CRT_SHIFT) | 701 ((0x1<<sliLinesLog2) << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 702 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 703 (0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 704 (0xff << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 705 } 706 } else if (pTDFX->numChips==4 && sliEnable && aaSamples==4 && sliAnalog) { 707 /* 4 chips 4 AA 2 analog SLI */ 708 if (!i) { 709 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 710 CFG_ENHANCED_VIDEO_EN | 711 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 712 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 713 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 714 CFG_DIVIDE_VIDEO_BY_4); 715 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 716 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 717 ((0x0<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 718 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_CRT_SHIFT) | 719 ((0x0<<sliLinesLog2) << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 720 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 721 (0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 722 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 723 } else if (i==1 || i==3) { 724 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 725 CFG_ENHANCED_VIDEO_EN | 726 CFG_ENHANCED_VIDEO_SLV | 727 CFG_DAC_HSYNC_TRISTATE | 728 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 729 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 730 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 731 CFG_DIVIDE_VIDEO_BY_4); 732 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 733 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 734 ((((i+1)>>2)<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 735 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_CRT_SHIFT) | 736 ((((i+1)>>2)<<sliLinesLog2) << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 737 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 738 (0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 739 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 740 } else { 741 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 742 CFG_ENHANCED_VIDEO_EN | 743 CFG_ENHANCED_VIDEO_SLV | 744 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 745 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 746 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 747 CFG_DIVIDE_VIDEO_BY_4); 748 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL1, 749 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 750 ((0x1<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 751 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_CRT_SHIFT) | 752 ((0x1<<sliLinesLog2) << CFG_SLI_COMPAREMASK_CRT_SHIFT)); 753 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL2, 754 (0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 755 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT)); 756 } 757 } 758 if (pTDFX->numChips==4 && sliEnable && aaSamples==4 && i==3) { 759 v=pciReadLong(pTDFX->PciTag[i], CFG_SLI_AA_MISC); 760 pciWriteLong(pTDFX->PciTag[i], CFG_SLI_AA_MISC, 761 v | CFG_AA_LFB_RD_SLV_WAIT); 762 } 763 if (i) { 764 v=pciReadLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0); 765 pciWriteLong(pTDFX->PciTag[i], CFG_VIDEO_CTRL0, 766 v|CFG_VIDPLL_SEL); 767 v=pTDFX->readChipLong(pTDFX, i, MISCINIT1); 768 pTDFX->writeChipLong(pTDFX, i, MISCINIT1, v|SST_POWERDOWN_DAC); 769 } 770 } 771 return TRUE; 772} 773