17706df26Smrg#ifdef HAVE_CONFIG_H
27706df26Smrg#include "config.h"
37706df26Smrg#endif
47706df26Smrg
57706df26Smrg#include "xf86.h"
67706df26Smrg#include "xf86_OSproc.h"
77706df26Smrg
87706df26Smrg#include "xf86PciInfo.h"
97706df26Smrg#include "xf86Pci.h"
107706df26Smrg
117706df26Smrg#include "BT.h"
127706df26Smrg#include "tga_regs.h"
137706df26Smrg#include "tga.h"
147706df26Smrg
157706df26Smrg
167706df26Smrg#define BT463_LOAD_ADDR(a) \
177706df26Smrg        TGA_WRITE_REG(BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG); \
187706df26Smrg        TGA_WRITE_REG((BT463_ADDR_LO<<10)|((a)&0xff), TGA_RAMDAC_REG); \
197706df26Smrg        TGA_WRITE_REG(BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG); \
207706df26Smrg        TGA_WRITE_REG((BT463_ADDR_HI<<10)|(((a)>>8)&0xff), TGA_RAMDAC_REG);
217706df26Smrg
227706df26Smrg#define BT463_WRITE(m,a,v) \
237706df26Smrg        BT463_LOAD_ADDR((a)); \
247706df26Smrg        TGA_WRITE_REG(((m)<<2),TGA_RAMDAC_SETUP_REG); \
257706df26Smrg        TGA_WRITE_REG(((m)<<10)|((v)&0xff),TGA_RAMDAC_REG);
267706df26Smrg
277706df26Smrg/*
287706df26Smrg * useful defines for managing the BT463 on the 24-plane TGAs
297706df26Smrg */
307706df26Smrg#define BT463_READ_BIT          0x2
317706df26Smrg
327706df26Smrg#define	BT463_ADDR_LO		0x0
337706df26Smrg#define	BT463_ADDR_HI		0x1
347706df26Smrg#define	BT463_REG_ACC		0x2
357706df26Smrg#define	BT463_PALETTE		0x3
367706df26Smrg
377706df26Smrg#define	BT463_CUR_CLR_0		0x0100
387706df26Smrg#define	BT463_CUR_CLR_1		0x0101
397706df26Smrg
407706df26Smrg#define	BT463_CMD_REG_0		0x0201
417706df26Smrg#define	BT463_CMD_REG_1		0x0202
427706df26Smrg#define	BT463_CMD_REG_2		0x0203
437706df26Smrg
447706df26Smrg#define	BT463_READ_MASK_0	0x0205
457706df26Smrg#define	BT463_READ_MASK_1	0x0206
467706df26Smrg#define	BT463_READ_MASK_2	0x0207
477706df26Smrg#define	BT463_READ_MASK_3	0x0208
487706df26Smrg
497706df26Smrg#define	BT463_BLINK_MASK_0	0x0209
507706df26Smrg#define	BT463_BLINK_MASK_1	0x020a
517706df26Smrg#define	BT463_BLINK_MASK_2	0x020b
527706df26Smrg#define	BT463_BLINK_MASK_3	0x020c
537706df26Smrg
547706df26Smrg#define	BT463_WINDOW_TYPE_BASE	0x0300
557706df26Smrg
567706df26Smrg
577706df26Smrgstatic unsigned
587706df26SmrgBT463_READ(TGAPtr pTga, unsigned m, unsigned a)
597706df26Smrg{
607706df26Smrg  unsigned val;
617706df26Smrg
627706df26Smrg  BT463_LOAD_ADDR(a);
637706df26Smrg  TGA_WRITE_REG((m<<2)|0x2, TGA_RAMDAC_SETUP_REG);
647706df26Smrg  val = TGA_READ_REG(TGA_RAMDAC_REG);
657706df26Smrg  val = (val >> 16) & 0xff;
667706df26Smrg  return val;
677706df26Smrg}
687706df26Smrg
697706df26Smrg
707706df26Smrgvoid
717706df26SmrgBT463ramdacSave(ScrnInfoPtr pScrn, unsigned char *Bt463)
727706df26Smrg{
737706df26Smrg  TGAPtr pTga = TGAPTR(pScrn);
747706df26Smrg  int i, j;
757706df26Smrg
767706df26Smrg  Bt463[0] = BT463_READ(pTga, BT463_REG_ACC, BT463_CMD_REG_0);
777706df26Smrg  Bt463[1] = BT463_READ(pTga, BT463_REG_ACC, BT463_CMD_REG_1);
787706df26Smrg  Bt463[2] = BT463_READ(pTga, BT463_REG_ACC, BT463_CMD_REG_2);
797706df26Smrg
807706df26Smrg  Bt463[3] = BT463_READ(pTga, BT463_REG_ACC, BT463_READ_MASK_0);
817706df26Smrg  Bt463[4] = BT463_READ(pTga, BT463_REG_ACC, BT463_READ_MASK_1);
827706df26Smrg  Bt463[5] = BT463_READ(pTga, BT463_REG_ACC, BT463_READ_MASK_2);
837706df26Smrg  Bt463[6] = BT463_READ(pTga, BT463_REG_ACC, BT463_READ_MASK_3);
847706df26Smrg
857706df26Smrg  Bt463[7] = BT463_READ(pTga, BT463_REG_ACC, BT463_BLINK_MASK_0);
867706df26Smrg  Bt463[8] = BT463_READ(pTga, BT463_REG_ACC, BT463_BLINK_MASK_1);
877706df26Smrg  Bt463[9] = BT463_READ(pTga, BT463_REG_ACC, BT463_BLINK_MASK_2);
887706df26Smrg  Bt463[10] = BT463_READ(pTga, BT463_REG_ACC, BT463_BLINK_MASK_3);
897706df26Smrg
907706df26Smrg  BT463_LOAD_ADDR(BT463_WINDOW_TYPE_BASE);
917706df26Smrg  TGA_WRITE_REG((BT463_REG_ACC<<2)|0x2, TGA_RAMDAC_SETUP_REG);
927706df26Smrg
937706df26Smrg  for (i = 0, j = 11; i < 16; i++) {
947706df26Smrg    Bt463[j++] = (TGA_READ_REG(TGA_RAMDAC_REG)>>16)&0xff;
957706df26Smrg    Bt463[j++] = (TGA_READ_REG(TGA_RAMDAC_REG)>>16)&0xff;
967706df26Smrg    Bt463[j++] = (TGA_READ_REG(TGA_RAMDAC_REG)>>16)&0xff;
977706df26Smrg  }
987706df26Smrg
997706df26Smrg/*
1007706df26Smrg  fprintf(stderr, "BT463ramdacSave (%p)\n", Bt463);
1017706df26Smrg  for (i=0; i<58; i++)
1027706df26Smrg    fprintf(stderr, "%2d: 0x%02x\n", i, (unsigned)Bt463[i]);
1037706df26Smrg*/
1047706df26Smrg}
1057706df26Smrg
1067706df26Smrg
1077706df26Smrgvoid
1087706df26SmrgBT463ramdacRestore(ScrnInfoPtr pScrn, unsigned char *Bt463)
1097706df26Smrg{
1107706df26Smrg  TGAPtr pTga = TGAPTR(pScrn);
1117706df26Smrg  int i, j;
1127706df26Smrg
1137706df26Smrg  BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_0, Bt463[0]);
1147706df26Smrg  BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_1, Bt463[1]);
1157706df26Smrg  BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_2, Bt463[2]);
1167706df26Smrg
1177706df26Smrg  BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_0, Bt463[3]);
1187706df26Smrg  BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_1, Bt463[4]);
1197706df26Smrg  BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_2, Bt463[5]);
1207706df26Smrg  BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_3, Bt463[6]);
1217706df26Smrg
1227706df26Smrg  BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_0, Bt463[7]);
1237706df26Smrg  BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_1, Bt463[8]);
1247706df26Smrg  BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_2, Bt463[9]);
1257706df26Smrg  BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_3, Bt463[10]);
1267706df26Smrg
1277706df26Smrg  BT463_LOAD_ADDR(BT463_WINDOW_TYPE_BASE);
1287706df26Smrg  TGA_WRITE_REG((BT463_REG_ACC<<2), TGA_RAMDAC_SETUP_REG);
1297706df26Smrg
1307706df26Smrg  for (i = 0, j = 11; i < 16; i++) {
1317706df26Smrg    TGA_WRITE_REG(Bt463[j++]|(BT463_REG_ACC<<10), TGA_RAMDAC_REG);
1327706df26Smrg    TGA_WRITE_REG(Bt463[j++]|(BT463_REG_ACC<<10), TGA_RAMDAC_REG);
1337706df26Smrg    TGA_WRITE_REG(Bt463[j++]|(BT463_REG_ACC<<10), TGA_RAMDAC_REG);
1347706df26Smrg  }
1357706df26Smrg
1367706df26Smrg/*
1377706df26Smrg  fprintf(stderr, "BT463ramdacRestore (%p)\n", Bt463);
1387706df26Smrg  for (i=0; i<58; i++)
1397706df26Smrg    fprintf(stderr, "%2d: 0x%02x\n", i, (unsigned)Bt463[i]);
1407706df26Smrg*/
1417706df26Smrg}
142