IBM561ramdac.c revision 7706df26
1/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/tga/IBM561ramdac.c,v 1.3 2001/02/15 11:03:58 alanh Exp $ */ 2 3#ifdef HAVE_CONFIG_H 4#include "config.h" 5#endif 6 7#include "xf86.h" 8#include "xf86_OSproc.h" 9 10#include "xf86PciInfo.h" 11#include "xf86Pci.h" 12 13#include "tga_regs.h" 14#include "tga.h" 15 16/* 17 * useful defines for managing the IBM561 on the 24-plane TGA2s 18 */ 19 20#define IBM561_HEAD_MASK 0x01 21#define IBM561_READ 0x02 22#define IBM561_WRITE 0x00 23 24#define RAMDAC_ONE_BYTE 0x0E000 25#define RAMDAC_TWO_BYTES 0x0c000 26#define RAMDAC_THREE_BYTES 0x08000 27#define RAMDAC_FOUR_BYTES 0x00000 28 29#define IBM561_ADDR_LOW 0x0000 30#define IBM561_ADDR_HIGH 0x0100 31#define IBM561_CMD_REGS 0x0200 32 33#define IBM561_CMD_CURS_PIX 0x0200 34#define IBM561_CMD_CURS_LUT 0x0300 35#define IBM561_CMD_FB_WAT 0x0300 36#define IBM561_CMD_AUXFB_WAT 0x0200 37#define IBM561_CMD_OL_WAT 0x0300 38#define IBM561_CMD_AUXOL_WAT 0x0200 39#define IBM561_CMD_GAMMA 0x0300 40#define IBM561_CMD_CMAP 0x0300 41 42#define IBM561_ADDR_EPSR_SHIFT 0 43#define IBM561_ADDR_EPDR_SHIFT 8 44 45#define IBM561_CONFIG_REG_1 0x0001 46#define IBM561_CONFIG_REG_2 0x0002 47#define IBM561_CONFIG_REG_1 0x0001 48#define IBM561_CONFIG_REG_2 0x0002 49#define IBM561_CONFIG_REG_3 0x0003 50#define IBM561_CONFIG_REG_4 0x0004 51#define IBM561_WAT_SEG_REG 0x0006 52#define IBM561_OL_SEG_REG 0x0007 53#define IBM561_CHROMA_KEY_REG0 0x0010 54#define IBM561_CHROMA_KEY_REG1 0x0011 55#define IBM561_CHROMA_MASK_REG0 0x0012 56#define IBM561_CHROMA_MASK_REG1 0x0013 57#define IBM561_SYNC_CONTROL 0x0020 58#define IBM561_PLL_VCO_DIV_REG 0x0021 59#define IBM561_PLL_REF_REG 0x0022 60#define IBM561_CURSOR_CTRL_REG 0x0030 61#define IBM561_CURSOR_HS_REG 0x0034 62#define IBM561_VRAM_MASK_REG 0x0050 63#define IBM561_DAC_CTRL 0x005f 64#define IBM561_DIV_DOT_CLK_REG 0x0082 65 66#define IBM561_READ_MASK 0x0205 67#define IBM561_BLINK_MASK 0x0209 68#define IBM561_FB_WINDOW_TYPE_TABLE 0x1000 69#define IBM561_AUXFB_WINDOW_TYPE_TABLE 0x0E00 70#define IBM561_OL_WINDOW_TYPE_TABLE 0x1400 71#define IBM561_AUXOL_WINDOW_TYPE_TABLE 0x0F00 72#define IBM561_RED_GAMMA_TABLE 0x3000 73#define IBM561_GREEN_GAMMA_TABLE 0x3400 74#define IBM561_BLUE_GAMMA_TABLE 0x3800 75#define IBM561_COLOR_LOOKUP_TABLE 0x4000 76#define IBM561_CURSOR_LOOKUP_TABLE 0x0a11 77#define IBM561_CURSOR_BLINK_TABLE 0x0a15 78#define IBM561_CROSS_LOOKUP_TABLE 0x0a19 79#define IBM561_CROSS_BLINK_TABLE 0x0a1d 80#define IBM561_CURSOR_PIXMAP 0x2000 81#define IBM561_CURSOR_X_LOW 0x0036 82#define IBM561_CURSOR_X_HIGH 0x0037 83#define IBM561_CURSOR_Y_LOW 0x0038 84#define IBM561_CURSOR_Y_HIGH 0x0039 85 86#define LO_ADDR (IBM561_ADDR_LOW | RAMDAC_ONE_BYTE) 87#define HI_ADDR (IBM561_ADDR_HIGH | RAMDAC_ONE_BYTE) 88 89#define REGS_ADDR (IBM561_CMD_REGS | RAMDAC_ONE_BYTE) 90#define FBWAT_ADDR (IBM561_CMD_FB_WAT | RAMDAC_ONE_BYTE) 91#define AUXFBWAT_ADDR (IBM561_CMD_AUXFB_WAT | RAMDAC_ONE_BYTE) 92#define OLWAT_ADDR (IBM561_CMD_OL_WAT | RAMDAC_ONE_BYTE) 93#define AUXOLWAT_ADDR (IBM561_CMD_AUXOL_WAT | RAMDAC_ONE_BYTE) 94#define CMAP_ADDR (IBM561_CMD_CMAP | RAMDAC_ONE_BYTE) 95#define GAMMA_ADDR (IBM561_CMD_GAMMA | RAMDAC_ONE_BYTE) 96 97#define IBM561LoadAddr(reg) \ 98do { \ 99 TGA2_WRITE_RAMDAC_REG((reg), LO_ADDR); \ 100 TGA2_WRITE_RAMDAC_REG((reg) >> 8, HI_ADDR); \ 101} while (0) 102 103unsigned char 104IBM561ReadReg(ScrnInfoPtr pScrn, CARD32 reg) 105{ 106 TGAPtr pTga; 107 unsigned char ret; 108 109 pTga = TGAPTR(pScrn); 110 111 TGA2_WRITE_RAMDAC_REG(reg, LO_ADDR); 112 TGA2_WRITE_RAMDAC_REG(reg >> 8, HI_ADDR); 113 114 ret = TGA2_READ_RAMDAC_REG(REGS_ADDR); 115 116#if 1 117 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "IBM561ReadReg: reg 0x%lx data 0x%x\n", 118 (unsigned long)reg, ret); 119#endif 120 return (ret); 121} 122 123void 124IBM561WriteReg(ScrnInfoPtr pScrn, CARD32 reg, 125#if 0 126 unsigned char mask, unsigned char data) 127#else 128 unsigned char data) 129#endif 130{ 131 TGAPtr pTga; 132 unsigned char tmp = 0x00; 133 134 pTga = TGAPTR(pScrn); 135 136#if 0 137 if (mask != 0x00) { 138 TGA2_WRITE_RAMDAC_REG(reg, LO_ADDR); 139 TGA2_WRITE_RAMDAC_REG(reg >> 8, HI_ADDR); 140 tmp = TGA2_READ_RAMDAC_REG(REGS_ADDR) & mask; 141 } 142#endif 143 144#if 1 145 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "IBM561WriteReg: reg 0x%lx data 0x%x\n", 146 (unsigned long)reg, tmp | data); 147#endif 148 149 TGA2_WRITE_RAMDAC_REG(reg, LO_ADDR); 150 TGA2_WRITE_RAMDAC_REG(reg >> 8, HI_ADDR); 151 TGA2_WRITE_RAMDAC_REG ((tmp | data), REGS_ADDR); 152} 153 154void 155IBM561ramdacSave(ScrnInfoPtr pScrn, unsigned char *Ibm561) 156{ 157#if 0 158 TGAPtr pTga = TGAPTR(pScrn); 159 int i, j; 160 161 /* ?? FIXME OR NOT this is from BT463ramdacSave ?? */ 162 Ibm561[0] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_CMD_REG_0); 163 Ibm561[1] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_CMD_REG_1); 164 Ibm561[2] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_CMD_REG_2); 165 166 Ibm561[3] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_READ_MASK_0); 167 Ibm561[4] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_READ_MASK_1); 168 Ibm561[5] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_READ_MASK_2); 169 Ibm561[6] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_READ_MASK_3); 170 171 Ibm561[7] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_BLINK_MASK_0); 172 Ibm561[8] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_BLINK_MASK_1); 173 Ibm561[9] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_BLINK_MASK_2); 174 Ibm561[10] = IBM561_READ(pTga, IBM561_REG_ACC, IBM561_BLINK_MASK_3); 175 176 IBM561_LOAD_ADDR(IBM561_WINDOW_TYPE_BASE); 177 TGA_WRITE_REG((IBM561_REG_ACC<<2)|0x2, TGA_RAMDAC_SETUP_REG); 178 179 for (i = 0, j = 11; i < 16; i++) { 180 Ibm561[j++] = (TGA_READ_REG(TGA_RAMDAC_REG)>>16)&0xff; 181 Ibm561[j++] = (TGA_READ_REG(TGA_RAMDAC_REG)>>16)&0xff; 182 Ibm561[j++] = (TGA_READ_REG(TGA_RAMDAC_REG)>>16)&0xff; 183 } 184#endif 185 186/* 187 fprintf(stderr, "IBM561ramdacSave (%p)\n", Ibm561); 188 for (i=0; i<58; i++) 189 fprintf(stderr, "%2d: 0x%02x\n", i, (unsigned)Ibm561[i]); 190*/ 191} 192 193static void 194IBM561WindowTagsInit(ScrnInfoPtr pScrn) 195{ 196 TGAPtr pTga = TGAPTR(pScrn); 197 unsigned char low, high; 198 int i; 199 200/* 201 tga.h defines fb_wid_cell_t as a structure containing two bytes, 202 low and high in order. The 561 has 10 bit window tags so only 203 part of the high byte is used (actually only 2 bits). Pixel C for 204 8-plane indexes uses 16bpp indexing per IBM's application notes 205 which describe quad bufering. Note, this array is arranged as 206 low byte followed by high byte which will apppear backwards 207 relative to the 561 spec( a value of 0x01 in the high byte 208 really represents a color table starting address of 256). 209 ex (entry 4): 210 {0x28, 0x01}, *4 8-plane index (PIXEL C 561 H/W screw-up) * 211 low byte = 0x28 212 high byte = 0x01 213 wat entry = 0x0128 214 215 from the spec: 8 in the low nibble selects buffer 1 216 2 in the next nibble selects pixformat of 16 bpp 217 1 in the next nibble indicates a start addr of 256 218*/ 219typedef struct { 220 unsigned char low_byte; 221 unsigned char high_byte; 222}fb_wid_cell_t; 223 224typedef struct { 225 unsigned char aux_fbwat; 226} aux_fb_wid_cell_t; 227 228typedef struct { 229 unsigned char low_byte; 230 unsigned char high_byte; 231} ol_wid_cell_t; 232 233typedef struct { 234 unsigned char aux_olwat; 235} aux_ol_wid_cell_t; 236 237/* 238 * There are actually 256 window tag entries in the FB and OL WAT tables. 239 * We will use only 16 for compatability with the BT463 and more importantly 240 * to implement the virtual ramdac interface. This requires us to only 241 * report the smallest WAT table size, in this case its the auxillary wat 242 * tables which are 16 entries. 243 */ 244 245#define TGA_RAMDAC_561_FB_WINDOW_TAG_COUNT 256 246#define TGA_RAMDAC_561_FB_WINDOW_TAG_MAX_COUNT 16 247#define TGA_RAMDAC_561_AUXFB_WINDOW_TAG_COUNT 16 248#define TGA_RAMDAC_561_OL_WINDOW_TAG_COUNT 256 249#define TGA_RAMDAC_561_OL_WINDOW_TAG_MAX_COUNT 16 250#define TGA_RAMDAC_561_AUXOL_WINDOW_TAG_COUNT 16 251#define TGA_RAMDAC_561_CMAP_ENTRY_COUNT 1024 252#define TGA_RAMDAC_561_GAM_ENTRY_COUNT 256 253 254 static fb_wid_cell_t 255 fb_wids_561[TGA_RAMDAC_561_FB_WINDOW_TAG_COUNT] = { 256#if 0 257 {0x28, 0x00}, /*0 8-plane index (PIXEL C 561 H/W screw-up) */ 258#else 259 {0x36, 0x00}, /*c 24-plane true */ 260#endif 261 {0x08, 0x00}, /*1 8-plane index (PIXEL B) */ 262 {0x00, 0x00}, /*2 8-plane index (PIXEL A) */ 263 {0x34, 0x00}, /*3 24-plane direct, cmap 0 */ 264 {0x28, 0x01}, /*4 8-plane index (PIXEL C 561 H/W screw-up) */ 265 {0x08, 0x01}, /*5 8-plane index (PIXEL B) */ 266 {0x00, 0x01}, /*6 8-plane index (PIXLE A) */ 267 {0x34, 0x01}, /*7 24-plane direct, cmap 1 */ 268 {0x1e, 0x00}, /*8 12-plane true */ 269 /*{0x16, 0x00}, 9 12-plane true */ 270 {0x14, 0x00}, /*9 12-plane true(direct) */ 271 {0x1e, 0x01}, /*a 12-plane true */ 272 {0x16, 0x01}, /*b 12-plane true */ 273 {0x36, 0x00}, /*c 24-plane true */ 274 {0x36, 0x00}, /*d 24-plane true */ 275 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 276 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 277 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 278 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 279 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 280 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 281 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 282 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 283 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 284 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 285 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 286 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 287 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 288 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 289 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 290 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 291 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 292 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 293 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 294 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 295 {0,0},{0,0} 296 }; 297 298 static aux_fb_wid_cell_t 299 auxfb_wids_561[TGA_RAMDAC_561_AUXFB_WINDOW_TAG_COUNT] = { 300 {0x04}, /*0 GMA=bypass, XH=disable, PT=dc */ 301 {0x04}, /*1 GMA=bypass, XH=disable, PT=dc */ 302 {0x04}, /*2 GMA=bypass, XH=disable, PT=dc */ 303 {0x04}, /*3 GMA=bypass, XH=disable, PT=dc */ 304 {0x04}, /*4 GMA=bypass, XH=disable, PT=dc */ 305 {0x04}, /*5 GMA=bypass, XH=disable, PT=dc */ 306 {0x04}, /*6 GMA=bypass, XH=disable, PT=dc */ 307 {0x04}, /*7 GMA=bypass, XH=disable, PT=dc */ 308 {0x04}, /*8 GMA=bypass, XH=disable, PT=dc */ 309 {0x04}, /*9 GMA=bypass, XH=disable, PT=dc */ 310 {0x04}, /*a GMA=bypass, XH=disable, PT=dc */ 311 {0x04}, /*b GMA=bypass, XH=disable, PT=dc */ 312 {0x04}, /*c GMA=bypass, XH=disable, PT=dc */ 313 {0x04}, /*d GMA=bypass, XH=disable, PT=dc */ 314 {0x04}, /*e old cursor colors for 463 don't use*/ 315 {0x04}, /*f old cursor colors for 463 don't use*/ 316 }; 317 318 static ol_wid_cell_t 319 ol_wids_561[TGA_RAMDAC_561_OL_WINDOW_TAG_COUNT] = { 320 {0x31, 0x02}, /*0 PX=4bpp, BS=0, MODE=index, TR=OPAQ */ 321 {0x31, 0x02}, /*1 PX=4bpp, BS=0, MODE=index, TR=OPAQ */ 322 {0x31, 0x02}, /*2 PX=4bpp, BS=0, MODE=index, TR=OPAQ */ 323 {0x31, 0x02}, /*3 PX=4bpp, BS=0, MODE=index, TR=OPAQ */ 324 {0x31, 0x02}, /*4 PX=4bpp, BS=0, MODE=index, TR=OPAQ */ 325 {0x31, 0x02}, /*5 PX=4bpp, BS=0, MODE=index, TR=OPAQ */ 326 {0x31, 0x02}, /*6 PX=4bpp, BS=0, MODE=index, TR=OPAQ */ 327 {0x31, 0x02}, /*7 PX=4bpp, BS=0, MODE=index, TR=OPAQ */ 328 {0x31, 0x02}, /*8 PX=4bpp, BS=0, MODE=index, TR=OPAQ */ 329 {0x31, 0x02}, /*9 PX=4bpp, BS=0, MODE=index, TR=OPAQ */ 330 {0x31, 0x02}, /*a PX=4bpp, BS=0, MODE=index, TR=OPAQ */ 331 {0x31, 0x02}, /*b PX=4bpp, BS=0, MODE=index, TR=OPAQ */ 332 {0x31, 0x02}, /*c PX=4bpp, BS=0, MODE=index, TR=OPAQ */ 333 {0x31, 0x02}, /*d PX=4bpp, BS=0, MODE=index, TR=OPAQ */ 334 {0x31, 0x02}, /*e PX=4bpp, BS=0, MODE=index, TR=OPAQ */ 335 {0x31, 0x02}, /*f PX=4bpp, BS=0, MODE=index, TR=OPAQ */ 336 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 337 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 338 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 339 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 340 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 341 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 342 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 343 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 344 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 345 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 346 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 347 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 348 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 349 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 350 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 351 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 352 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 353 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 354 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}, 355 {0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0} 356 }; 357 358 static aux_ol_wid_cell_t 359 auxol_wids_561[TGA_RAMDAC_561_AUXOL_WINDOW_TAG_COUNT] = { 360 {0x0c}, /*0 CK/OT=dc, UL=disabled, OL=enabled, GB=bypass */ 361 {0x0c}, /*1 CK/OT=dc, UL=disabled, OL=enabled, GB=bypass */ 362 {0x0c}, /*2 CK/OT=dc, UL=disabled, OL=enabled, GB=bypass */ 363 {0x0c}, /*3 CK/OT=dc, UL=disabled, OL=enabled, GB=use */ 364 {0x0c}, /*4 CK/OT=dc, UL=disabled, OL=enabled, GB=bypass */ 365 {0x0c}, /*5 CK/OT=dc, UL=disabled, OL=enabled, GB=bypass */ 366 {0x0c}, /*6 CK/OT=dc, UL=disabled, OL=enabled, GB=bypass */ 367 {0x0c}, /*7 CK/OT=dc, UL=disabled, OL=enabled, GB=use */ 368 {0x0c}, /*8 CK/OT=dc, UL=disabled, OL=disabled, GB=use */ 369 {0x0c}, /*9 CK/OT=dc, UL=disabled, OL=enabled, GB=use */ 370 {0x0c}, /*a CK/OT=dc, UL=disabled, OL=enabled, GB=use */ 371 {0x0c}, /*b CK/OT=dc, UL=disabled, OL=enabled, GB=use */ 372 {0x0c}, /*c CK/OT=dc, UL=disabled, OL=enabled, GB=bypass */ 373 {0x0c}, /*d CK/OT=dc, UL=disabled, OL=disabled, GB=bypass */ 374 {0x0c}, /*e old cursor color for 463, don't use */ 375 {0x0c}, /*f old cursor color for 463, don't use */ 376 }; 377 378 /* ibm561 so init the window tags's via interrupt. It must be 379 * done either during the vsync interrupt or by blanking, We will 380 * actually do both. ??????? 381 */ 382 383 IBM561LoadAddr(IBM561_FB_WINDOW_TYPE_TABLE); 384 for ( i = 0; i < TGA_RAMDAC_561_FB_WINDOW_TAG_COUNT; i++ ) { 385 low = ((fb_wids_561[i].low_byte & 0xfc) >> 2); 386 high =((fb_wids_561[i].high_byte & 0x03) << 6) & 0xff; 387 TGA2_WRITE_RAMDAC_REG (low | high, FBWAT_ADDR); 388 389 low = (fb_wids_561[i].low_byte & 0x03) << 6; 390 TGA2_WRITE_RAMDAC_REG (low, FBWAT_ADDR); 391 } 392 393 IBM561LoadAddr(IBM561_AUXFB_WINDOW_TYPE_TABLE); 394 for ( i = 0; i < TGA_RAMDAC_561_AUXFB_WINDOW_TAG_COUNT; i++ ) { 395 TGA2_WRITE_RAMDAC_REG (auxfb_wids_561[i].aux_fbwat, AUXFBWAT_ADDR); 396 } 397 398 399 IBM561LoadAddr(IBM561_OL_WINDOW_TYPE_TABLE); 400 for ( i = 0; i < TGA_RAMDAC_561_OL_WINDOW_TAG_COUNT; i++ ) { 401 low = ((ol_wids_561[i].low_byte & 0xfc) >> 2); 402 high =((ol_wids_561[i].high_byte & 0x03) << 6) & 0xff; 403 TGA2_WRITE_RAMDAC_REG (low | high, OLWAT_ADDR); 404 405 low = (ol_wids_561[i].low_byte & 0x03) << 6; 406 TGA2_WRITE_RAMDAC_REG (low, OLWAT_ADDR); 407 } 408 409 410 IBM561LoadAddr(IBM561_AUXOL_WINDOW_TYPE_TABLE); 411 for ( i = 0; i < TGA_RAMDAC_561_AUXOL_WINDOW_TAG_COUNT; i++ ) { 412 TGA2_WRITE_RAMDAC_REG (auxol_wids_561[i].aux_olwat, AUXOLWAT_ADDR); 413 } 414} 415 416/* 417 * ibm561_init_color_map 418 * 419 * Initialize color map in 561. Note the entire 420 * color map is initialized, both the 8-bit and the 24-bit 421 * portions. 422 */ 423static int 424IBM561InitColormap(ScrnInfoPtr pScrn) 425{ 426 TGAPtr pTga = TGAPTR(pScrn); 427#if 0 428 tga_ibm561_info_t *bti = (tga_ibm561_info_t *) closure; 429 tga_info_t *tgap = tga_softc[bti->unit]; 430#endif 431 int i; 432 433 TGA2_WRITE_RAMDAC_REG(IBM561_COLOR_LOOKUP_TABLE, LO_ADDR); 434 TGA2_WRITE_RAMDAC_REG(IBM561_COLOR_LOOKUP_TABLE >> 8, HI_ADDR); 435 436 TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR); 437 TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR); 438 TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR); 439 440 for ( i = 1; i <256; i++ ) { 441 TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR); 442 TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR); 443 TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR); 444 } 445 446 TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR); 447 TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR); 448 TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR); 449 450 for ( i = 1; i <256; i++ ) { 451 TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR); 452 TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR); 453 TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR); 454 } 455 456 TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR); 457 TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR); 458 TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR); 459 460 for ( i = 1; i <256; i++ ) { 461 TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR); 462 TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR); 463 TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR); 464 } 465 466 TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR); 467 TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR); 468 TGA2_WRITE_RAMDAC_REG (0x00, CMAP_ADDR); 469 470 for ( i = 1; i <256; i++ ) { 471 TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR); 472 TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR); 473 TGA2_WRITE_RAMDAC_REG (i, CMAP_ADDR); 474 } 475 476 /* 477 * The ddx layer views the gamma table as an extension of the 478 * color pallettes, therefore the gamma table is initialized here. 479 * Note, each entry in the table is 10 bits, requiring two writes 480 * per entry!! The table are initialized the same way as color tables, 481 * a zero entry followed by mulitple ff's. NOTE, the gamma tables are 482 * loaded in a strange manner, DO NOT use this code as a guide (we are 483 * writing all zero's or all ones). See the tga_ibm561_load_color_map 484 * _entry code above. 485 */ 486 487 TGA2_WRITE_RAMDAC_REG(IBM561_RED_GAMMA_TABLE, LO_ADDR); 488 TGA2_WRITE_RAMDAC_REG(IBM561_RED_GAMMA_TABLE >> 8, HI_ADDR); 489 490 TGA2_WRITE_RAMDAC_REG (0x00, GAMMA_ADDR); 491 TGA2_WRITE_RAMDAC_REG (0x00, GAMMA_ADDR); 492 493 for ( i = 1; i <256; i++ ) { 494 TGA2_WRITE_RAMDAC_REG (0xff, GAMMA_ADDR); 495 TGA2_WRITE_RAMDAC_REG (0xff, GAMMA_ADDR); 496 } 497 498 TGA2_WRITE_RAMDAC_REG(IBM561_GREEN_GAMMA_TABLE, LO_ADDR); 499 TGA2_WRITE_RAMDAC_REG(IBM561_GREEN_GAMMA_TABLE >> 8, HI_ADDR); 500 501 TGA2_WRITE_RAMDAC_REG (0x00, GAMMA_ADDR); 502 TGA2_WRITE_RAMDAC_REG (0x00, GAMMA_ADDR); 503 504 for ( i = 1; i <256; i++ ) { 505 TGA2_WRITE_RAMDAC_REG (0xff, GAMMA_ADDR); 506 TGA2_WRITE_RAMDAC_REG (0xff, GAMMA_ADDR); 507 } 508 509 TGA2_WRITE_RAMDAC_REG(IBM561_BLUE_GAMMA_TABLE, LO_ADDR); 510 TGA2_WRITE_RAMDAC_REG(IBM561_BLUE_GAMMA_TABLE >> 8, HI_ADDR); 511 512 TGA2_WRITE_RAMDAC_REG (0x00, GAMMA_ADDR); 513 TGA2_WRITE_RAMDAC_REG (0x00, GAMMA_ADDR); 514 515 for ( i = 1; i <256; i++ ) { 516 TGA2_WRITE_RAMDAC_REG (0xff, GAMMA_ADDR); 517 TGA2_WRITE_RAMDAC_REG (0xff, GAMMA_ADDR); 518 } 519 520 521#if 0 522 /* ?? no cursor support yet */ 523 bti->cursor_fg.red = bti->cursor_fg.green = bti->cursor_fg.blue 524 = 0xffff; 525 bti->cursor_bg.red = bti->cursor_bg.green = bti->cursor_bg.blue 526 = 0x0000; 527 tga_ibm561_restore_cursor_color( closure, 0 ); 528#endif 529 530 return 0; 531} 532 533void 534IBM561ramdacHWInit(ScrnInfoPtr pScrn) 535{ 536 TGAPtr pTga = TGAPTR(pScrn); 537 538 unsigned int temp1[6] = {0,0,0,0,0,0}; 539 540 /* 541 * Set-up av9110 to 14.3 Mhz as reference for 561's PLL 542 */ 543 temp1[0] = 0x00000101; 544 temp1[1] = 0x01000000; 545 temp1[2] = 0x00000001; 546 temp1[3] = 0x00010000; 547 temp1[4] = 0x01010100; 548 temp1[5] = 0x01000000; 549 550 write_av9110(pScrn, temp1); 551 552 /* 553 * Initialize IBM561 RAMDAC 554 */ 555 IBM561WriteReg(pScrn, IBM561_CONFIG_REG_1, 0x2a ); 556 IBM561WriteReg(pScrn, IBM561_CONFIG_REG_3, 0x41 ); 557 IBM561WriteReg(pScrn, IBM561_CONFIG_REG_4, 0x20 ); 558 559/* IBM561WriteReg(pScrn, IBM561_PLL_VCO_DIV_REG, 0xc8 ); */ 560 IBM561WriteReg(pScrn, IBM561_PLL_VCO_DIV_REG, tga_c_table->ibm561_vco_div); 561 562/* IBM561WriteReg(pScrn, IBM561_PLL_REF_REG, 0x08 ); */ 563 IBM561WriteReg(pScrn, IBM561_PLL_REF_REG, tga_c_table->ibm561_ref ); 564 565 IBM561WriteReg(pScrn, IBM561_DIV_DOT_CLK_REG, 0xb0 ); 566 567 IBM561WriteReg(pScrn, IBM561_SYNC_CONTROL, 0x01 ); 568 569 IBM561WriteReg(pScrn, IBM561_CONFIG_REG_2, 0x19 ); 570 571 TGA_WRITE_REG(0xFFFFFFFF, TGA_PLANEMASK_REG); 572 573 /* Configure the RAMDAC, note registers not set either depend on the 574 * previous setting (ie what firmaware programmed to be) or what the 575 * X-server will set them to 576 */ 577 578 579 /* 580 * Config Register 1: MUX=4:1 BASIC, OVLY=8 bits, WID=8 bits (bits 4-7 of the 581 * overlay and window ID's are tied to ground in the hardware). 582 */ 583 IBM561WriteReg(pScrn, IBM561_CONFIG_REG_1, 0x2a ); 584 585 /* SKIP Config Register 2-3 (use Diag settings at least for now) */ 586 587 /* 588 * Config Register 4: FB_WID=4 bits, SWE=Common, AOW=LSB, AFW=LSB 589 */ 590 IBM561WriteReg(pScrn, IBM561_CONFIG_REG_4, 0x20 ); 591 592 /* 593 * SKIP Interleave Register (use Diag settings at least for now) 594 */ 595 TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR); 596 597 /* 598 * WAT/OL Segement Registers 599 */ 600 /* ?? we setup the address registers first, then stream the data out ?? */ 601 TGA2_WRITE_RAMDAC_REG(IBM561_WAT_SEG_REG, LO_ADDR); 602 TGA2_WRITE_RAMDAC_REG(IBM561_WAT_SEG_REG >> 8, HI_ADDR); 603 604 /* WAT Segment Register */ 605 TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR); 606 607 /* OL Segment Register */ 608 TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR); 609 610 /* AUX WAT Segment Register */ 611 TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR); 612 613 /* AUX OL Segment Register */ 614 TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR); 615 616 /* 617 * Chroma Key Registers and Masks 618 */ 619 /* ?? we setup the address registers first, then stream the data out ?? */ 620 TGA2_WRITE_RAMDAC_REG(IBM561_CHROMA_KEY_REG0, LO_ADDR); 621 TGA2_WRITE_RAMDAC_REG(IBM561_CHROMA_KEY_REG0 >> 8, HI_ADDR); 622 623 /* Chroma key register 0 */ 624 TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR); 625 626 /* Chroma key register 1 */ 627 TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR); 628 629 /* Chroma key mask register 0 */ 630 TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR); 631 632 /* Chroma key mask register 1 */ 633 TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR); 634 635 /* 636 * Cursor Control Register 637 */ 638 IBM561WriteReg(pScrn, IBM561_CURSOR_CTRL_REG, /*pScrn->cursor_on_off*/0); 639 640 /* 641 * Cursor Hot Spot X/Y Registers 642 */ 643 TGA2_WRITE_RAMDAC_REG(IBM561_CURSOR_HS_REG, LO_ADDR); 644 TGA2_WRITE_RAMDAC_REG(IBM561_CURSOR_HS_REG >> 8, HI_ADDR); 645 646 /* Cursor "x" Hot Spot Register */ 647 TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR); 648 649 /* Cursor "y" Hot Spot Register */ 650 TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR); 651 652 /* Cursor "x" Location Register (low byte) */ 653 TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR); 654 655 /* Cursor "x" Location Register (high byte) */ 656 TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR); 657 658 /* Cursor "y" Location Register (low byte) */ 659 TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR); 660 661 /* Cursor "y" Location Register (high byte) */ 662 TGA2_WRITE_RAMDAC_REG (0x00, REGS_ADDR); 663 664 /* 665 * VRAM Mask regs (used for diag purposes, reset them just in case) 666 */ 667 TGA2_WRITE_RAMDAC_REG(IBM561_VRAM_MASK_REG, LO_ADDR); 668 TGA2_WRITE_RAMDAC_REG(IBM561_VRAM_MASK_REG >> 8, HI_ADDR); 669 670 /* VRAM mask register 1 */ 671 TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR); 672 673 /* VRAM mask register 2 */ 674 TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR); 675 676 /* VRAM mask register 3 */ 677 TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR); 678 679 /* VRAM mask register 4 */ 680 TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR); 681 682 /* VRAM mask register 5 */ 683 TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR); 684 685 /* VRAM mask register 6 */ 686 TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR); 687 688 /* VRAM mask register 7 */ 689 TGA2_WRITE_RAMDAC_REG (0xff, REGS_ADDR); 690 691 /* Finally, do colormaps and windowtags */ 692 IBM561InitColormap(pScrn); 693 IBM561WindowTagsInit(pScrn); 694} 695 696void 697IBM561ramdacRestore(ScrnInfoPtr pScrn, unsigned char *Ibm561) 698{ 699#if 0 700 TGAPtr pTga = TGAPTR(pScrn); 701#endif 702 703#if 0 704 /* ?? finally the stock stuff ?? */ 705 int i, j; 706 /* ?? FIXME OR NOT this is currently copied from the BT463 */ 707 IBM561_WRITE(IBM561_REG_ACC, IBM561_CMD_REG_0, Ibm561[0]); 708 IBM561_WRITE(IBM561_REG_ACC, IBM561_CMD_REG_1, Ibm561[1]); 709 IBM561_WRITE(IBM561_REG_ACC, IBM561_CMD_REG_2, Ibm561[2]); 710 711 IBM561_WRITE(IBM561_REG_ACC, IBM561_READ_MASK_0, Ibm561[3]); 712 IBM561_WRITE(IBM561_REG_ACC, IBM561_READ_MASK_1, Ibm561[4]); 713 IBM561_WRITE(IBM561_REG_ACC, IBM561_READ_MASK_2, Ibm561[5]); 714 IBM561_WRITE(IBM561_REG_ACC, IBM561_READ_MASK_3, Ibm561[6]); 715 716 IBM561_WRITE(IBM561_REG_ACC, IBM561_BLINK_MASK_0, Ibm561[7]); 717 IBM561_WRITE(IBM561_REG_ACC, IBM561_BLINK_MASK_1, Ibm561[8]); 718 IBM561_WRITE(IBM561_REG_ACC, IBM561_BLINK_MASK_2, Ibm561[9]); 719 IBM561_WRITE(IBM561_REG_ACC, IBM561_BLINK_MASK_3, Ibm561[10]); 720 721 IBM561_LOAD_ADDR(IBM561_WINDOW_TYPE_BASE); 722 TGA_WRITE_REG((IBM561_REG_ACC<<2), TGA_RAMDAC_SETUP_REG); 723 724 for (i = 0, j = 11; i < 16; i++) { 725 TGA_WRITE_REG(Ibm561[j++]|(IBM561_REG_ACC<<10), TGA_RAMDAC_REG); 726 TGA_WRITE_REG(Ibm561[j++]|(IBM561_REG_ACC<<10), TGA_RAMDAC_REG); 727 TGA_WRITE_REG(Ibm561[j++]|(IBM561_REG_ACC<<10), TGA_RAMDAC_REG); 728 } 729#endif 730 731/* 732 fprintf(stderr, "IBM561ramdacRestore (%p)\n", Ibm561); 733 for (i=0; i<58; i++) 734 fprintf(stderr, "%2d: 0x%02x\n", i, (unsigned)Ibm561[i]); 735*/ 736 737} 738 739