tga_regs.h revision 7706df26 
1/*
2 * Copyright 1997,1998 by Alan Hourihane, Wigan, England.
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that
7 * copyright notice and this permission notice appear in supporting
8 * documentation, and that the name of Alan Hourihane not be used in
9 * advertising or publicity pertaining to distribution of the software without
10 * specific, written prior permission.  Alan Hourihane makes no representations
11 * about the suitability of this software for any purpose.  It is provided
12 * "as is" without express or implied warranty.
13 *
14 * ALAN HOURIHANE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL ALAN HOURIHANE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
20 * PERFORMANCE OF THIS SOFTWARE.
21 *
22 * Author:  Alan Hourihane, <alanh@fairlite.demon.co.uk>
23 */
24/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/tga/tga_regs.h,v 1.11 2000/10/20 12:57:26 alanh Exp $ */
25
26/* TGA hardware description (minimal)
27 *
28 * Offsets within Memory Space
29 *
30 * Portions taken from linux's own tga driver...
31 * Courtesy of Jay Estabrook.
32 */
33
34#ifndef TGA_REGS_H
35#define TGA_REGS_H
36
37#include "compiler.h"
38
39#define TYPE_TGA_8PLANE			0
40#define TYPE_TGA_24PLANE		1
41#define TYPE_TGA_24PLUSZ		3
42
43#if 1
44#define WMB	mem_barrier()
45#else
46#define WMB	write_mem_barrier()
47#endif
48
49#define TGA_WRITE_REG(v,r) \
50	do {\
51		 *(unsigned int *)((char*)(pTga->IOBase)+(r)) = (v);\
52		 WMB;\
53	} while (0)
54
55#define TGA_READ_REG(r) \
56	( *(unsigned int *)((char*)(pTga->IOBase)+(r)))
57
58#define TGA2_WRITE_CLOCK_REG(v,r) \
59	do {\
60		 *(unsigned int *)((char*)(pTga->ClkBase)+(r)) = (v);\
61		 WMB;\
62	} while (0)
63
64#define TGA2_WRITE_RAMDAC_REG(v,r) \
65	do {\
66		 *(unsigned int *)((char*)(pTga->DACBase)+(r)) = (v);\
67		 WMB;\
68	} while (0)
69
70#define TGA2_READ_RAMDAC_REG(r) \
71	( *(unsigned int *)((char*)(pTga->DACBase)+(r)))
72
73#if defined(__alpha__) && 0 /* ?? disable this for now ?? */
74/* we can avoid an mb() if we write to an alternate register space each time */
75
76#define MAX_OFFSET 8192
77#define OFFSET_INC 1024
78
79#define TGA_DECL() register unsigned long iobase, offset
80#define TGA_GET_IOBASE() iobase = (unsigned long)pTga->IOBase;
81#define TGA_GET_OFFSET() offset = pTga->regOffset;
82#define TGA_SAVE_OFFSET() pTga->regOffset = offset;
83
84/* #define PROFILE */
85#undef PROFILE
86
87#ifdef PROFILE
88static __inline__ unsigned int realcc()
89{
90  u_long cc;
91  __asm__ volatile("rpcc %0" : "=r"(cc) : : "memory");
92  return cc;
93}
94
95#define TGA_FAST_WRITE_REG(v,r) \
96do {\
97start = realcc();\
98  *(unsigned int *)(iobase + offset + (r)) = v;\
99  offset += OFFSET_INC;\
100  if(offset > MAX_OFFSET) (offset = 0);\
101  stop = realcc();\
102  ErrorF("TGA_FAST_WRITE_REG = %d\n", stop - start);\
103} while (0)
104
105#else /* PROFILE */
106
107#define TGA_FAST_WRITE_REG(v,r) \
108do {\
109  *(unsigned int *)(iobase + offset + (r)) = v;\
110  offset += OFFSET_INC;\
111  if(offset > MAX_OFFSET) (offset = 0);\
112} while (0)
113#endif /* PROFILE */
114
115#else /* __alpha__ */
116
117#define TGA_DECL()
118#define TGA_GET_IOBASE() ;
119#define TGA_GET_OFFSET() ;
120#define TGA_SAVE_OFFSET() ;
121#define TGA_FAST_WRITE_REG(v,r) TGA_WRITE_REG(v,r)
122
123#endif /* __alpha__ */
124
125#define	TGA_ROM_OFFSET			0x00000000
126#define TGA2_CLOCK_OFFSET		0x00060000
127#define TGA2_RAMDAC_OFFSET		0x00080000
128#define	TGA_REGS_OFFSET			0x00100000
129#define	TGA_8PLANE_FB_OFFSET		0x00200000
130#define	TGA_24PLANE_FB_OFFSET		0x00800000
131#define	TGA_24PLUSZ_FB_OFFSET		0x01000000
132
133#define TGA_FOREGROUND_REG		0x0020
134#define TGA_BACKGROUND_REG		0x0024
135#define	TGA_PLANEMASK_REG		0x0028
136#define	TGA_MODE_REG			0x0030
137#define		SIMPLE			0x00
138#define		Z3D			0x10
139#define		OPAQUESTIPPLE		0x01
140#define		FILL			0x20
141#define		TRANSPARENTSTIPPLE	0x05
142#define		BLOCKSTIPPLE		0x0D
143#define		BLOCKFILL		0x2D
144#define		OPAQUELINE		0x02
145#define		TRANSPARENTLINE		0x06
146#define		BPP8PACKED		(0x00 << 8)
147#define		BPP8UNPACK		(0x01 << 8)
148#define		BPP12LOW		(0x02 << 8)
149#define		BPP12HIGH		(0x06 << 8)
150#define		BPP24			(0x03 << 8)
151#define		CAP_ENDS		0x8000
152#define		X11			0x0000
153#define		MODE_WIN32		0x2000
154 /* copy mode */
155#define         COPY                    0x07
156 /* opaque fill mode */
157#define         OPAQUEFILL              0x21
158#define         TRANSPARENTFILL         0x45
159#define	TGA_RASTEROP_REG		0x0034
160#define TGA_PIXELSHIFT_REG              0x0038
161#define TGA_ADDRESS_REG			0x003c
162#define TGA_CONTINUE_REG                0x004c
163#define	TGA_DEEP_REG			0x0050
164#define	TGA_REVISION_REG		0x0054		/* TGA2 */
165#define	TGA_PIXELMASK_REG		0x002c
166#define	TGA_PIXELMASK_PERS_REG		0x005c
167#define	TGA_CURSOR_BASE_REG		0x0060
168#define	TGA_HORIZ_REG			0x0064
169#define	TGA_VERT_REG			0x0068
170#define	TGA_BASE_ADDR_REG		0x006c
171#define	TGA_VALID_REG			0x0070
172#define	TGA_CURSOR_XY_REG		0x0074
173#define	TGA_INTR_STAT_REG		0x007c
174 /* GDAR */
175#define TGA_DATA_REG                    0x0080
176#define TGA_WIDTH_REG                   0x009c
177#define TGA_SPAN_REG			0x00bc
178#define	TGA_RAMDAC_SETUP_REG		0x00c0
179
180#define TGA_NOSLOPE7_REG                0x011C
181#define TGA_NOSLOPE6_REG                0x0118
182#define TGA_NOSLOPE5_REG                0x0114
183#define TGA_NOSLOPE4_REG                0x0110
184#define TGA_NOSLOPE3_REG                0x010C
185#define TGA_NOSLOPE2_REG                0x0108
186#define TGA_NOSLOPE1_REG                0x0104
187#define TGA_NOSLOPE0_REG                0x0100
188
189#define TGA_SLOPE0_REG                  0x0120
190#define TGA_SLOPE1_REG                  0x0124
191#define TGA_SLOPE2_REG                  0x0128
192#define TGA_SLOPE3_REG                  0x012C
193#define TGA_SLOPE4_REG                  0x0130
194#define TGA_SLOPE5_REG                  0x0134
195#define TGA_SLOPE6_REG                  0x0138
196#define TGA_SLOPE7_REG                  0x013C
197#define TGA_BRES3_REG                   0x0048
198#define TGA_BRES2_REG                   0x0044
199#define TGA_BRES1_REG                   0x0040
200
201#define	TGA_BLOCK_COLOR0_REG		0x0140
202#define	TGA_BLOCK_COLOR1_REG		0x0144
203#define	TGA_BLOCK_COLOR2_REG		0x0148
204#define	TGA_BLOCK_COLOR3_REG		0x014c
205#define	TGA_BLOCK_COLOR4_REG		0x0150
206#define	TGA_BLOCK_COLOR5_REG		0x0154
207#define	TGA_BLOCK_COLOR6_REG		0x0158
208#define	TGA_BLOCK_COLOR7_REG		0x015c
209#define	TGA_CLOCK_REG			0x01e8
210#define	TGA_RAMDAC_REG			0x01f0
211#define	TGA_CMD_STAT_REG		0x01f8
212
213#define	BT485_READ_BIT			0x01
214#define	BT485_WRITE_BIT			0x00
215
216#endif
217