README revision 1.1
1 2 Copyright (C) 1999-2002 VMware, Inc. 3 All Rights Reserved 4 5 The code here may be used/distributed under the terms of the standard 6 XFree86 license. 7 8 9 VMware SVGA Device Interface and Programming Model 10 -------------------------------------------------- 11 12 13 Include Files 14 ------------- 15 16 svga_reg.h 17 SVGA register definitions, SVGA capabilities, and FIFO command definitions. 18 19 svga_limits.h 20 Included by svga_reg.h, defines maximum frame buffer and memory region 21 sizes. 22 23 svga_modes.h 24 A list of default display modes that are built into the driver. 25 26 svga_overlay.h 27 A list of definitions required for Xv extension support. Included by vmwarevideo.c 28 29 svga_escape.h 30 A list of definitions for the SVGA Escape commands. 31 32 guest_os.h 33 Values for the GUEST_ID register. 34 35 vm_basic_types.h 36 Common type definitions. 37 38 vm_device_version.h 39 PCI vendor ID's and related information. 40 41 vmwarectrl.h 42 vmwarectrlproto.h 43 The definitions of the VMWARECTRL protocol extension. 44 45 Programming the VMware SVGA Device 46 ---------------------------------- 47 48 1. Reading/writing a register: 49 50 The SVGA registers are addressed by an index/value pair of 32 bit 51 registers in the IO address space. 52 53 The 0710 VMware SVGA chipset (PCI device ID PCI_DEVICE_ID_VMWARE_SVGA) has 54 its index and value ports hardcoded at: 55 56 index: SVGA_LEGACY_BASE_PORT + 4 * SVGA_INDEX_PORT 57 value: SVGA_LEGACY_BASE_PORT + 4 * SVGA_VALUE_PORT 58 59 The 0405 VMware SVGA chipset (PCI device ID PCI_DEVICE_ID_VMWARE_SVGA2) 60 determines its index and value ports as a function of the first base 61 address register in its PCI configuration space as: 62 63 index: <Base Address Register 0> + SVGA_INDEX_PORT 64 value: <Base Address Register 0> + SVGA_VALUE_PORT 65 66 To read a register: 67 Set the index port to the index of the register, using a dword OUT 68 Do a dword IN from the value port 69 70 To write a register: 71 Set the index port to the index of the register, using a dword OUT 72 Do a dword OUT to the value port 73 74 Example, setting the width to 1024: 75 76 mov eax, SVGA_REG_WIDTH 77 mov edx, <SVGA Address Port> 78 out dx, eax 79 mov eax, 1024 80 mov edx, <SVGA Value Port> 81 out dx, eax 82 83 2. Initialization 84 Check the version number 85 loop: 86 Write into SVGA_REG_ID the maximum SVGA_ID_* the driver supports. 87 Read from SVGA_REG_ID. 88 Check if it is the value you wrote. 89 If yes, VMware SVGA device supports it 90 If no, decrement SVGA_ID_* and goto loop 91 This algorithm converges. 92 93 Map the frame buffer and the command FIFO 94 Read SVGA_REG_FB_START, SVGA_REG_FB_SIZE, SVGA_REG_MEM_START, 95 SVGA_REG_MEM_SIZE. 96 Map the frame buffer (FB) and the FIFO memory (MEM) 97 98 Get the device capabilities and frame buffer dimensions 99 Read SVGA_REG_CAPABILITIES, SVGA_REG_MAX_WIDTH, SVGA_REG_MAX_HEIGHT, 100 and SVGA_REG_HOST_BITS_PER_PIXEL / SVGA_REG_BITS_PER_PIXEL. 101 102 Note: The capabilities can and do change without the PCI device ID 103 changing or the SVGA_REG_ID changing. A driver should always check 104 the capabilities register when loading before expecting any 105 capabilities-determined feature to be available. See below for a list 106 of capabilities as of this writing. 107 108 Note: If SVGA_CAP_8BIT_EMULATION is not set, then it is possible that 109 SVGA_REG_HOST_BITS_PER_PIXEL does not exist and 110 SVGA_REG_BITS_PER_PIXEL should be read instead. 111 112 Report the Guest Operating System 113 Write SVGA_REG_GUEST_ID with the appropriate value from <guest_os.h>. 114 While not required in any way, this is useful information for the 115 virtual machine to have available for reporting and sanity checking 116 purposes. 117 118 SetMode 119 Set SVGA_REG_WIDTH, SVGA_REG_HEIGHT, SVGA_REG_BITS_PER_PIXEL 120 Read SVGA_REG_FB_OFFSET 121 (SVGA_REG_FB_OFFSET is the offset from SVGA_REG_FB_START of the 122 visible portion of the frame buffer) 123 Read SVGA_REG_BYTES_PER_LINE, SVGA_REG_DEPTH, SVGA_REG_PSEUDOCOLOR, 124 SVGA_REG_RED_MASK, SVGA_REG_GREEN_MASK, SVGA_REG_BLUE_MASK 125 126 Note: SVGA_REG_BITS_PER_PIXEL is readonly if 127 SVGA_CAP_8BIT_EMULATION is not set in the capabilities register. Even 128 if it is set, values other than 8 and SVGA_REG_HOST_BITS_PER_PIXEL 129 will be ignored. 130 131 Enable SVGA 132 Set SVGA_REG_ENABLE to 1 133 (to disable SVGA, set SVGA_REG_ENABLE to 0. Setting SVGA_REG_ENABLE 134 to 0 also enables VGA.) 135 136 Initialize the command FIFO 137 The FIFO is exclusively dword (32-bit) aligned. The first four 138 dwords define the portion of the MEM area that is used for the 139 command FIFO. These are values are all in byte offsets from the 140 start of the MEM area. 141 142 A minimum sized FIFO would have these values: 143 mem[SVGA_FIFO_MIN] = 16; 144 mem[SVGA_FIFO_MAX] = 16 + (10 * 1024); 145 mem[SVGA_FIFO_NEXT_CMD] = 16; 146 mem[SVGA_FIFO_STOP] = 16; 147 148 Set SVGA_REG_CONFIG_DONE to 1 after these values have been set. 149 150 Note: Setting SVGA_REG_CONFIG_DONE to 0 will stop the device from 151 reading the FIFO until it is reinitialized and SVGA_REG_CONFIG_DONE is 152 set to 1 again. 153 154 3. SVGA command FIFO protocol 155 The FIFO is empty when SVGA_FIFO_NEXT_CMD == SVGA_FIFO_STOP. The 156 driver writes commands to the FIFO starting at the offset specified 157 by SVGA_FIFO_NEXT_CMD, and then increments SVGA_FIFO_NEXT_CMD. 158 159 The FIFO is full when SVGA_FIFO_NEXT_CMD is one word before SVGA_FIFO_STOP. 160 161 When the FIFO becomes full, the FIFO should be sync'd 162 163 To sync the FIFO 164 Write SVGA_REG_SYNC 165 Read SVGA_REG_BUSY 166 Wait for the value in SVGA_REG_BUSY to be 0 167 168 The FIFO should be sync'd before the driver touches the frame buffer, to 169 guarantee that any outstanding BLT's are completed. 170 171 4. Cursor 172 When SVGA_CAP_CURSOR is set, hardware cursor support is available. In 173 practice, SVGA_CAP_CURSOR will only be set when SVGA_CAP_CURSOR_BYPASS is 174 also set and drivers supporting a hardware cursor should only worry about 175 SVGA_CAP_CURSOR_BYPASS and only use the FIFO to define the cursor. See 176 below for more information. 177 178 5. Pseudocolor 179 When the read-only register SVGA_REG_PSEUDOCOLOR is 1, the device is in a 180 colormapped mode whose index width and color width are both SVGA_REG_DEPTH. 181 Thus far, 8 is the only depth at which pseudocolor is ever used. 182 183 In pseudocolor, the colormap is programmed by writing to the SVGA palette 184 registers. These start at SVGA_PALETTE_BASE and are interpreted as 185 follows: 186 187 SVGA_PALETTE_BASE + 3*n - The nth red component 188 SVGA_PALETTE_BASE + 3*n + 1 - The nth green component 189 SVGA_PALETTE_BASE + 3*n + 2 - The nth blue component 190 191 And n ranges from 0 to ((1<<SVGA_REG_DEPTH) - 1). 192 193 194 Drawing to the Screen 195 --------------------- 196 197 After initialization, the driver can write directly to the frame buffer. The 198 updated frame buffer is not displayed immediately, but only when an update 199 command is sent. The update command (SVGA_CMD_UPDATE) defines the rectangle 200 in the frame buffer that has been modified by the driver, and causes that 201 rectangle to be updated on the screen. 202 203 A complete driver can be developed this way. For increased performance, 204 additional commands are available to accelerate common operations. The two 205 most useful are SVGA_CMD_RECT_FILL and SVGA_CMD_RECT_COPY. 206 207 After issuing an accelerated command, the FIFO should be sync'd, as described 208 above, before writing to the frame buffer. 209 210 Addendum on 7/11/2000 211 --------------------- 212 213 SVGA_REG_FB_OFFSET and SVGA_REG_BYTES_PER_LINE may change after SVGA_REG_WIDTH 214 or SVGA_REG_HEIGHT is set. Also the VGA registers must be written to after 215 setting SVGA_REG_ENABLE to 0 to change the display to a VGA mode. 216 217 Addendum on 11/29/2001 218 --------------------- 219 220 Actually, after changing any of SVGA_REG_WIDTH, SVGA_REG_HEIGHT, and 221 SVGA_REG_BITS_PER_PIXEL, all of the registers listed in the 'SetMode' 222 initialization section above should be reread. Additionally, when changing 223 modes, it can be convenient to set SVGA_REG_ENABLE to 0, change 224 SVGA_REG_WIDTH, SVGA_REG_HEIGHT, and SVGA_REG_BITS_PER_PIXEL (if available), 225 and then set SVGA_REG_ENABLE to 1 again. 226 227 228 Capabilities 229 ------------ 230 231 The capabilities register (SVGA_REG_CAPABILITIES) is an array of bits that 232 indicates the capabilities of the SVGA emulation. A driver should check 233 SVGA_REG_CAPABILITIES every time it loads before relying on any feature that 234 is only optionally available. 235 236 Some of the capabilities determine which FIFO commands are available. This 237 table shows which capability indicates support for which command. 238 239 FIFO Command Capability 240 ------------ ---------- 241 242 SVGA_CMD_RECT_FILL SVGA_CAP_RECT_FILL 243 SVGA_CMD_RECT_COPY SVGA_CAP_RECT_COPY 244 SVGA_CMD_DEFINE_BITMAP SVGA_CAP_OFFSCREEN 245 SVGA_CMD_DEFINE_BITMAP_SCANLINE SVGA_CAP_OFFSCREEN 246 SVGA_CMD_DEFINE_PIXMAP SVGA_CAP_OFFSCREEN 247 SVGA_CMD_DEFINE_PIXMAP_SCANLINE SVGA_CAP_OFFSCREEN 248 SVGA_CMD_RECT_BITMAP_FILL SVGA_CAP_RECT_PAT_FILL 249 SVGA_CMD_RECT_PIXMAP_FILL SVGA_CAP_RECT_PAT_FILL 250 SVGA_CMD_RECT_BITMAP_COPY SVGA_CAP_RECT_PAT_FILL 251 SVGA_CMD_RECT_PIXMAP_COPY SVGA_CAP_RECT_PAT_FILL 252 SVGA_CMD_FREE_OBJECT SVGA_CAP_OFFSCREEN 253 SVGA_CMD_RECT_ROP_FILL SVGA_CAP_RECT_FILL + 254 SVGA_CAP_RASTER_OP 255 SVGA_CMD_RECT_ROP_COPY SVGA_CAP_RECT_COPY + 256 SVGA_CAP_RASTER_OP 257 SVGA_CMD_RECT_ROP_BITMAP_FILL SVGA_CAP_RECT_PAT_FILL + 258 SVGA_CAP_RASTER_OP 259 SVGA_CMD_RECT_ROP_PIXMAP_FILL SVGA_CAP_RECT_PAT_FILL + 260 SVGA_CAP_RASTER_OP 261 SVGA_CMD_RECT_ROP_BITMAP_COPY SVGA_CAP_RECT_PAT_FILL + 262 SVGA_CAP_RASTER_OP 263 SVGA_CMD_RECT_ROP_PIXMAP_COPY SVGA_CAP_RECT_PAT_FILL + 264 SVGA_CAP_RASTER_OP 265 SVGA_CMD_DEFINE_CURSOR SVGA_CAP_CURSOR 266 SVGA_CMD_DISPLAY_CURSOR SVGA_CAP_CURSOR 267 SVGA_CMD_MOVE_CURSOR SVGA_CAP_CURSOR 268 SVGA_CMD_DEFINE_ALPHA_CURSOR SVGA_CAP_ALPHA_CURSOR 269 SVGA_CMD_DRAW_GLYPH SVGA_CAP_GLYPH 270 SVGA_CMD_DRAW_GLYPH_CLIPPED SVGA_CAP_GLYPH_CLIPPING 271 SVGA_CMD_ESCAPE SVGA_FIFO_CAP_ESCAPE 272 273 Note: SVGA_CMD_DISPLAY_CURSOR and SVGA_CMD_MOVE_CURSOR should not be used. 274 Drivers wishing hardware cursor support should use cursor bypass (see below). 275 276 Other capabilities indicate other functionality as described below: 277 278 SVGA_CAP_CURSOR_BYPASS 279 The hardware cursor can be drawn via SVGA Registers (without requiring 280 the FIFO be synchronized and will be drawn potentially before any 281 outstanding unprocessed FIFO commands). 282 283 Note: Without SVGA_CAP_CURSOR_BYPASS_2, cursors drawn this way still 284 appear in the guest's framebuffer and need to be turned off before any 285 save under / overlapping drawing and turned back on after. This can 286 cause very noticeable cursor flicker. 287 288 SVGA_CAP_CURSOR_BYPASS_2 289 Instead of turning the cursor off and back on around any overlapping 290 drawing, the driver can write SVGA_CURSOR_ON_REMOVE_FROM_FB and 291 SVGA_CURSOR_ON_RESTORE_TO_FB to SVGA_REG_CURSOR_ON. In almost all 292 cases these are NOPs and the cursor will be remain visible without 293 appearing in the guest framebuffer. In 'direct graphics' modes like 294 Linux host fullscreen local displays, however, the cursor will still 295 be drawn in the framebuffer, still flicker, and be drawn incorrectly 296 if a driver does not use SVGA_CURSOR_ON_REMOVE_FROM_FB / RESTORE_TO_FB. 297 298 SVGA_CAP_8BIT_EMULATION 299 SVGA_REG_BITS_PER_PIXEL is writable and can be set to either 8 or 300 SVGA_REG_HOST_BITS_PER_PIXEL. Otherwise the only SVGA modes available 301 inside a virtual machine must match the host's bits per pixel. 302 303 Note: Some versions which lack SVGA_CAP_8BIT_EMULATION also lack the 304 SVGA_REG_HOST_BITS_PER_PIXEL and a driver should assume 305 SVGA_REG_BITS_PER_PIXEL is both read-only and initialized to the only 306 available value if SVGA_CAP_8BIT_EMULATION is not set. 307 308 SVGA_CAP_OFFSCREEN_1 309 SVGA_CMD_RECT_FILL, SVGA_CMD_RECT_COPY, SVGA_CMD_RECT_ROP_FILL, 310 SVGA_CMD_RECT_ROP_COPY can operate with a source or destination (or 311 both) in offscreen memory. 312 313 Usable offscreen memory is a rectangle located below the last scanline 314 of the visible memory: 315 x1 = 0 316 y1 = (SVGA_REG_FB_SIZE + SVGA_REG_BYTES_PER_LINE - 1) / 317 SVGA_REG_BYTES_PER_LINE 318 x2 = SVGA_REG_BYTES_PER_LINE / SVGA_REG_DEPTH 319 y2 = SVGA_REG_VRAM_SIZE / SVGA_REG_BYTES_PER_LINE 320 321 322 Cursor Handling 323 --------------- 324 325 Starting with GSX Server Beta 3 (after 11/15/2000), hardware cursor support 326 was added. Actually, both a hardware cursor via the FIFO (SVGA_CAP_CURSOR) 327 and a hardware cursor via the SVGA registers (SVGA_CAP_CURSOR_BYPASS) were 328 added. SVGA_CAP_CURSOR was never available without SVGA_CAP_CURSOR_BYPASS and 329 the FIFO hardware cursor should never be used and may be removed without 330 warning in the future. 331 332 Cursor bypass is programmed using the two FIFO commands SVGA_CMD_DEFINE_CURSOR 333 and SVGA_CMD_DEFINE_ALPHA_CURSOR in conjunction with the SVGA registers 334 SVGA_REG_CURSOR_ID, SVGA_REG_CURSOR_X, SVGA_REG_CURSOR_Y, and 335 SVGA_REG_CURSOR_ON. 336 337 A driver defines an AND/XOR hardware cursor using SVGA_CMD_DEFINE_CURSOR to 338 assign an ID and establish the AND and XOR masks with the hardware. A driver 339 uses SVGA_CMD_DEFINE_ALPHA_CURSOR to define a 32 bit mask whose top 8 bits are 340 used to blend the cursor image with the pixels it covers. Alpha cursor 341 support is only available when SVGA_CAP_ALPHA_CURSOR is set. 342 343 Once a cursor is defined, a driver can draw it to the screen at any time by 344 writing the SVGA_REG_CURSOR_ID register with the ID used when the cursor was 345 defined, writing SVGA_REG_CURSOR_X and SVGA_REG_CURSOR_Y with the location of 346 the cursor, and SVGA_CURSOR_ON_SHOW to SVGA_REG_CURSOR_ON. The drawing occurs 347 when SVGA_REG_CURSOR_ON is written. 348 349 Writing SVGA_CURSOR_ON_HIDE to SVGA_REG_CURSOR_ON will turn the cursor off and 350 make it vanish from the display and, if present, from the framebuffer. 351 SVGA_CURSOR_ON_REMOVE_FROM_FB will ensure the cursor is not in the 352 framebuffer, but will only turn it off if there's no other way to remove it. 353 SVGA_CURSOR_ON_RESTORE_TO_FB is the complement to 354 SVGA_CURSOR_ON_REMOVE_FROM_FB. Whenever possible, the device will not put the 355 cursor in the framebuffer and Remove From / Restore To will be NOPs. 356 357 Note: The cursor must be out of the frame buffer before the driver (or any 358 agent in the virtual machine) touches an overlapping portion of the frame 359 buffer, because it is actually drawn into the frame buffer memory in the 360 case of direct graphics mode (e.g. full screen mode on Linux). The cursor 361 does not have to be touched before issuing an accelerated command via the 362 command FIFO, this case is handled by the SVGA device. 363 364 Note: If SVGA_CAP_CURSOR_BYPASS2 is not present, the driver must use 365 SVGA_CURSOR_ON_HIDE and SVGA_CURSOR_ON_HIDE to be certain the cursor is out of 366 the framebuffer. 367 368 369 Driver Version Numbers 370 ---------------------- 371 372 The SVGA drivers use the following convention for their version numbers: 373 374 Version 10.0 - The first version that uses the FIFO 375 Version 10.1 - The version that uses the hardware cursor emulation via the FIFO 376 Version 10.2 - The version that uses the cursor that bypasses the FIFO 377 Version 10.3 - The version that can also support the 0405 chipset 378 Version 10.4 - The version that knows about SVGA_CAP_CURSOR_BYPASS2 379 Version 10.5 - [Never released or well defined] 380 Version 10.6 - The version that knows about SVGA_CAP_8BIT_EMULATION 381 Version 10.7 - The version that knows about SVGA_CAP_ALPHA_CURSOR 382 Version 10.8 - The version that knows about SVGA_CAP_GLYPH 383 Version 10.9 - The version that knows about SVGA_CAP_OFFSCREEN_1 384 385 Note that this is merely the convention used by SVGA drivers written and 386 maintained by VMware, Inc. and describes the capabilities of the driver, not 387 the virtual hardware. An SVGA driver can only use the intersection of the 388 functionality it supports and the functionality available in the virtual SVGA 389 hardware. 390 391 392 Frequently Asked Questions 393 -------------------------- 394 395 1. My driver doesn't display anything, what's going on? 396 397 First check if you are issuing an SVGA_CMD_UPDATE after drawing to 398 the screen. Another check you can do is to run your driver in full 399 screen mode on a Linux host. In this case you are drawing directly 400 on the frame buffer, so what you draw to the screen will be immediately 401 visible. If nothing is visible in this case, then most likely your 402 driver hasn't mapped the frame buffer correctly. 403 404 A discrepancy between what you get in full screen mode and what you 405 get in window mode indicates that you have a missing or incorrect 406 update command. 407 408 409 2. What's the difference between bitmaps and pixmaps? 410 411 Pixmaps have the same depth as the screen, while bitmaps have depth one. 412 When a bitmap is drawn, the command also takes two colors, foreground and 413 background. The set bits in the bitmap are replaced with the foreground 414 color, and the unset bits are replaced with the background color. 415 416 Pixmaps, on the other hand, can be directly copied to the screen. 417 418 419 3. What's the significance of the ROP in the commands SVGA_CMD_RECT_ROP_FILL, 420 SVGA_CMD_RECT_ROP_BITMAP_COPY, etc. ? 421 422 The ROP in the ...ROP... commands is a raster operation. It has the same 423 significance (and encoding) as it does in X. The ROP value SVGA_ROP_COPY 424 means the source is copied to the destination, which makes these commands the 425 same as their non-ROP counterparts. The most commonly used raster operation 426 other than copy is probably SVGA_ROP_XOR, which combines the source and 427 destination using exclusive-or. 428 429 430 4. Tell me more about bitmaps and pixmaps. For example, the macro 431 SVGA_CMD_DEFINE_BITMAP has a field <scanlines>. What should this be 432 set to? Likewise with SVGA_CMD_DEFINE_PIXMAP. And when should the 433 SCANLINE macros be used? 434 435 OK, I'll use pixmaps as an example. First you have to define the pixmap: 436 437 #define SVGA_CMD_DEFINE_PIXMAP 6 438 /* FIFO layout: 439 Pixmap ID, Width, Height, Depth, <scanlines> */ 440 441 The ID is something you choose, which you subsequently use to refer to 442 this pixmap. It must be an integer between 0 and SVGA_MAX_ID. 443 444 The width and height and depth are the dimensions of the pixmap. For now, 445 the depth of the pixmap has to match the depth of the screen. 446 447 The scanlines are the pixels that make up the pixmap, arranged one row 448 at a time. Each row is required to be 32-bit aligned. The macros 449 SVGA_PIXMAP_SCANLINE_SIZE and SVGA_PIXMAP_SIZE give the size of a 450 single scanline, and the size of the entire pixmap, respectively, in 451 32-bit words. 452 453 The second step is to use it: 454 455 #define SVGA_CMD_RECT_PIXMAP_FILL 9 456 /* FIFO layout: 457 Pixmap ID, X, Y, Width, Height */ 458 459 The ID here is the one you chose when defining the pixmap. X, Y, 460 Width, and Height define a rectangle on the screen that is to be filled 461 with the pixmap. The pixmap is screen aligned, which means that the 462 coordinates in the pixmap are defined by the screen coordinates modulo 463 the pixmap dimensions. 464 465 If you want a different alignment between the screen and the pixmap, 466 then you can use this command, which allows the pixmap coordinates to 467 be defined: 468 469 #define SVGA_CMD_RECT_PIXMAP_COPY 11 470 /* FIFO layout: 471 Pixmap ID, Source X, Source Y, Dest X, Dest Y, Width, 472 Height */ 473 474 The Source X and Source Y are pixmap coordinates, and the Dest X and 475 Dest Y are screen coordinates. 476 477 478 5. OK, now it works briefly, then stops displaying anything. Also, 479 my log file is filled with lines like: 480 Unknown Command 0xff in SVGA command FIFO 481 What's happening? 482 483 The most common problem at this point is that the FIFO gets out 484 of sync. This can happen if the amount of data in the FIFO doesn't 485 match what the VMware SVGA device expects. To track this down, try 486 to isolate the particular command which causes the problem. 487 488 Another way this can happen is if the wraparound in the FIFO isn't 489 done correctly. Here is some example code for writing to the FIFO 490 (mem is an array of 32-bit integers that points to the FIFO memory 491 region): 492 493 while (TRUE) { 494 fifo_min = mem[SVGA_FIFO_MIN] / 4; 495 fifo_max = mem[SVGA_FIFO_MAX] / 4; 496 fifo_next = mem[SVGA_FIFO_NEXT_CMD] / 4; 497 fifo_stop = mem[SVGA_FIFO_STOP] / 4; 498 499 tmp_next = fifo_next+1; 500 if (tmp_next == fifo_max) 501 tmp_next = fifo_min; // Wraparound 502 503 if (tmp_next == fifo_stop) { 504 sync_fifo(); // FIFO full 505 continue; // retry 506 } 507 508 mem[fifo_next] = item; 509 mem[SVGA_FIFO_NEXT_CMD] = tmp_next * 4; 510 break; 511 } 512 513 This isn't the most efficient code, but it should work. It's important 514 to do the increment with wraparound before the FIFO full check, and to 515 check FIFO full before updating the next command pointer. 516 517 518 6. My driver tries to switch modes and either nothing happens or the 519 display becomes completely garbled. What's going on? 520 521 When you change modes, make very sure you reread all of the registers listed 522 above under SetMode. Getting the pitch (SVGA_REG_BYTES_PER_LINE) incorrect 523 will cause a heavily garbled display. Also, if you change 524 SVGA_REG_BITS_PER_PIXEL, make certain that SVGA_CAP_8BIT_EMULATION is present 525 in the SVGA_REG_CAPABILITIES register. Also, even with 8 bit emulation, the 526 driver must still use either 8 bpp or SVGA_REG_HOST_BITS_PER_PIXEL bpp, 527 nothing else. 528 529 530 7. Why does my driver's hardware cursor work when my virtual machine is in 531 window mode, but draw/erase incorrectly or in garbled locations in fullscreen 532 mode? 533 534 You need to make sure you use SVGA_CURSOR_ON_REMOVE_FROM_FB and 535 SVGA_CURSOR_ON_RESTORE_TO_FB _every_ time your driver or the virtual machine 536 touches a region of the framebuffer that overlaps the cursor. If you forget 537 to remove it then it can show up when doing save-under operations or get mixed 538 in with other drawing. If you forget to restore it then can disappear. You 539 also need to make sure SVGA_CAP_CURSOR_BYPASS2 is available, or else you will 540 have to use SVGA_CURSOR_ON_SHOW and SVGA_CURSOR_ON_HIDE (which will flicker, 541 even in window mode), or else a software cursor. Newer version of the virtual 542 SVGA hardware will never put the hardware cursor in the framebuffer while in 543 window mode, so everything will appear to work correctly there. 544 545 546 8. Why do my accelerated glyphs look funny? OR Why does the fifo complain 547 about invalid commands when I draw accelerated glyphs? 548 549 The bitmap data passed to SVGA_CMD_DRAW_GLYPH_* must not have any per-scanline 550 alignment. If there are any remaining bits left in the last byte of a scanline, 551 the first bits of the next scanline should use them. 552 553 The bitmap data as a whole must be 4 byte aligned. 554 555 $XFree86: xc/programs/Xserver/hw/xfree86/drivers/vmware/README,v 1.5 2002/10/16 22:12:53 alanh Exp $ 556
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