vb_def.h revision dfe64dd3
1/* Copyright (C) 2003-2006 by XGI Technology, Taiwan. 2 * 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation on the rights to use, copy, modify, merge, 9 * publish, distribute, sublicense, and/or sell copies of the Software, 10 * and to permit persons to whom the Software is furnished to do so, 11 * subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 20 * NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR 21 * ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 22 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 */ 26 27#ifndef _INITDEF_ 28#define _INITDEF_ 29 30#ifndef NewScratch 31#define NewScratch 32#endif 33/* shampoo */ 34#ifdef LINUX_KERNEL 35#define SEQ_ADDRESS_PORT 0x0014 36#define SEQ_DATA_PORT 0x0015 37#define MISC_OUTPUT_REG_READ_PORT 0x001C 38#define MISC_OUTPUT_REG_WRITE_PORT 0x0012 39#define GRAPH_DATA_PORT 0x1F 40#define GRAPH_ADDRESS_PORT 0x1E 41#define XGI_MASK_DUAL_CHIP 0x04 /* SR3A */ 42#define CRTC_ADDRESS_PORT_COLOR 0x0024 43#define VIDEO_SUBSYSTEM_ENABLE_PORT 0x0013 44#define PCI_COMMAND 0x04 45#endif 46/* ~shampoo */ 47 48 49#define VB_XGI301 0x0001 /*301b*/ 50#define VB_XGI301B 0x0002 51#define VB_XGI302B 0x0004 52#define VB_XGI301LV 0x0008 /*301lv*/ 53#define VB_XGI302LV 0x0010 54#define VB_XGI302ELV 0x0020 55#define VB_XGI301C 0x0040 /* for 301C */ 56#define VB_NoLCD 0x8000 57#define VB_XGI301BLV302BLV (VB_XGI301B|VB_XGI301C|VB_XGI302B|VB_XGI301LV|VB_XGI302LV|VB_XGI302ELV) 58#define VB_XGI301LV302LV (VB_XGI301LV|VB_XGI302LV|VB_XGI302ELV) 59#define VB_XGIVB (VB_XGI301 | VB_XGI301BLV302BLV) 60/*end 301b*/ 61 62#define VB_YPbPrInfo 0x07 /*301lv*/ 63#define VB_YPbPr525i 0x00 64#define VB_YPbPr525p 0x01 65#define VB_YPbPr750p 0x02 66#define VB_YPbPr1080i 0x03 67 68/* #define CRT1Len 17 */ 69#define LVDSCRT1Len 15 70#define CHTVRegDataLen 5 71 72/* #define ModeInfoFlag 0x07 */ 73/* #define IsTextMode 0x07 */ 74/* #define ModeText 0x00 */ 75/* #define ModeCGA 0x01 */ 76/* #define ModeEGA 0x02 */ 77/* #define ModeVGA 0x03 */ 78/* #define Mode15Bpp 0x04 */ 79/* #define Mode16Bpp 0x05 */ 80/* #define Mode24Bpp 0x06 */ 81/* #define Mode32Bpp 0x07 */ 82 83/* #define DACInfoFlag 0x18 */ 84/* #define MemoryInfoFlag 0x1E0 */ 85/* #define MemorySizeShift 0x05 */ 86 87#define Charx8Dot 0x0200 88#define LineCompareOff 0x0400 89#define CRT2Mode 0x0800 90#define HalfDCLK 0x1000 91#define NoSupportSimuTV 0x2000 92#define DoubleScanMode 0x8000 93 94#define SupportAllCRT2 0x0078 95#define SupportTV 0x0008 96#define SupportHiVisionTV 0x0010 97#define SupportLCD 0x0020 98#define SupportRAMDAC2 0x0040 /* All (<= 100Mhz) */ 99#define NoSupportTV 0x0070 100#define NoSupportHiVisionTV 0x0060 101#define NoSupportLCD 0x0058 102#define SupportCHTV 0x0800 103#define SupportCRT2in301C 0x0100 /* for 301C */ 104#define SupportTV1024 0x0800 /*301b*/ 105#define SupportYPbPr 0x1000 /*301lv*/ 106#define InterlaceMode 0x0080 107#define SyncPP 0x0000 108#define SyncPN 0x4000 109#define SyncNP 0x8000 110/* #define SyncNN 0xc000 */ 111#define ECLKindex0 0x0000 112#define ECLKindex1 0x0100 113#define ECLKindex2 0x0200 114#define ECLKindex3 0x0300 115#define ECLKindex4 0x0400 116 117/** 118 * CR30 119 */ 120#define SetSimuScanMode 0x0001 121#define SwitchToCRT2 0x0002 122#define SetCRT2ToAVIDEO 0x0004 123#define SetCRT2ToSVIDEO 0x0008 124#define SetCRT2ToSCART 0x0010 125#define SetCRT2ToLCD 0x0020 126#define SetCRT2ToRAMDAC 0x0040 127#define SetCRT2ToHiVisionTV 0x0080 128#define SetCRT2ToCHYPbPr SetCRT2ToHiVisionTV /* for Chrontel */ 129 130/** 131 * CR31 132 */ 133#define SetNTSCTV 0x0000 134/* #define SetPALTV 0x0100 */ 135#define SetCRT2ToLCDA 0x0100 136#define SetInSlaveMode 0x0200 137#define SetNotSimuMode 0x0400 138#define SetNotSimuTVMode SetNotSimuMode 139#define SetDispDevSwitch 0x0800 140#define SetCRT2ToYPbPr 0x0800 141#define LoadDACFlag 0x1000 142#define DisableCRT2Display 0x2000 143#define DriverMode 0x4000 144#define HotKeySwitch 0x8000 145#define SetCHTVOverScan 0x8000 146#define SetCRT2ToDualEdge 0x8000 147/* #define SetCRT2ToLCDA 0x8000 301b */ 148#define PanelRGB18Bit 0x0100 149#define PanelRGB24Bit 0x0000 150 151/* v-- Needs change in xgi_vga.c if changed (GPIO) --v */ 152#define SetCRT2ToTV1 (SetCRT2ToHiVisionTV | SetCRT2ToSCART | SetCRT2ToSVIDEO | SetCRT2ToAVIDEO) 153#define SetCRT2ToTV (SetCRT2ToYPbPr | SetCRT2ToTV1) 154 155 156#define TVOverScan 0x10 157#define TVOverScanShift 4 158#define ClearBufferFlag 0x20 159#define EnableDualEdge 0x01 /*301b*/ 160#define SetToLCDA 0x02 161 162#define YPbPrModeInfo 0x38 163/* #define YPbPrMode525i 0x00 */ 164/* #define YPbPrMode525p 0x08 */ 165/* #define YPbPrMode750p 0x10 */ 166/* #define YPbPrMode1080i 0x18 */ 167 168#define SetSCARTOutput 0x01 169#define BoardTVType 0x02 170#define EnablePALMN 0x40 /* Romflag: 1 = Allow PALM/PALN */ 171/* #define LCDVESATiming 0x0008 */ 172/* #define EnableLVDSDDA 0x0010 */ 173 174#define Panel320x480 0x07/*fstn*/ 175/* [ycchen] 02/12/03 Modify for Multi-Sync. LCD Support */ 176#define PanelResInfo 0x1F /* CR36 Panel Type/LCDResInfo */ 177#define PanelRefInfo 0x60 178#define Panel800x600 0x01 179#define Panel1024x768 0x02 180#define Panel1024x768x75 0x22 181#define Panel1280x1024 0x03 182#define Panel1280x1024x75 0x23 183#define Panel640x480 0x04 184#define Panel1024x600 0x05 185#define Panel1152x864 0x06 186#define Panel1280x960 0x07 187#define Panel1152x768 0x08 188#define Panel1400x1050 0x09 189#define Panel1280x768 0x0A 190#define Panel1600x1200 0x0B 191#define Panel1600x1200_1 0x0E 192 193#define PanelRef60Hz 0x00 194#define PanelRef75Hz 0x20 195 196/* #define DDC2DelayTime 300 */ 197 198#define CRT2DisplayFlag 0x2000 199/* #define LCDDataLen 8 */ 200/* #define HiTVDataLen 12 */ 201/* #define TVDataLen 16 */ 202/* #define SetPALTV 0x0100 */ 203#define HalfDCLK 0x1000 204#define NTSCHT 1716 205#define NTSC2HT 1920 206#define NTSCVT 525 207#define PALHT 1728 208#define PALVT 625 209#define StHiTVHT 892 210#define StHiTVVT 1126 211#define StHiTextTVHT 1000 212#define StHiTextTVVT 1126 213#define ExtHiTVHT 2100 214#define ExtHiTVVT 1125 215 216#define St750pTVHT 1716 217#define St750pTVVT 525 218#define Ext750pTVHT 1716 219#define Ext750pTVVT 525 220#define St525pTVHT 1716 221#define St525pTVVT 525 222#define Ext525pTVHT 1716 223#define Ext525pTVVT 525 224#define St525iTVHT 1716 225#define St525iTVVT 525 226#define Ext525iTVHT 1716 227#define Ext525iTVVT 525 228 229#define VCLKStartFreq 25 230#define SoftDramType 0x80 231#define VCLK40 0x04 232 233#define VCLK162 0x21 234 235#define YPbPr525iVCLK 0x03B 236#define YPbPr525iVCLK_2 0x03A 237 238/* #define LCDVESATiming 0x08 */ 239#define SetSCARTOutput 0x01 240#define AVIDEOSense 0x01 241#define SVIDEOSense 0x02 242#define SCARTSense 0x04 243#define LCDSense 0x08 244#define Monitor1Sense 0x20 245#define Monitor2Sense 0x10 246#define HiTVSense 0x40 247#define BoardTVType 0x02 248#define HotPlugFunction 0x08 249#define StStructSize 0x06 250 251 252#define XGI_VIDEO_CAPTURE 0x00 - 0x30 253#define XGI_VIDEO_PLAYBACK 0x02 - 0x30 254#define XGI_CRT2_PORT_00 0x00 - 0x30 255#define XGI_CRT2_PORT_04 0x04 - 0x30 256#define XGI_CRT2_PORT_10 0x10 - 0x30 257#define XGI_CRT2_PORT_12 0x12 - 0x30 258#define XGI_CRT2_PORT_14 0x14 - 0x30 259 260 261#define ADR_CRT2PtrData 0x20E 262#define offset_Zurac 0x210 /* TW: Trumpion Zurac data pointer */ 263#define ADR_LVDSDesPtrData 0x212 264#define ADR_LVDSCRT1DataPtr 0x214 265#define ADR_CHTVVCLKPtr 0x216 266#define ADR_CHTVRegDataPtr 0x218 267 268#define LVDSDataLen 6 269/* #define EnableLVDSDDA 0x10 */ 270/* #define LVDSDesDataLen 3 */ 271#define ActiveNonExpanding 0x40 272#define ActiveNonExpandingShift 6 273/* #define ActivePAL 0x20 */ 274#define ActivePALShift 5 275/* #define ModeSwitchStatus 0x0F */ 276#define SoftTVType 0x40 277#define SoftSettingAddr 0x52 278#define ModeSettingAddr 0x53 279 280/* #define SelectCRT1Rate 0x4 */ 281 282#define _PanelType00 0x00 283#define _PanelType01 0x08 284#define _PanelType02 0x10 285#define _PanelType03 0x18 286#define _PanelType04 0x20 287#define _PanelType05 0x28 288#define _PanelType06 0x30 289#define _PanelType07 0x38 290#define _PanelType08 0x40 291#define _PanelType09 0x48 292#define _PanelType0A 0x50 293#define _PanelType0B 0x58 294#define _PanelType0C 0x60 295#define _PanelType0D 0x68 296#define _PanelType0E 0x70 297#define _PanelType0F 0x78 298 299 300#define PRIMARY_VGA 0 /* 1: XGI is primary vga 0:XGI is secondary vga */ 301#define BIOSIDCodeAddr 0x235 /* Offsets to ptrs in BIOS image */ 302#define OEMUtilIDCodeAddr 0x237 303#define VBModeIDTableAddr 0x239 304#define OEMTVPtrAddr 0x241 305#define PhaseTableAddr 0x243 306#define NTSCFilterTableAddr 0x245 307#define PALFilterTableAddr 0x247 308#define OEMLCDPtr_1Addr 0x249 309#define OEMLCDPtr_2Addr 0x24B 310#define LCDHPosTable_1Addr 0x24D 311#define LCDHPosTable_2Addr 0x24F 312#define LCDVPosTable_1Addr 0x251 313#define LCDVPosTable_2Addr 0x253 314#define OEMLCDPIDTableAddr 0x255 315 316#define VBModeStructSize 5 317#define PhaseTableSize 4 318#define FilterTableSize 4 319#define LCDHPosTableSize 7 320#define LCDVPosTableSize 5 321#define OEMLVDSPIDTableSize 4 322#define LVDSHPosTableSize 4 323#define LVDSVPosTableSize 6 324 325#define VB_ModeID 0 326#define VB_TVTableIndex 1 327#define VB_LCDTableIndex 2 328#define VB_LCDHIndex 3 329#define VB_LCDVIndex 4 330 331#define OEMLCDEnable 0x0001 332#define OEMLCDDelayEnable 0x0002 333#define OEMLCDPOSEnable 0x0004 334#define OEMTVEnable 0x0100 335#define OEMTVDelayEnable 0x0200 336#define OEMTVFlickerEnable 0x0400 337#define OEMTVPhaseEnable 0x0800 338#define OEMTVFilterEnable 0x1000 339 340#define OEMLCDPanelIDSupport 0x0080 341 342/* #define LCDVESATiming 0x0001 //LCD Info CR37 */ 343/* #define EnableLVDSDDA 0x0002 */ 344#define EnableScalingLCD 0x0008 345#define SetPWDEnable 0x0004 346#define SetLCDtoNonExpanding 0x0010 347/* #define SetLCDPolarity 0x00E0 */ 348#define SetLCDDualLink 0x0100 349#define SetLCDLowResolution 0x0200 350#define SetLCDStdMode 0x0400 351#define SetTVStdMode 0x0200 352#define SetTVLowResolution 0x0400 353/* ============================================================= 354 for 310 355============================================================== */ 356#define SoftDRAMType 0x80 357#define SoftSetting_OFFSET 0x52 358#define SR07_OFFSET 0x7C 359#define SR15_OFFSET 0x7D 360#define SR16_OFFSET 0x81 361#define SR17_OFFSET 0x85 362#define SR19_OFFSET 0x8D 363#define SR1F_OFFSET 0x99 364#define SR21_OFFSET 0x9A 365#define SR22_OFFSET 0x9B 366#define SR23_OFFSET 0x9C 367#define SR24_OFFSET 0x9D 368#define SR25_OFFSET 0x9E 369#define SR31_OFFSET 0x9F 370#define SR32_OFFSET 0xA0 371#define SR33_OFFSET 0xA1 372 373#define CR40_OFFSET 0xA2 374#define SR25_1_OFFSET 0xF6 375#define CR49_OFFSET 0xF7 376 377#define VB310Data_1_2_Offset 0xB6 378#define VB310Data_4_D_Offset 0xB7 379#define VB310Data_4_E_Offset 0xB8 380#define VB310Data_4_10_Offset 0xBB 381 382#define RGBSenseDataOffset 0xBD 383#define YCSenseDataOffset 0xBF 384#define VideoSenseDataOffset 0xC1 385#define OutputSelectOffset 0xF3 386 387#define ECLK_MCLK_DISTANCE 0x14 388#define VBIOSTablePointerStart 0x200 389#define StandTablePtrOffset VBIOSTablePointerStart+0x02 390#define EModeIDTablePtrOffset VBIOSTablePointerStart+0x04 391#define CRT1TablePtrOffset VBIOSTablePointerStart+0x06 392#define ScreenOffsetPtrOffset VBIOSTablePointerStart+0x08 393#define VCLKDataPtrOffset VBIOSTablePointerStart+0x0A 394#define MCLKDataPtrOffset VBIOSTablePointerStart+0x0E 395#define CRT2PtrDataPtrOffset VBIOSTablePointerStart+0x10 396#define TVAntiFlickPtrOffset VBIOSTablePointerStart+0x12 397#define TVDelayPtr1Offset VBIOSTablePointerStart+0x14 398#define TVPhaseIncrPtr1Offset VBIOSTablePointerStart+0x16 399#define TVYFilterPtr1Offset VBIOSTablePointerStart+0x18 400#define LCDDelayPtr1Offset VBIOSTablePointerStart+0x20 401#define TVEdgePtr1Offset VBIOSTablePointerStart+0x24 402#define CRT2Delay1Offset VBIOSTablePointerStart+0x28 403#define LCDDataDesOffset VBIOSTablePointerStart-0x02 404#define LCDDataPtrOffset VBIOSTablePointerStart+0x2A 405#define LCDDesDataPtrOffset VBIOSTablePointerStart+0x2C 406#define LCDDataList VBIOSTablePointerStart+0x22 /* add for GetLCDPtr */ 407#define TVDataList VBIOSTablePointerStart+0x36 /* add for GetTVPtr */ 408/* */ 409/* Modify from 310.inc */ 410/* */ 411/* */ 412 413 414#define ShowMsgFlag 0x20 /* SoftSetting */ 415#define ShowVESAFlag 0x10 416#define HotPlugFunction 0x08 417#define ModeSoftSetting 0x04 418#define TVSoftSetting 0x02 419#define LCDSoftSetting 0x01 420 421#define GatingCRTinLCDA 0x10 422#define SetHiTVOutput 0x08 423#define SetYPbPrOutput 0x04 424#define BoardTVType 0x02 425#define SetSCARTOutput 0x01 426 427#define ModeSettingYPbPr 0x02 /* TVModeSetting, Others as same as CR30 */ 428 429/* TVModeSetting same as CR35 */ 430 431/* LCDModeSetting same as CR37 */ 432 433#define EnableNewTVFont 0x10 /* MiscCapability */ 434 435#define EnableLCDOutput 0x80 /* LCDCfgSetting */ 436 437#define SoftDRAMType 0x80 /* DRAMSetting */ 438#define SoftDRAMConfig 0x40 439#define MosSelDRAMType 0x20 440#define SDRAM 000h 441#define SGRAM 0x01 442#define ESDRAM 0x02 443 444#define EnableAGPCfgSetting 0x01 /* AGPCfgSetting */ 445 446/* ---------------- SetMode Stack */ 447#define CRT1Len 15 448#define VCLKLen 4 449#define DefThreshold 0x0100 450#define ExtRegsSize (57+8+37+70+63+28+768+1)/64+1 451 452#define VB_XGI301 0x0001 /* VB Type Info */ 453#define VB_XGI301B 0x0002 /* 301 series */ 454#define VB_XGI302B 0x0004 455#define VB_NoLCD 0x8000 456#define VB_XGI301LV 0x0008 457#define VB_XGI302LV 0x0010 458#define VB_LVDS_NS 0x0001 /* 3rd party chip */ 459 460/* Jong 10/04/2007; merge code */ 461#define VB_CH7017 0x0002 462#define VB_CH7007 0x0080 /* [Billy] 07/05/03 */ 463 464/* #define VB_LVDS_SI 0x0004 */ 465 466#define ModeInfoFlag 0x0007 467#define IsTextMode 0x0007 468#define ModeText 0x0000 469#define ModeCGA 0x0001 470#define ModeEGA 0x0002 /* 16 colors mode */ 471#define ModeVGA 0x0003 /* 256 colors mode */ 472#define Mode15Bpp 0x0004 /* 15 Bpp Color Mode */ 473#define Mode16Bpp 0x0005 /* 16 Bpp Color Mode */ 474#define Mode24Bpp 0x0006 /* 24 Bpp Color Mode */ 475#define Mode32Bpp 0x0007 /* 32 Bpp Color Mode */ 476 477#define DACInfoFlag 0x0018 478#define MONODAC 0x0000 479#define CGADAC 0x0008 480#define EGADAC 0x0010 481#define VGADAC 0x0018 482 483#define MemoryInfoFlag 0x01e0 484#define MemorySizeShift 5 485#define Need1MSize 0x0000 486#define Need2MSize 0x0020 487#define Need4MSize 0x0060 488#define Need8MSize 0x00e0 489#define Need16MSize 0x01e0 490 491#define Charx8Dot 0x0200 492#define LineCompareOff 0x0400 493#define CRT2Mode 0x0800 494#define HalfDCLK 0x1000 495#define NoSupportSimuTV 0x2000 496#define DoubleScanMode 0x8000 497 498/* -------------- Ext_InfoFlag */ 499#define SupportModeInfo 0x0007 500#define Support256 0x0003 501#define Support15Bpp 0x0004 502#define Support16Bpp 0x0005 503#define Support24Bpp 0x0006 504#define Support32Bpp 0x0007 505 506#define SupportAllCRT2 0x0078 507#define SupportTV 0x0008 508#define SupportHiVisionTV 0x0010 509#define SupportLCD 0x0020 510#define SupportRAMDAC2 0x0040 511#define NoSupportTV 0x0070 512#define NoSupportHiVisionTV 0x0060 513#define NoSupportLCD 0x0058 514#define SupportTV1024 0x0800 /* 301btest */ 515#define SupportYPbPr 0x1000 /* 301lv */ 516#define InterlaceMode 0x0080 517#define SyncPP 0x0000 518#define SyncPN 0x4000 519#define SyncNP 0x8000 520#define SyncNN 0xc000 521 522/** 523 * Bits for SetFlag 524 */ 525#define ProgrammingCRT2 0x0001 526#define LowModeTests 0x0002 527#define EnableVCMode 0x0004 528#define SetHKEventMode 0x0008 529#define ReserveTVOption 0x0010 530#define DisableRelocateIO 0x0020 531#define Win9xDOSMode 0x0040 532#define GatingCRT 0x0800 533#define DisableChB 0x1000 534#define EnableChB 0x2000 535#define DisableChA 0x4000 536#define EnableChA 0x8000 537 538#define SetNTSCTV 0x0000 /* TV Info */ 539#define SetPALTV 0x0001 540#define SetNTSCJ 0x0002 541#define SetPALMTV 0x0004 542#define SetPALNTV 0x0008 543#define SetCHTVUnderScan 0x0000 544/* #define SetCHTVOverScan 0x0010 */ 545#define SetYPbPrMode525i 0x0020 546#define SetYPbPrMode525p 0x0040 547#define SetYPbPrMode750p 0x0080 548#define SetYPbPrMode1080i 0x0100 549#define SetTVStdMode 0x0200 550#define SetTVLowResolution 0x0400 551#define SetTVSimuMode 0x0800 552#define TVSimuMode 0x0800 553#define RPLLDIV2XO 0x1000 554#define NTSC1024x768 0x2000 555#define SetTVLockMode 0x4000 556 557#define LCDVESATiming 0x0001 /* LCD Info/CR37 */ 558#define EnableLVDSDDA 0x0002 559#define EnableScalingLCD 0x0008 560#define SetPWDEnable 0x0004 561#define SetLCDtoNonExpanding 0x0010 562#define SetLCDPolarity 0x00e0 563#define SetLCDDualLink 0x0100 564#define SetLCDLowResolution 0x0200 565#define SetLCDStdMode 0x0400 566#define EnableReduceTiming 0x0800 567 568#define DefaultLCDCap 0x80ea /* LCD Capability shampoo */ 569#define RLVDSDHL00 0x0000 570#define RLVDSDHL01 0x0001 571#define RLVDSDHL10 0x0002 /* default */ 572#define RLVDSDHL11 0x0003 573#define EnableLCD24bpp 0x0004 /* default */ 574#define DisableLCD24bpp 0x0000 575#define RLVDSClkSFT0 0x0000 576#define RLVDSClkSFT1 0x0008 /* default */ 577#define EnableLVDSDCBal 0x0010 578#define DisableLVDSDCBal 0x0000 /* default */ 579#define SinglePolarity 0x0020 /* default */ 580#define MultiPolarity 0x0000 581#define LCDPolarity 0x00c0 /* default: SyncNN */ 582#define LCDSingleLink 0x0000 /* default */ 583#define LCDDualLink 0x0100 584#define EnableSpectrum 0x0200 585#define DisableSpectrum 0x0000 /* default */ 586#define PWDEnable 0x0400 587#define PWDDisable 0x0000 /* default */ 588#define PWMEnable 0x0800 589#define PWMDisable 0x0000 /* default */ 590#define EnableVBCLKDRVLOW 0x4000 591#define EnableVBCLKDRVHigh 0x0000 /* default */ 592#define EnablePLLSPLOW 0x8000 593#define EnablePLLSPHigh 0x0000 /* default */ 594 595#define LCDBToA 0x20 /* LCD SetFlag */ 596#define StLCDBToA 0x40 597#define LockLCDBToA 0x80 598#define LCDToFull 0x10 599#define AVIDEOSense 0x01 /* CR32 */ 600#define SVIDEOSense 0x02 601#define SCARTSense 0x04 602#define LCDSense 0x08 603#define Monitor2Sense 0x10 604#define Monitor1Sense 0x20 605#define HiTVSense 0x40 606 607#ifdef NewScratch 608#define YPbPrSense 0x80 /* NEW SCRATCH */ 609#endif 610 611#define TVSense 0xc7 612 613/** 614 * CR35 (661 series only) 615 * 616 * [0] 1 = PAL, 0 = NTSC 617 * [1] 1 = NTSC-J (if D0 = 0) 618 * [2] 1 = PALM (if D0 = 1) 619 * [3] 1 = PALN (if D0 = 1) 620 * [4] 1 = Overscan (Chrontel only) 621 * [7:5] (only if D2 in CR38 is set) 622 * 000 525i 623 * 001 525p 624 * 010 750p 625 * 011 1080i (or HiVision on 301, 301B) 626 * 627 * These bits are being translated to TVMode flag. 628 */ 629#define TVOverScan 0x10 630#define TVOverScanShift 4 631 632#ifdef NewScratch 633#define NTSCMode 0x00 634#define PALMode 0x00 635#define NTSCJMode 0x02 636#define PALMNMode 0x0c 637#define YPbPrMode 0xe0 638#define YPbPrMode525i 0x00 639#define YPbPrMode525p 0x20 640#define YPbPrMode750p 0x40 641#define YPbPrMode1080i 0x60 642#else /* Old Scratch */ 643#define ClearBufferFlag 0x20 644#endif 645 646 647/** 648 * CR37 649 * 650 * [0] Set 24/18 bit (0/1) RGB to LVDS/TMDS transmitter (set by BIOS) 651 * [3:1] External chip 652 * 660 series [2:1] only: 653 * reserved (now in CR38) 654 * All other combinations reserved 655 * [3] 661 only: Pass 1:1 data 656 * [4] LVDS: 0: Panel Link expands / 1: Panel Link does not expand 657 * 30x: 0: Bridge scales / 1: Bridge does not scale = Panel scales (if possible) 658 * [5] LCD polarity select 659 * 0: VESA DMT Standard 660 * 1: EDID 2.x defined 661 * [6] LCD horizontal polarity select 662 * 0: High active 663 * 1: Low active 664 * [7] LCD vertical polarity select 665 * 0: High active 666 * 1: Low active 667 */ 668#define ExtChipTrumpion 0x0006 /**< Is this actually CR38? */ 669#define ExtChipMitacTV 0x000a /**< Is this actually CR38? */ 670#define LCDRGB18Bit 0x0001 671#define ScalingLCD 0x0008 672#define LCDNonExpanding 0x0010 673#define LCDNonExpandingShift 4 674#define LCDSync 0x0020 675#define LCDSyncBit 0x00e0 /* H/V polarity & sync ID */ 676#define LCDSyncShift 6 677#define LCDPass11 0x0100 /* 0: center screen, 1: Pass 1:1 data */ 678 679#define DontExpandLCD LCDNonExpanding 680#define DontExpandLCDShift LCDNonExpandingShift 681 682 683/** 684 * CR38 (661 and later) 685 * 686 * D[7:5] 000 No VB 687 * 001 301 series VB 688 * 010 LVDS 689 * 011 Chrontel 7019 690 * 100 Conexant 691 * D2 Enable YPbPr output (see CR35) 692 * D[1:0] LCDA (like before) 693 */ 694#define EnableDualEdge 0x01 /* CR38 */ 695#define SetToLCDA 0x02 696#ifdef NewScratch 697#define SetYPbPr 0x04 698#define DisableChannelA 0x08 699#define DisableChannelB 0x10 700#define ExtChipType 0xe0 701#define ExtChip301 0x20 702#define ExtChipLVDS 0x40 703#define ExtChipCH7019 0x60 704#else /* Old Scratch */ 705#define YPbPrSense 0x04 706#define SetYPbPr 0x08 707#define YPbPrMode 0x30 708#define YPbPrMode525i 0x00 709#define YPbPrMode525p 0x10 710#define YPbPrMode750p 0x20 711#define YPbPrMode1080i 0x30 712#define PALMNMode 0xc0 713#endif 714 715/** 716 * CR39 (661 and later) 717 * 718 * D[1:0] YPbPr Aspect Ratio 719 * 00 4:3 letterbox 720 * 01 4:3 721 * 10 16:9 722 * 11 4:3 723 */ 724#define ReduceTiming 0x0001 725 726#define BacklightControlBit 0x01 /* CR3A */ 727#define Win9xforJap 0x40 728#define Win9xforKorea 0x80 729 730#define ForceMDBits 0x07 /* CR3B */ 731#define ForceMD_JDOS 0x00 732#define ForceMD_640x400T 0x01 733#define ForceMD_640x350T 0x02 734#define ForceMD_720x400T 0x03 735#define ForceMD_640x480E 0x04 736#define ForceMD_640x400E 0x05 737#define ForceP1Bit 0x10 738#define ForceP2Bit 0x20 739#define EnableForceMDinBIOS 0x40 740#define EnableForceMDinDrv 0x80 741 742#ifdef NewScratch /* New Scratch */ 743/* ---------------------- VUMA Information */ 744#define LCDSettingFromCMOS 0x04 /* CR3C */ 745#define TVSettingFromCMOS 0x08 746#define DisplayDeviceFromCMOS 0x10 747#define HKSupportInSBIOS 0x20 748#define OSDSupportInSBIOS 0x40 749#define DisableLogo 0x80 750 751/* ---------------------- HK Evnet Definition */ 752#define HKEvent 0x0f /* CR3D */ 753#define HK_ModeSwitch 0x01 754#define HK_Expanding 0x02 755#define HK_OverScan 0x03 756#define HK_Brightness 0x04 757#define HK_Contrast 0x05 758#define HK_Mute 0x06 759#define HK_Volume 0x07 760#define ModeSwitchStatus 0xf0 761#define ActiveCRT1 0x10 762#define ActiveLCD 0x20 763#define ActiveTV 0x40 764#define ActiveCRT2 0x80 765 766#define TVSwitchStatus 0x1f /* CR3E */ 767#define ActiveAVideo 0x01 768#define ActiveSVideo 0x02 769#define ActiveSCART 0x04 770#define ActiveHiTV 0x08 771#define ActiveYPbPr 0x10 772 773#define EnableHKEvent 0x01 /* CR3F */ 774#define EnableOSDEvent 0x02 775#define StartOSDEvent 0x04 776#define IgnoreHKEvent 0x08 777#define IgnoreOSDEvent 0x10 778#else /* Old Scratch */ 779#define OSD_SBIOS 0x02 /* SR17 */ 780#define DisableLogo 0x04 781#define SelectKDOS 0x08 782#define KorWinMode 0x10 783#define KorMode3Bit 0x0020 784#define PSCCtrlBit 0x40 785#define NPSCCtrlBitShift 6 786#define BlueScreenBit 0x80 787 788#define HKEvent 0x0f /* CR79 */ 789#define HK_ModeSwitch 0x01 790#define HK_Expanding 0x02 791#define HK_OverScan 0x03 792#define HK_Brightness 0x04 793#define HK_Contrast 0x05 794#define HK_Mute 0x06 795#define HK_Volume 0x07 796#define ActivePAL 0x20 797#define ActivePALShift 5 798#define ActiveNonExpanding 0x40 799#define ActiveNonExpandingShift 6 800#define ActiveOverScan 0x80 801#define ActiveOverScanShift 7 802 803#define ModeSwitchStatus 0x0b /* SR15 */ 804#define ActiveCRT1 0x01 805#define ActiveLCD 0x02 806#define ActiveCRT2 0x08 807 808#define TVSwitchStatus 0xf0 /* SR16 */ 809#define TVConfigShift 3 810#define ActiveTV 0x01 811#define ActiveYPbPr 0x04 812#define ActiveAVideo 0x10 813#define ActiveSVideo 0x0020 814#define ActiveSCART 0x40 815#define ActiveHiTV 0x80 816 817#define EnableHKEvent 0x01 /* CR7A */ 818#define EnableOSDEvent 0x02 819#define StartOSDEvent 0x04 820#define CMOSSupport 0x08 821#define HotKeySupport 0x10 822#define IngoreHKOSDEvent 0x20 823#endif 824 825/* //------------- Misc. Definition */ 826#define SelectCRT1Rate 00h 827/* #define SelectCRT2Rate 04h */ 828 829#define DDC1DelayTime 1000 830#ifdef TRUMPION 831#define DDC2DelayTime 15 832#else 833#define DDC2DelayTime 150 834#endif 835 836#define R_FACTOR 04Dh 837#define G_FACTOR 097h 838#define B_FACTOR 01Ch 839/* --------------------------------------------------------- */ 840/* translated from asm code 301def.h */ 841/* */ 842/* --------------------------------------------------------- */ 843#define LCDDataLen 8 844#define HiTVDataLen 12 845#define TVDataLen 12 846#define LVDSCRT1Len_H 8 847#define LVDSCRT1Len_V 7 848#define LVDSDataLen 6 849#define LVDSDesDataLen 6 850#define LCDDesDataLen 6 851#define LVDSDesDataLen2 8 852#define LCDDesDataLen2 8 853#define CHTVRegLen 16 854#define CHLVRegLen 12 855 856#define StHiTVHT 892 857#define StHiTVVT 1126 858#define StHiTextTVHT 1000 859#define StHiTextTVVT 1126 860#define ExtHiTVHT 2100 861#define ExtHiTVVT 1125 862#define NTSCHT 1716 863#define NTSCVT 525 864#define NTSC1024x768HT 1908 865#define NTSC1024x768VT 525 866#define PALHT 1728 867#define PALVT 625 868 869#define YPbPrTV525iHT 1716 /* YPbPr */ 870#define YPbPrTV525iVT 525 871#define YPbPrTV525pHT 1716 872#define YPbPrTV525pVT 525 873#define YPbPrTV750pHT 1650 874#define YPbPrTV750pVT 750 875 876#define CRT2VCLKSel 0xc0 877 878#define CRT2Delay1 0x04 /* XGI301 */ 879#define CRT2Delay2 0x0A /* 301B,302 */ 880 881 882#define VCLK25_175 0x00 883#define VCLK28_322 0x01 884#define VCLK31_5 0x02 885#define VCLK36 0x03 886#define VCLK40 0x04 887#define VCLK43_163 0x05 888#define VCLK44_9 0x06 889#define VCLK49_5 0x07 890#define VCLK50 0x08 891#define VCLK52_406 0x09 892#define VCLK56_25 0x0A 893#define VCLK65 0x0B 894#define VCLK67_765 0x0C 895#define VCLK68_179 0x0D 896#define VCLK72_852 0x0E 897#define VCLK75 0x0F 898#define VCLK75_8 0x10 899#define VCLK78_75 0x11 900#define VCLK79_411 0x12 901#define VCLK83_95 0x13 902#define VCLK84_8 0x14 903#define VCLK86_6 0x15 904#define VCLK94_5 0x16 905#define VCLK104_998 0x17 906#define VCLK105_882 0x18 907#define VCLK108_2 0x19 908#define VCLK109_175 0x1A 909#define VCLK113_309 0x1B 910#define VCLK116_406 0x1C 911#define VCLK132_258 0x1D 912#define VCLK135_5 0x1E 913#define VCLK139_054 0x1F 914#define VCLK157_5 0x20 915#define VCLK162 0x21 916#define VCLK175 0x22 917#define VCLK189 0x23 918#define VCLK194_4 0x24 919#define VCLK202_5 0x25 920#define VCLK229_5 0x26 921#define VCLK234 0x27 922#define VCLK252_699 0x28 923#define VCLK254_817 0x29 924#define VCLK265_728 0x2A 925#define VCLK266_952 0x2B 926#define VCLK269_655 0x2C 927#define VCLK272_042 0x2D 928#define VCLK277_015 0x2E 929#define VCLK286_359 0x2F 930#define VCLK291_132 0x30 931#define VCLK291_766 0x31 932#define VCLK309_789 0x32 933#define VCLK315_195 0x33 934#define VCLK323_586 0x34 935#define VCLK330_615 0x35 936#define VCLK332_177 0x36 937#define VCLK340_477 0x37 938#define VCLK375_847 0x38 939#define VCLK388_631 0x39 940#define VCLK125_999 0x51 941#define VCLK148_5 0x52 942#define VCLK178_992 0x54 943#define VCLK217_325 0x55 944#define VCLK299_505 0x56 945#define YPbPr750pVCLK 0x57 946 947#define TVVCLKDIV2 0x3A 948#define TVVCLK 0x3B 949#define HiTVVCLKDIV2 0x3C 950#define HiTVVCLK 0x3D 951#define HiTVSimuVCLK 0x3E 952#define HiTVTextVCLK 0x3F 953#define VCLK39_77 0x40 954/* #define YPbPr750pVCLK 0x0F */ 955#define YPbPr525pVCLK 0x3A 956/* #define ;;YPbPr525iVCLK 0x3B */ 957/* #define ;;YPbPr525iVCLK_2 0x3A */ 958#define NTSC1024VCLK 0x41 959#define VCLK25_175_41 0x42 /* ; ScaleLCD */ 960#define VCLK25_175_42 0x43 961#define VCLK28_322_43 0x44 962#define VCLK40_44 0x45 963#define VCLKQVGA_1 0x46 /* ; QVGA */ 964#define VCLKQVGA_2 0x47 965#define VCLKQVGA_3 0x48 966#define VCLK35_2 0x49 /* ; 800x480 */ 967#define VCLK122_61 0x4A 968#define VCLK80_350 0x4B 969#define VCLK107_385 0x4C 970 971#define CHTVVCLK30_2 0x50 /* ;;CHTV */ 972#define CHTVVCLK28_1 0x51 973#define CHTVVCLK43_6 0x52 974#define CHTVVCLK26_4 0x53 975#define CHTVVCLK24_6 0x54 976#define CHTVVCLK47_8 0x55 977#define CHTVVCLK31_5 0x56 978#define CHTVVCLK26_2 0x57 979#define CHTVVCLK39 0x58 980#define CHTVVCLK36 0x59 981 982/* Jong 10/04/2007; merge code */ 983#define CH7007TVVCLK30_2 0x00 /* [Billy] 2007/05/18 For CH7007 */ 984#define CH7007TVVCLK28_1 0x01 985#define CH7007TVVCLK43_6 0x02 986#define CH7007TVVCLK26_4 0x03 987#define CH7007TVVCLK24_6 0x04 988#define CH7007TVVCLK47_8 0x05 989#define CH7007TVVCLK31_5 0x06 990#define CH7007TVVCLK26_2 0x07 991#define CH7007TVVCLK39 0x08 992#define CH7007TVVCLK36 0x09 993 994#define RES320x200 0x00 995#define RES320x240 0x01 996#define RES400x300 0x02 997#define RES512x384 0x03 998#define RES640x400 0x04 999#define RES640x480x60 0x05 1000#define RES640x480x72 0x06 1001#define RES640x480x75 0x07 1002#define RES640x480x85 0x08 1003#define RES640x480x100 0x09 1004#define RES640x480x120 0x0A 1005#define RES640x480x160 0x0B 1006#define RES640x480x200 0x0C 1007#define RES800x600x56 0x0D 1008#define RES800x600x60 0x0E 1009#define RES800x600x72 0x0F 1010#define RES800x600x75 0x10 1011#define RES800x600x85 0x11 1012#define RES800x600x100 0x12 1013#define RES800x600x120 0x13 1014#define RES800x600x160 0x14 1015#define RES1024x768x43 0x15 1016#define RES1024x768x60 0x16 1017#define RES1024x768x70 0x17 1018#define RES1024x768x75 0x18 1019#define RES1024x768x85 0x19 1020#define RES1024x768x100 0x1A 1021#define RES1024x768x120 0x1B 1022#define RES1280x1024x43 0x1C 1023#define RES1280x1024x60 0x1D 1024#define RES1280x1024x75 0x1E 1025#define RES1280x1024x85 0x1F 1026#define RES1600x1200x60 0x20 1027#define RES1600x1200x65 0x21 1028#define RES1600x1200x70 0x22 1029#define RES1600x1200x75 0x23 1030#define RES1600x1200x85 0x24 1031#define RES1600x1200x100 0x25 1032#define RES1600x1200x120 0x26 1033#define RES1920x1440x60 0x27 1034#define RES1920x1440x65 0x28 1035#define RES1920x1440x70 0x29 1036#define RES1920x1440x75 0x2A 1037#define RES1920x1440x85 0x2B 1038#define RES1920x1440x100 0x2C 1039#define RES2048x1536x60 0x2D 1040#define RES2048x1536x65 0x2E 1041#define RES2048x1536x70 0x2F 1042#define RES2048x1536x75 0x30 1043#define RES2048x1536x85 0x31 1044#define RES800x480x60 0x32 1045#define RES800x480x75 0x33 1046#define RES800x480x85 0x34 1047#define RES1024x576x60 0x35 1048#define RES1024x576x75 0x36 1049#define RES1024x576x85 0x37 1050#define RES1280x720x60 0x38 1051#define RES1280x720x75 0x39 1052#define RES1280x720x85 0x3A 1053#define RES1280x960x60 0x3B 1054#define RES720x480x60 0x3C 1055#define RES720x576x56 0x3D 1056#define RES856x480x79I 0x3E 1057#define RES856x480x60 0x3F 1058#define RES1280x768x60 0x40 1059#define RES1400x1050x60 0x41 1060#define RES1152x864x60 0x42 1061#define RES1152x864x75 0x43 1062#define RES1024x768x160 0x44 1063#define RES1280x960x75 0x45 1064#define RES1280x960x85 0x46 1065#define RES1280x960x120 0x47 1066 1067#define LFBDRAMTrap 0x30 1068 1069/** 1070 * SR1E - Module enable register 1071 */ 1072#define SR1E_ENABLE_3D_TRANSFORM_ENGINE (1<<7) 1073#define SR1E_ENABLE_2D (1<<6) 1074#define SR1E_ENABLE_CRT2 (1<<5) 1075#define SR1E_ENABLE_3D_AGP_VERTEX_FETCH (1<<4) 1076#define SR1E_ENABLE_3D_COMMAND_PARSER (1<<3) 1077#define SR1E_ENABLE_VGA_BIOS_WRITE (1<<2) 1078#define SR1E_ENABLE_3D (1<<1) 1079#define SR1E_ENABLE_MPEG (1<<0) 1080 1081/** 1082 * MMIO 85CC - command queue read pointer 1083 */ 1084#define IDLE_ALL (1 << 31) /**< 3D & 2D idle, HQ & SQ empty */ 1085#define EMPTY_HQ (1 << 30) /**< HQ empty */ 1086#define IDLE_2D (1 << 29) /**< 2D idle */ 1087#define IDLE_3D (1 << 28) /**< 3D idle */ 1088#define EMPTY_HW_CQ (1 << 27) /**< Hardware command queue empty */ 1089#define EMPTY_2D (1 << 26) /**< 2D queue empty */ 1090#define EMPTY_3D (1 << 25) /**< 3D queue empty */ 1091#define EMPTY_SW_CQ (1 << 24) /**< Software command queue empty */ 1092#define COUNTER_3_MASK (0xff << 16) 1093#define COUNTER_2_MASK (0xff << 8) 1094#define COUNTER_1_MASK (0xff << 0) 1095 1096#endif 1097