xgi_setup.c revision cb1acafb 
1/*
2 * Basic hardware and memory detection
3 *
4 * Copyright (C) 2001-2004 by Thomas Winischhofer, Vienna, Austria.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1) Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2) Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3) The name of the author may not be used to endorse or promote products
15 *    derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESSED OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Author:  	Thomas Winischhofer <thomas@winischhofer.net>
29 *
30 * Ideas and methods for old series based on code by Can-Ru Yeou, XGI Inc.
31 *
32 */
33
34#ifdef HAVE_CONFIG_H
35#include "config.h"
36#endif
37
38#include "xf86PciInfo.h"
39#include "xf86Pci.h"
40#include "xf86.h"
41#include "fb.h"
42#include "xf86_OSproc.h"
43#include "xorgVersion.h"
44
45#include "xf86cmap.h"
46
47#include "xgi.h"
48#include "xgi_regs.h"
49#include "xgi_dac.h"
50#include "xgi_driver.h"
51/* #include "valid_mode.h" */
52
53#define _XF86DGA_SERVER_
54#include <X11/extensions/xf86dgaproto.h>
55
56#include "globals.h"
57#ifdef HAVE_XEXTPROTO_71
58#include <X11/extensions/dpmsconst.h>
59#else
60#define DPMS_SERVER
61#include <X11/extensions/dpms.h>
62#endif
63
64
65#include "vb_def.h"
66extern  int  FbDevExist;
67
68static Bool bAccessVGAPCIInfo(PXGI_HW_DEVICE_INFO pHwDevInfo, ULONG ulOffset,
69    ULONG ulSet, CARD32 *pulValue);
70static Bool bAccessNBridgePCIInfo(PXGI_HW_DEVICE_INFO pHwDevInfo,
71    ULONG ulOffset, ULONG ulSet, ULONG *pulValue);
72static Bool XGI_IsXG21(ScrnInfoPtr pScrn);
73
74static void XGI_InitHwDevInfo(ScrnInfoPtr pScrn);
75
76/* Jong 10/16/2007; merge code */
77static void
78xgiXG2X_Setup(ScrnInfoPtr pScrn)
79{
80
81/*********************************************************************
82 * Setup
83 * Decide the following item of execution data:
84 *
85 * pXGI->BusWidth
86 * pXGI->videoRam (with KB unit)
87 * pXGI->CursorOffset (with Byte Unit)
88 * pXGI->cmdQueueSize (with Byte Unit)
89 * pXGI->cmdQueueSizeMask (with Byte Unit)
90 * pXGI->cmdQueueOffset (with Byte Unit)
91 * pXGI->cmdQueueLen = 0 ; // init value
92 * pXGI->cmdQueueLenMin = 0x200 ; // init value
93 * pXGI->cmdQueueLenMax = pXGI->cmdQueueSize -  pXGI->cmdQueueLenMin ;
94 *********************************************************************/
95
96    XGIPtr        pXGI = XGIPTR(pScrn);
97    unsigned int  ulMemConfig = 0;
98    unsigned long ulMemSize   = 0;
99    unsigned long ulDramType  = 0;
100    char *dramTypeStr ;
101    unsigned long ulTemp ;
102
103    /* DumpDDIName("xgiXG2X_Setup()\n") ; */
104
105    inXGIIDXREG(XGICR, 0x48, ulTemp) ;
106    if(ulTemp & (1<<0)) /* GPIOH, CR48 D[0] read */
107    {
108        dramTypeStr = "DDRII DRAM" ;
109    }
110    else
111    {
112        dramTypeStr = "DDR DRAM" ;
113    }
114
115
116    pXGI->MemClock = XG40Mclk(pXGI);
117
118    /*********************************************************************************************************
119     * SR14 DRAM Size Register
120     *     Default value: XXh
121     *     D[7:4]    Memory size per channel {BChMemSize}
122     *         0011: 8 MB
123     *         0100: 16 MB
124     *         0101: 32 MB
125     *         0110: 64 MB
126     *         0111: 128 MB
127     *         1000: 256MB
128     *        others: reserved
129     *     D[3:2]    Number of  dram channels [1:0] {BChNum}
130     *         00: uni-channel
131     *         01: reserved
132     *         10: dual-channel.
133     *         11: quad-channel
134     *     D1  Data width per channel selection {BDataWidth}
135     *         0: 32-bits
136     *         1: 64-bits
137     *     D0  Dram channel mapping {BReverseChMapping}
138     *         0: Normal mapping
139     *         1: Reversal mapping
140     *             Dual-channel: Logical channel A/B to physical channel B/A
141     *             Quad-channel: Logical  channel A/B/C/D to physical channel C/D/A/B
142     *
143     *********************************************************************************************************/
144
145    outXGIIDXREG(XGISR, 0x5, 0x86) ;
146    inXGIIDXREG(XGISR, 0x14, ulMemConfig) ;
147    inXGIIDXREG(XGISR, 0x3A, ulDramType) ;
148
149    PDEBUG(ErrorF("xg40_Setup(): ulMemConfig = %02X\n",ulMemConfig)) ;
150    PDEBUG(ErrorF("xg40_Setup(): ulDramType = %02X\n",ulDramType)) ;
151
152    pXGI->BusWidth = (ulMemConfig & (1<<1) )?64:32 ;
153
154    switch(ulMemConfig>>4)
155    {
156    case 8:
157        ulMemSize = 256*1024 ;
158        break ;
159    case 7:
160        ulMemSize = 128*1024 ;
161        break ;
162    case 6:
163        ulMemSize = 64*1024 ;
164        break ;
165    case 5:
166        ulMemSize = 32*1024 ;
167        break ;
168    case 4:
169        ulMemSize = 16*1024 ;
170        break ;
171    case 3:
172        ulMemSize = 8*1024 ;
173        break ;
174    default:
175        ulMemSize = 8*1024 ;
176    }
177
178    if (pXGI->Chipset == PCI_CHIP_XGIXG40) {
179	const unsigned revision =
180#ifdef XSERVER_LIBPCIACCESS
181	    pXGI->PciInfo->revision
182#else
183	    pciReadLong(pXGI->PciTag, 0x08) & 0x0FF
184#endif
185	    ;
186
187	/* Revision 2 cards encode the memory config bits slightly differently
188	 * from revision 1 cards.
189	 */
190        if (revision == 2) {
191            switch((ulMemConfig>>2)&0x1)
192            {
193            case 0:
194                /* Uni channel */
195                ulMemSize *= 1 ;
196       	        break ;
197            case 1:
198                /* Dual channel */
199                ulMemSize *= 2 ;
200    	        break ;
201            }
202        }
203        else
204        {
205            switch((ulMemConfig>>2)&0x3)
206            {
207            case 2:
208                /* Dual channel */
209                ulMemSize *= 2 ;
210        	break ;
211            case 3:
212                /* Quad channel */
213                ulMemSize *= 4 ;
214    	        break ;
215           }
216        }
217    }
218
219    pScrn->videoRam = ulMemSize ;
220
221    /*********************************************************************************************************
222     * SR15 DRAM Address Mapping Register
223     * Default value: XXh
224     *     D7  Channel  interleaving configuration { BChConfig }
225     *         0: Divide the whole memory  into 2/4 equal-sized regions , each mapped to one channel
226     *         1: Divide the whole memory into 2 regions according to BTilingSize[1:0] . The low-address region
227     *         will be channel-interleaved as per BFineGranSize; the high-address region will be channel-
228     *         interleaved  as per BCoarseGranSize[1:0]
229     *     D[6:5]    Memory size of tile-mapped region {BTilingSize}
230     *         00: 4 MB
231     *         01: 8 MB
232     *         10: 16 MB
233     *         11: 32 MB
234     *         The following bits are effective only when D7=1
235     *     D4  Channel-interleaving granularity for tile-mapped region {BFineGranSize}
236     *         0:  64 B
237     *         1:  128 B
238     *     D[3:2] Channel-interleaving granularity for linearly mapped region {BCoarseGranSize}
239     *         00: 1KB
240     *         01: 2KB
241     *         10: 4KB
242     *         11: 1MB
243     *     D[1:0] reserved
244     *********************************************************************************************************/
245
246    /* Accelerator parameter Initialization */
247    if(( pXGI->Chipset == PCI_CHIP_XGIXG20 )||( pXGI->Chipset == PCI_CHIP_XGIXG21 )||( pXGI->Chipset == PCI_CHIP_XGIXG27 ))
248    {
249        pXGI->cmdQueueSize = VOLARI_CQSIZEXG20;
250    /* XgiMode = XG20_Mode ; */
251        PDEBUG(ErrorF(" ---XG20_Mode \n"));
252    }
253
254
255    pXGI->cmdQueueSizeMask = pXGI->cmdQueueSize - 1 ;
256    pXGI->pCQ_shareWritePort = &(pXGI->cmdQueue_shareWP_only2D);
257
258
259    /*
260     If FbDevExist, XFree86 driver use the 8MB only. The rest
261     frame buffer is used by other AP.
262     */
263
264    if( FbDevExist && (pXGI->Chipset != PCI_CHIP_XGIXG20 ) && (pXGI->Chipset != PCI_CHIP_XGIXG21 ) && (pXGI->Chipset != PCI_CHIP_XGIXG27 ) )
265    {
266        if( pScrn->videoRam < 8*1024 )
267        {
268            pXGI->cmdQueueOffset = 4*1024*1024 - pXGI->cmdQueueSize ;
269        }
270        else if( pScrn->videoRam < 16*1024 )
271        {
272            pXGI->cmdQueueOffset = 8*1024*1024 - pXGI->cmdQueueSize ;
273        }
274        else
275        {
276            pXGI->cmdQueueOffset = 13*1024*1024 - pXGI->cmdQueueSize ;
277        }
278    }
279    else
280    {
281        pXGI->cmdQueueOffset = (pScrn->videoRam)*1024 - pXGI->cmdQueueSize ;
282    }
283
284    pXGI->CursorOffset = pXGI->cmdQueueOffset - 64*1024 ;
285    PDEBUG4(ErrorF("pScrn->videoRam = %08lX pXGI->cmdQueueSize = %08lX\n",
286			pScrn->videoRam, pXGI->cmdQueueSize)) ;
287    PDEBUG4(ErrorF("pXGI->cmdQueueOffset = %08lX pXGI->CursorOffset = %08lX\n",
288		pXGI->cmdQueueOffset, pXGI->CursorOffset)) ;
289
290    pXGI->cmdQueueLen = 0 ;
291    pXGI->cmdQueueLenMin = 0x200 ;
292    pXGI->cmdQueueLenMax = pXGI->cmdQueueSize -  pXGI->cmdQueueLenMin ;
293
294    /*****************************************************************
295     * Dual Chip support put here                                    *
296     *****************************************************************/
297    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
298            "Detected DRAM type : %s\n", dramTypeStr);
299    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
300            "Detected memory clock : %3.3fMHz\n",
301            pXGI->MemClock/1000.0);
302    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
303            "Detected VRAM bus width is %d\n", pXGI->BusWidth);
304    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
305            "Detected Cmd Queue size is %d KB\n", pXGI->cmdQueueSize / 1024);
306    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
307            "Detected Cmd Queue Offset is %d\n", pXGI->cmdQueueOffset ) ;
308    XGI_InitHwDevInfo(pScrn);
309}
310
311static void
312xgiXG40_Setup(ScrnInfoPtr pScrn)
313{
314    static const char *const dramChannelStr[5] = {
315	"<invalid>", "Single", "Dual", "<invalid>", "Quad"
316    };
317
318    static const char *const dramTypeStr[4] = {
319	"DDR SDRAM",
320	"DDR2 SDRAM",
321	"DDR2x SDRAM",
322	""
323    };
324
325/*********************************************************************
326 * Setup
327 * Decide the following item of execution data:
328 *
329 * pXGI->BusWidth
330 * pXGI->videoRam (with KB unit)
331 * pXGI->CursorOffset (with Byte Unit)
332 * pXGI->cmdQueueSize (with Byte Unit)
333 * pXGI->cmdQueueSizeMask (with Byte Unit)
334 * pXGI->cmdQueueOffset (with Byte Unit)
335 * pXGI->cmdQueueLen = 0 ; // init value
336 * pXGI->cmdQueueLenMin = 0x200 ; // init value
337 * pXGI->cmdQueueLenMax = pXGI->cmdQueueSize -  pXGI->cmdQueueLenMin ;
338 *********************************************************************/
339
340    XGIPtr        pXGI = XGIPTR(pScrn);
341    unsigned int  ulMemConfig = 0;
342    unsigned mem_per_channel;
343    unsigned mem_channels = 1;
344    unsigned long ulDramType  = 0;
345
346    PDEBUG4(ErrorF("xgiXG40_Setup()\n")) ;
347
348    pXGI->MemClock = XG40Mclk(pXGI);
349
350    /* SR14 DRAM Size Register
351     *     Default value: XXh
352     *     D[7:4]    Memory size per channel {BChMemSize}
353     *         0011: 8 MB
354     *         0100: 16 MB
355     *         0101: 32 MB
356     *         0110: 64 MB
357     *         0111: 128 MB
358     *         1000: 256MB
359     *        others: reserved
360     *     D[3:2]    Number of  dram channels [1:0] {BChNum}
361     *         00: uni-channel
362     *         01: reserved
363     *         10: dual-channel
364     *         11: quad-channel
365     *     D1  Data width per channel selection {BDataWidth}
366     *         0: 32-bits
367     *         1: 64-bits
368     *     D0  Dram channel mapping {BReverseChMapping}
369     *         0: Normal mapping
370     *         1: Reversal mapping
371     *             Dual-channel: Logical channel A/B to physical channel B/A
372     *             Quad-channel: Logical channel A/B/C/D to physical channel
373     *                           C/D/A/B
374     */
375
376    outXGIIDXREG(XGISR, 0x5, 0x86) ;
377    inXGIIDXREG(XGISR, 0x14, ulMemConfig) ;
378
379    /* FIXME: Is this correct?  The SiS driver detects this differently
380     * FIXME: for XG20.
381     */
382    inXGIIDXREG(XGISR, 0x3A, ulDramType) ;
383
384    PDEBUG(ErrorF("xg40_Setup(): ulMemConfig = %02X\n",ulMemConfig)) ;
385    PDEBUG(ErrorF("xg40_Setup(): ulDramType = %02X\n",ulDramType)) ;
386
387    /* FIXME: Is this correct?  The SiS driver detects this differently
388     * FIXME: for XG20.
389     */
390    pXGI->BusWidth = (ulMemConfig & 0x02) ? 64 : 32;
391
392    mem_per_channel = ((ulMemConfig >> 4) >= 3)
393        ? (1 << (ulMemConfig >> 4)) * 1024
394        : 8 * 1024;
395
396
397    /* All XG20 family chips are single channel, so only test the channel
398     * count field on XG40 family chips.
399     */
400    if (pXGI->Chipset == PCI_CHIP_XGIXG40) {
401        /* Check the PCI revision field.  For whatever reason, rev. 2 XG40
402         * chips encode the DRAM channel count differently than other
403         * revisions.
404         */
405        if (pXGI->ChipRev == 2) {
406            switch ((ulMemConfig >> 2) & 0x1) {
407            case 1:
408                /* Dual channel */
409                mem_channels = 2;
410                break ;
411            }
412        }
413        else {
414            switch ((ulMemConfig >> 2) & 0x3) {
415            case 2:
416                /* Dual channel */
417                mem_channels = 2;
418                break ;
419            case 3:
420                /* Quad channel */
421                mem_channels = 4;
422                break ;
423            }
424        }
425    }
426
427    pScrn->videoRam = mem_per_channel * mem_channels;
428
429    /* SR15 DRAM Address Mapping Register
430     * Default value: XXh
431     *     D7  Channel  interleaving configuration { BChConfig }
432     *         0: Divide the whole memory  into 2/4 equal-sized regions , each mapped to one channel
433     *         1: Divide the whole memory into 2 regions according to BTilingSize[1:0] . The low-address region
434     *         will be channel-interleaved as per BFineGranSize; the high-address region will be channel-
435     *         interleaved  as per BCoarseGranSize[1:0]
436     *     D[6:5]    Memory size of tile-mapped region {BTilingSize}
437     *         00: 4 MB
438     *         01: 8 MB
439     *         10: 16 MB
440     *         11: 32 MB
441     *         The following bits are effective only when D7=1
442     *     D4  Channel-interleaving granularity for tile-mapped region {BFineGranSize}
443     *         0:  64 B
444     *         1:  128 B
445     *     D[3:2] Channel-interleaving granularity for linearly mapped region {BCoarseGranSize}
446     *         00: 1KB
447     *         01: 2KB
448     *         10: 4KB
449     *         11: 1MB
450     *     D[1:0] reserved
451     */
452
453    /* Accelerator parameter Initialization */
454
455    pXGI->cmdQueueSize = ((pXGI->Chipset == PCI_CHIP_XGIXG20)||(pXGI->Chipset == PCI_CHIP_XGIXG21||(pXGI->Chipset == PCI_CHIP_XGIXG27)))
456	? VOLARI_CQSIZEXG20 : VOLARI_CQSIZE;
457    pXGI->cmdQueueSizeMask = pXGI->cmdQueueSize - 1 ;
458    pXGI->pCQ_shareWritePort = &(pXGI->cmdQueue_shareWP_only2D);
459
460
461    /* If FbDevExist, X.org driver uses 8MB only. The rest of the framebuffer
462     * is used by the fbdev driver.
463     */
464    if (FbDevExist) {
465	/* FIXME: Is it even possible to have less than 8Mb of video memory?
466	 */
467        if (pScrn->videoRam < 8*1024) {
468            pXGI->cmdQueueOffset = 4*1024*1024 - pXGI->cmdQueueSize;
469        }
470	else if (pScrn->videoRam < 16*1024) {
471	    pXGI->cmdQueueOffset = 8*1024*1024 - pXGI->cmdQueueSize;
472	}
473        else {
474            pXGI->cmdQueueOffset = 13*1024*1024 - pXGI->cmdQueueSize;
475        }
476    }
477    else {
478        pXGI->cmdQueueOffset = (pScrn->videoRam)*1024 - pXGI->cmdQueueSize;
479    }
480
481    pXGI->CursorOffset = pXGI->cmdQueueOffset - 64*1024;
482    PDEBUG4(ErrorF("pScrn->videoRam = %08lX pXGI->cmdQueueSize = %08lX\n",
483			pScrn->videoRam, pXGI->cmdQueueSize)) ;
484    PDEBUG4(ErrorF("pXGI->cmdQueueOffset = %08lX pXGI->CursorOffset = %08lX\n",
485		pXGI->cmdQueueOffset, pXGI->CursorOffset)) ;
486
487    pXGI->cmdQueueLen = 0 ;
488    pXGI->cmdQueueLenMin = 0x200 ;
489    pXGI->cmdQueueLenMax = pXGI->cmdQueueSize -  pXGI->cmdQueueLenMin ;
490
491    /* Dual Chip support put here
492     */
493    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
494	       "Detected DRAM type : %s channel %s\n",
495	       dramChannelStr[mem_channels],
496	       dramTypeStr[(ulDramType & 0x02) >> 1]);
497    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
498            "Detected memory clock : %3.3fMHz\n",
499            pXGI->MemClock/1000.0);
500    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
501            "Detected VRAM bus width is %d\n", pXGI->BusWidth);
502    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
503            "Detected Cmd Queue size is %d KB\n", pXGI->cmdQueueSize / 1024);
504    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
505            "Detected Cmd Queue Offset is %d\n", pXGI->cmdQueueOffset ) ;
506    XGI_InitHwDevInfo(pScrn);
507}
508
509void
510XGISetup(ScrnInfoPtr pScrn)
511{
512    XGIPtr pXGI = XGIPTR(pScrn);
513
514    pXGI->Flags = 0;
515    pXGI->VBFlags = 0;
516
517	/* Jong 10/16/2007; merge code */
518    switch (pXGI->Chipset) {
519		case PCI_CHIP_XGIXG20:
520		case PCI_CHIP_XGIXG21:
521		case PCI_CHIP_XGIXG27:
522			xgiXG2X_Setup(pScrn);
523			break;
524
525		case PCI_CHIP_XGIXG40:
526		default:
527			xgiXG40_Setup(pScrn);
528			break;
529    }
530}
531
532/* Jong 01/07/2008; Force to disable 2D engine by SR3A[6]=1 */
533Bool ForceToDisable2DEngine(ScrnInfoPtr pScrn)
534{
535    XGIPtr pXGI ;
536	Bool   bReturn=FALSE;
537    CARD8  bForce;
538
539    pXGI = XGIPTR(pScrn);
540
541	if(pXGI->Chipset == PCI_CHIP_XGIXG21)
542	{
543	    inXGIIDXREG(XGISR, 0x3A, bForce) ;
544		bForce &= 0x40;
545
546		if(bForce == 0)
547			bReturn=FALSE;
548		else
549			bReturn=TRUE;
550	}
551	else
552	{
553		bReturn=FALSE;
554	}
555
556	return(bReturn);
557}
558
559Bool
560XGI_IsXG21(ScrnInfoPtr pScrn)
561{
562    XGIPtr pXGI = XGIPTR(pScrn);
563    Bool is_XG21 = FALSE;
564
565    if (pXGI->Chipset == PCI_CHIP_XGIXG20) {
566		int temp;
567
568        orXGIIDXREG(XGICR, Index_CR_GPIO_Reg3, GPIOG_EN);
569        inXGIIDXREG(XGICR, Index_CR_GPIO_Reg1, temp);
570
571		is_XG21 = ((temp & GPIOG_READ) != 0);
572    }
573
574    return is_XG21;
575}
576
577void
578XGI_InitHwDevInfo(ScrnInfoPtr pScrn)
579{
580    XGIPtr pXGI = XGIPTR(pScrn);
581    PXGI_HW_DEVICE_INFO pHwDevInfo = &pXGI->xgi_HwDevExt;
582    int i;
583
584    pHwDevInfo->pDevice = pXGI ;
585    pHwDevInfo->pjVirtualRomBase = pXGI->BIOS ;
586    pHwDevInfo->pjCustomizedROMImage = NULL ;
587    pHwDevInfo->pjVideoMemoryAddress = (UCHAR*)(pXGI->FbBase) ;
588    PDEBUG(ErrorF("pXGI->FbBase = 0x%08lx\n",(ULONG)(pXGI->FbBase))) ;
589    PDEBUG(ErrorF("pHwDevInfo->pjVideoMemoryAddress = 0x%08lx\n",(ULONG)(pHwDevInfo->pjVideoMemoryAddress))) ;
590    pHwDevInfo->ulVideoMemorySize = pXGI->FbMapSize ;
591    pHwDevInfo->pjIOAddress = pXGI->RelIO + 0x30 ;
592
593    switch (pXGI->Chipset) {
594    case PCI_CHIP_XGIXG40:
595        pHwDevInfo->jChipType = XG40 ;
596        break ;
597    case PCI_CHIP_XGIXG20:
598        pHwDevInfo->jChipType = XGI_IsXG21(pScrn)?XG21:XG20 ;
599        break ;
600    case PCI_CHIP_XGIXG27:
601    pHwDevInfo->jChipType = XG27;
602        break;
603    case PCI_CHIP_XGIXG21:
604	pHwDevInfo->jChipType = XG21;
605	break;
606    default:
607        pHwDevInfo->jChipType = XG40 ;
608        break ;
609    }
610
611    pHwDevInfo->jChipRevision = pXGI->ChipRev;
612    pHwDevInfo->ujVBChipID = VB_CHIP_UNKNOWN ;
613    pHwDevInfo->ulExternalChip = 0 ;
614
615    pHwDevInfo->ulCRT2LCDType = LCD_1024x768 ;
616    pHwDevInfo->bIntegratedMMEnabled = FALSE ;
617    pHwDevInfo->bSkipDramSizing = TRUE ;
618
619    pHwDevInfo->pSR = pXGI->SRList ;
620    pHwDevInfo->pCR = pXGI->CRList ;
621    pHwDevInfo->pQueryVGAConfigSpace = (PXGI_QUERYSPACE) bAccessVGAPCIInfo;
622
623    for( i = 0 ; i < ExtRegSize ; i++ ){
624        pHwDevInfo->pSR[i].jIdx = 0xFF ;
625        pHwDevInfo->pSR[i].jVal = 0xFF ;
626        pHwDevInfo->pCR[i].jIdx = 0xFF ;
627        pHwDevInfo->pCR[i].jVal = 0xFF ;
628    }
629
630    for( i = 0 ; i < VBIOS_VER_MAX_LENGTH ; i++ ){
631        pHwDevInfo -> szVBIOSVer[i] = '\0' ;
632    }
633
634
635    XGINew_InitVBIOSData(pHwDevInfo, pXGI->XGI_Pr);
636    PDEBUG(ErrorF("XGINew_InitVBIOSData(pHwDevInfo) done\n")) ;
637
638    ErrorF("XGI_InitVBIOSData  VBType = %x\n", pXGI->XGI_Pr->VBType);
639    XGI_New_GetVBType(pXGI->XGI_Pr, pHwDevInfo); //yilin
640    ErrorF("XGI_New_GetVBType  VBType = %x\n", pXGI->XGI_Pr->VBType);
641
642 //   pHwDevInfo->ujVBChipID = VB_CHIP_301 ; //yilin
643    if( pXGI->XGI_Pr->VBType & (VB_XGI301 | VB_XGI301B | VB_XGI301C))
644    {
645    PDEBUG(ErrorF("VB chip = 301 \n")) ;
646	 pHwDevInfo->ujVBChipID = VB_CHIP_301 ;
647    }
648    else if( pXGI->VBFlags & ( VB_XGI302B| VB_XGI302LV ))
649    {
650        pHwDevInfo->ujVBChipID = VB_CHIP_302 ;
651    }
652/*
653    else if (pXGI->VBFlags & VB_LVDS) {
654        pHwDevInfo->ulExternalChip |= 0x01 ;
655    }
656*/ //yilin
657
658
659    PDEBUG(ErrorF("pHwDevInfo->jChipType = %08lX done\n",pHwDevInfo->jChipType)) ;
660}
661
662Bool
663bAccessVGAPCIInfo(PXGI_HW_DEVICE_INFO pHwDevInfo, ULONG ulOffset, ULONG ulSet, CARD32 *pulValue)
664{
665    XGIPtr pXGI ;
666#ifdef XSERVER_LIBPCIACCESS
667    int err;
668#else
669    PCITAG pciDev;
670#endif
671
672    if (!pHwDevInfo || !pulValue) {
673        return FALSE;
674    }
675
676    pXGI = (XGIPtr)pHwDevInfo->pDevice ;
677#ifdef XSERVER_LIBPCIACCESS
678    if (ulSet) {
679	err = pci_device_cfg_write_u32(pXGI->PciInfo, *pulValue,
680				       ulOffset & ~3);
681    } else {
682	err = pci_device_cfg_read_u32(pXGI->PciInfo, (uint32_t *)pulValue,
683				       ulOffset & ~3);
684    }
685
686    return (err == 0);
687#else
688    pciDev = pXGI->PciTag ;
689
690    if (ulSet) {
691        pciWriteLong(pciDev, ulOffset&0xFFFFFFFc, *pulValue);
692    } else {
693        *pulValue = pciReadLong(pciDev, ulOffset&0xFFFFFFFc);
694    }
695
696    return TRUE ;
697#endif
698}
699