1706f2543Smrg			DDC.HOWTO
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3706f2543Smrg  This file describes how to add DDC support to a chipset driver.
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5706f2543Smrg1) DDC INITIALIZATION
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7706f2543Smrg   When implementing DDC in the driver one has the choice between
8706f2543Smrg   DDC1 and DDC2. 
9706f2543Smrg   DDC1 data is continuously transmitted by a DDC1 capable display 
10706f2543Smrg   device. The data is send serially over a data line; the Vsync 
11706f2543Smrg   signal serves as clock. Only one EDID 1.x data block can be 
12706f2543Smrg   transmitted using DDC1. Since transmission of an EDID1 block 
13706f2543Smrg   using a regular Vsync frequency would take up several seconds 
14706f2543Smrg   the driver can increase the Vsync frequency to up to 25 kHz as 
15706f2543Smrg   soon as it detects DDC1 activity on the data line.
16706f2543Smrg   DDC2 data is transmitted using the I2C protocol. This requires
17706f2543Smrg   an additional clock line. DDC2 is capable of transmitting EDID1
18706f2543Smrg   and EDID2 block as well as a VDIF block on display devices that 
19706f2543Smrg   support these.  
20706f2543Smrg   Display devices switch into the DDC2 mode as soon as they detect
21706f2543Smrg   activity on the DDC clock line. Once the are in DDC2 mode they
22706f2543Smrg   stop transmitting DDC1 signals until the next power cycle.
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24706f2543Smrg   Some graphics chipset configurations which are not capable of
25706f2543Smrg   DDC2 might still be able to read DDC1 data. Where available
26706f2543Smrg   DDC2 it is preferable. 
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28706f2543Smrg   All relevant prototypes and defines are in xf86DDC.h.
29706f2543Smrg   DDC2 additionally requires I2C support. The I2C prototypes
30706f2543Smrg   are in xf86i2c.h.
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32706f2543Smrg   DDC1 Support:
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34706f2543Smrg     The driver has to provide a read function which waits for the
35706f2543Smrg     end of the next Vsync signal and reads in and returns the status
36706f2543Smrg     of the DDC line:
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38706f2543Smrg     unsigned int XXX_ddc1Read(ScrnInfoPtr pScrn)
39706f2543Smrg     
40706f2543Smrg     Additionally a function is required to increase the Vsync
41706f2543Smrg     frequency to max. 25 kHz. 
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43706f2543Smrg     void XXX_ddc1SetSpeed(ScrnInfoPtr pScrn, xf86ddcSpeed speed)
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45706f2543Smrg     If the speed argument is DDC_FAST the function should increase
46706f2543Smrg     the Vsync frequency on DDC_SLOW it should restore the original
47706f2543Smrg     value. For convenience a generic ddc1SetSpeed() function is provided
48706f2543Smrg     in the vga module for VGA-like chipsets.     
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50706f2543Smrg     void vgaHWddc1SetSpeed(ScrnInfoPtr pScrn, sf86ddcSpeed speed).
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52706f2543Smrg     To read out the DDC1 data the driver should call 
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54706f2543Smrg     xf86MonPtr xf86DoEDID_DDC1(int scrnIndex, 
55706f2543Smrg                              void (*DDC1SetSpeed)(ScrnInfoPtr, xf86ddcSpeed),
56706f2543Smrg                              unsigned int (*DDC1Read)(ScrnInfoPtr))
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58706f2543Smrg     in PreInit(). DDC1SetSpeed is a pointer to the SetSpeed()
59706f2543Smrg     function, DDC1Read has to point to the DDC1 read function.
60706f2543Smrg     The function will return a pointer to the xf86Monitor structure
61706f2543Smrg     which contains all information retrieved by DDC.
62706f2543Smrg     NULL will be returned on failure.
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64706f2543Smrg   DDC2 Support
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66706f2543Smrg     To read out DDC2 information I2C has to be initialized first.
67706f2543Smrg     (See documentation for the i2c module). 
68706f2543Smrg     The function 
69706f2543Smrg     
70706f2543Smrg     xf86MonPtr xf86DoEDID_DDC2(int scrnIndex, I2CBusPtr pBus)
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72706f2543Smrg     is provided to read out and process DDC2 data. A pointer
73706f2543Smrg     to the I2CBusRec of the appropriate I2C Bus has to be passed
74706f2543Smrg     as the second argument.
75706f2543Smrg     The function will return a pointer to the xf86Monitor structure
76706f2543Smrg     which contains all information retrieved by DDC.
77706f2543Smrg     NULL will be returned on failure.
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79706f2543Smrg   Printing monitor parameters   
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81706f2543Smrg     To print out the information contained in the xf86Monitor
82706f2543Smrg     structure the function 
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84706f2543Smrg     xf86MonPtr xf86PrintEDID(xf86MonPtr monitor)
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86706f2543Smrg     is provided.
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88706f2543Smrg    Further processing of the xf86Monitor structure is not yet 
89706f2543Smrg    implemented. However, it is planned to use the information
90706f2543Smrg    about video modes, gamma values etc.
91706f2543Smrg    Therefore it is strongly recommended to read out DDC data
92706f2543Smrg    before any video mode processing is done.
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97706f2543Smrg$XFree86: xc/programs/Xserver/hw/xfree86/ddc/DDC.HOWTO,v 1.2 1998/12/06 13:30:39 dawes Exp $
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