1706f2543Smrg
2706f2543Smrg/* xf86DDC.h
3706f2543Smrg *
4706f2543Smrg * This file contains all information to interpret a standard EDIC block
5706f2543Smrg * transmitted by a display device via DDC (Display Data Channel). So far
6706f2543Smrg * there is no information to deal with optional EDID blocks.
7706f2543Smrg * DDC is a Trademark of VESA (Video Electronics Standard Association).
8706f2543Smrg *
9706f2543Smrg * Copyright 1998 by Egbert Eich <Egbert.Eich@Physik.TU-Darmstadt.DE>
10706f2543Smrg */
11706f2543Smrg
12706f2543Smrg#ifndef XF86_DDC_H
13706f2543Smrg# define XF86_DDC_H
14706f2543Smrg
15706f2543Smrg#include "edid.h"
16706f2543Smrg#include "xf86i2c.h"
17706f2543Smrg#include "xf86str.h"
18706f2543Smrg
19706f2543Smrg/* speed up / slow down */
20706f2543Smrgtypedef enum {
21706f2543Smrg  DDC_SLOW,
22706f2543Smrg  DDC_FAST
23706f2543Smrg} xf86ddcSpeed;
24706f2543Smrg
25706f2543Smrgtypedef void (* DDC1SetSpeedProc)(ScrnInfoPtr, xf86ddcSpeed);
26706f2543Smrg
27706f2543Smrgextern _X_EXPORT xf86MonPtr xf86DoEDID_DDC1(
28706f2543Smrg    int scrnIndex,
29706f2543Smrg    DDC1SetSpeedProc DDC1SetSpeed,
30706f2543Smrg    unsigned int (*DDC1Read)(ScrnInfoPtr)
31706f2543Smrg);
32706f2543Smrg
33706f2543Smrgextern _X_EXPORT xf86MonPtr xf86DoEDID_DDC2(
34706f2543Smrg   int scrnIndex,
35706f2543Smrg   I2CBusPtr pBus
36706f2543Smrg);
37706f2543Smrg
38706f2543Smrgextern _X_EXPORT xf86MonPtr xf86DoEEDID(int scrnIndex, I2CBusPtr pBus, Bool);
39706f2543Smrg
40706f2543Smrgextern _X_EXPORT xf86MonPtr xf86PrintEDID(
41706f2543Smrg    xf86MonPtr monPtr
42706f2543Smrg);
43706f2543Smrg
44706f2543Smrgextern _X_EXPORT xf86MonPtr xf86InterpretEDID(
45706f2543Smrg    int screenIndex, Uchar *block
46706f2543Smrg);
47706f2543Smrg
48706f2543Smrgextern _X_EXPORT xf86MonPtr xf86InterpretEEDID(
49706f2543Smrg    int screenIndex, Uchar *block
50706f2543Smrg);
51706f2543Smrg
52706f2543Smrgextern _X_EXPORT void
53706f2543Smrgxf86EdidMonitorSet(int scrnIndex, MonPtr Monitor, xf86MonPtr DDC);
54706f2543Smrg
55706f2543Smrgextern _X_EXPORT Bool xf86SetDDCproperties(
56706f2543Smrg    ScrnInfoPtr pScreen,
57706f2543Smrg    xf86MonPtr DDC
58706f2543Smrg);
59706f2543Smrg
60706f2543Smrgextern _X_EXPORT Bool
61706f2543Smrgxf86MonitorIsHDMI(xf86MonPtr mon);
62706f2543Smrg
63706f2543Smrgextern _X_EXPORT xf86MonPtr
64706f2543Smrgxf86DoDisplayID(int scrnIndex, I2CBusPtr pBus);
65706f2543Smrg
66706f2543Smrgextern _X_EXPORT void
67706f2543Smrgxf86DisplayIDMonitorSet(int scrnIndex, MonPtr mon, xf86MonPtr DDC);
68706f2543Smrg
69706f2543Smrgextern _X_EXPORT DisplayModePtr
70706f2543SmrgFindDMTMode(int hsize, int vsize, int refresh, Bool rb);
71706f2543Smrg
72706f2543Smrgextern _X_EXPORT const DisplayModeRec DMTModes[];
73706f2543Smrg
74706f2543Smrg/*
75706f2543Smrg * Quirks to work around broken EDID data from various monitors.
76706f2543Smrg */
77706f2543Smrgtypedef enum {
78706f2543Smrg    DDC_QUIRK_NONE = 0,
79706f2543Smrg    /* First detailed mode is bogus, prefer largest mode at 60hz */
80706f2543Smrg    DDC_QUIRK_PREFER_LARGE_60 = 1 << 0,
81706f2543Smrg    /* 135MHz clock is too high, drop a bit */
82706f2543Smrg    DDC_QUIRK_135_CLOCK_TOO_HIGH = 1 << 1,
83706f2543Smrg    /* Prefer the largest mode at 75 Hz */
84706f2543Smrg    DDC_QUIRK_PREFER_LARGE_75 = 1 << 2,
85706f2543Smrg    /* Convert detailed timing's horizontal from units of cm to mm */
86706f2543Smrg    DDC_QUIRK_DETAILED_H_IN_CM = 1 << 3,
87706f2543Smrg    /* Convert detailed timing's vertical from units of cm to mm */
88706f2543Smrg    DDC_QUIRK_DETAILED_V_IN_CM = 1 << 4,
89706f2543Smrg    /* Detailed timing descriptors have bogus size values, so just take the
90706f2543Smrg     * maximum size and use that.
91706f2543Smrg     */
92706f2543Smrg    DDC_QUIRK_DETAILED_USE_MAXIMUM_SIZE = 1 << 5,
93706f2543Smrg    /* Monitor forgot to set the first detailed is preferred bit. */
94706f2543Smrg    DDC_QUIRK_FIRST_DETAILED_PREFERRED = 1 << 6,
95706f2543Smrg    /* use +hsync +vsync for detailed mode */
96706f2543Smrg    DDC_QUIRK_DETAILED_SYNC_PP = 1 << 7,
97706f2543Smrg    /* Force single-link DVI bandwidth limit */
98706f2543Smrg    DDC_QUIRK_DVI_SINGLE_LINK = 1 << 8,
99706f2543Smrg} ddc_quirk_t;
100706f2543Smrg
101706f2543Smrgtypedef void (* handle_detailed_fn)(struct detailed_monitor_section *,void *);
102706f2543Smrg
103706f2543Smrgvoid xf86ForEachDetailedBlock(xf86MonPtr mon,
104706f2543Smrg                              handle_detailed_fn,
105706f2543Smrg                              void *data);
106706f2543Smrg
107706f2543Smrgddc_quirk_t
108706f2543Smrgxf86DDCDetectQuirks(int scrnIndex, xf86MonPtr DDC, Bool verbose);
109706f2543Smrg
110706f2543Smrgvoid xf86DetTimingApplyQuirks(struct detailed_monitor_section *det_mon,
111706f2543Smrg                              ddc_quirk_t quirks, int hsize, int vsize);
112706f2543Smrg
113706f2543Smrgtypedef void (* handle_video_fn)(struct cea_video_block *, void *);
114706f2543Smrg
115706f2543Smrgvoid xf86ForEachVideoBlock(xf86MonPtr,
116706f2543Smrg                           handle_video_fn,
117706f2543Smrg                           void *);
118706f2543Smrg
119706f2543Smrg#endif
120