1706f2543Smrg 2706f2543Smrg#include <xf86RamDac.h> 3706f2543Smrg 4706f2543Smrgextern _X_EXPORT unsigned long TIramdacCalculateMNPForClock(unsigned long RefClock, 5706f2543Smrg unsigned long ReqClock, char IsPixClock, unsigned long MinClock, 6706f2543Smrg unsigned long MaxClock, unsigned long *rM, unsigned long *rN, 7706f2543Smrg unsigned long *rP); 8706f2543Smrgextern _X_EXPORT RamDacHelperRecPtr TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs); 9706f2543Smrgextern _X_EXPORT void TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec); 10706f2543Smrgextern _X_EXPORT void TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, RamDacRegRecPtr RamDacRegRec); 11706f2543Smrgextern _X_EXPORT void TIramdac3026SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec); 12706f2543Smrgextern _X_EXPORT void TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr RamDacRegRec); 13706f2543Smrgextern _X_EXPORT void TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr); 14706f2543Smrgextern _X_EXPORT void TIramdacLoadPalette( ScrnInfoPtr pScrn, int numColors, int *indices, 15706f2543Smrg LOCO *colors, VisualPtr pVisual); 16706f2543Smrg 17706f2543Smrgtypedef void TIramdacLoadPaletteProc(ScrnInfoPtr, int, int *, LOCO *, 18706f2543Smrg VisualPtr); 19706f2543Smrgextern _X_EXPORT TIramdacLoadPaletteProc *TIramdacLoadPaletteWeak(void); 20706f2543Smrg 21706f2543Smrg#define TI3030_RAMDAC (VENDOR_TI << 16) | 0x00 22706f2543Smrg#define TI3026_RAMDAC (VENDOR_TI << 16) | 0x01 23706f2543Smrg 24706f2543Smrg/* 25706f2543Smrg * TI Ramdac registers 26706f2543Smrg */ 27706f2543Smrg 28706f2543Smrg#define TIDAC_rev 0x01 29706f2543Smrg#define TIDAC_ind_curs_ctrl 0x06 30706f2543Smrg#define TIDAC_byte_router_ctrl 0x07 31706f2543Smrg#define TIDAC_latch_ctrl 0x0f 32706f2543Smrg#define TIDAC_true_color_ctrl 0x18 33706f2543Smrg#define TIDAC_multiplex_ctrl 0x19 34706f2543Smrg#define TIDAC_clock_select 0x1a 35706f2543Smrg#define TIDAC_palette_page 0x1c 36706f2543Smrg#define TIDAC_general_ctrl 0x1d 37706f2543Smrg#define TIDAC_misc_ctrl 0x1e 38706f2543Smrg#define TIDAC_pll_addr 0x2c 39706f2543Smrg#define TIDAC_pll_pixel_data 0x2d 40706f2543Smrg#define TIDAC_pll_memory_data 0x2e 41706f2543Smrg#define TIDAC_pll_loop_data 0x2f 42706f2543Smrg#define TIDAC_key_over_low 0x30 43706f2543Smrg#define TIDAC_key_over_high 0x31 44706f2543Smrg#define TIDAC_key_red_low 0x32 45706f2543Smrg#define TIDAC_key_red_high 0x33 46706f2543Smrg#define TIDAC_key_green_low 0x34 47706f2543Smrg#define TIDAC_key_green_high 0x35 48706f2543Smrg#define TIDAC_key_blue_low 0x36 49706f2543Smrg#define TIDAC_key_blue_high 0x37 50706f2543Smrg#define TIDAC_key_ctrl 0x38 51706f2543Smrg#define TIDAC_clock_ctrl 0x39 52706f2543Smrg#define TIDAC_sense_test 0x3a 53706f2543Smrg#define TIDAC_test_mode_data 0x3b 54706f2543Smrg#define TIDAC_crc_remain_lsb 0x3c 55706f2543Smrg#define TIDAC_crc_remain_msb 0x3d 56706f2543Smrg#define TIDAC_crc_bit_select 0x3e 57706f2543Smrg#define TIDAC_id 0x3f 58706f2543Smrg 59706f2543Smrg/* These are pll values that are accessed via TIDAC_pll_pixel_data */ 60706f2543Smrg#define TIDAC_PIXEL_N 0x80 61706f2543Smrg#define TIDAC_PIXEL_M 0x81 62706f2543Smrg#define TIDAC_PIXEL_P 0x82 63706f2543Smrg#define TIDAC_PIXEL_VALID 0x83 64706f2543Smrg 65706f2543Smrg/* These are pll values that are accessed via TIDAC_pll_loop_data */ 66706f2543Smrg#define TIDAC_LOOP_N 0x90 67706f2543Smrg#define TIDAC_LOOP_M 0x91 68706f2543Smrg#define TIDAC_LOOP_P 0x92 69706f2543Smrg#define TIDAC_LOOP_VALID 0x93 70706f2543Smrg 71706f2543Smrg/* Direct mapping addresses */ 72706f2543Smrg#define TIDAC_INDEX 0xa0 73706f2543Smrg#define TIDAC_PALETTE_DATA 0xa1 74706f2543Smrg#define TIDAC_READ_MASK 0xa2 75706f2543Smrg#define TIDAC_READ_ADDR 0xa3 76706f2543Smrg#define TIDAC_CURS_WRITE_ADDR 0xa4 77706f2543Smrg#define TIDAC_CURS_COLOR 0xa5 78706f2543Smrg#define TIDAC_CURS_READ_ADDR 0xa7 79706f2543Smrg#define TIDAC_CURS_CTL 0xa9 80706f2543Smrg#define TIDAC_INDEXED_DATA 0xaa 81706f2543Smrg#define TIDAC_CURS_RAM_DATA 0xab 82706f2543Smrg#define TIDAC_CURS_XLOW 0xac 83706f2543Smrg#define TIDAC_CURS_XHIGH 0xad 84706f2543Smrg#define TIDAC_CURS_YLOW 0xae 85706f2543Smrg#define TIDAC_CURS_YHIGH 0xaf 86706f2543Smrg 87706f2543Smrg#define TIDAC_sw_reset 0xff 88706f2543Smrg 89706f2543Smrg/* Constants */ 90706f2543Smrg#define TIDAC_TVP_3026_ID 0x26 91706f2543Smrg#define TIDAC_TVP_3030_ID 0x30 92