105b261ecSmrg DDC.HOWTO 205b261ecSmrg 305b261ecSmrg This file describes how to add DDC support to a chipset driver. 405b261ecSmrg 505b261ecSmrg1) DDC INITIALIZATION 605b261ecSmrg 705b261ecSmrg When implementing DDC in the driver one has the choice between 805b261ecSmrg DDC1 and DDC2. 94642e01fSmrg DDC1 data is continuously transmitted by a DDC1 capable display 1005b261ecSmrg device. The data is send serially over a data line; the Vsync 1105b261ecSmrg signal serves as clock. Only one EDID 1.x data block can be 1205b261ecSmrg transmitted using DDC1. Since transmission of an EDID1 block 1305b261ecSmrg using a regular Vsync frequency would take up several seconds 1405b261ecSmrg the driver can increase the Vsync frequency to up to 25 kHz as 154642e01fSmrg soon as it detects DDC1 activity on the data line. 1605b261ecSmrg DDC2 data is transmitted using the I2C protocol. This requires 1705b261ecSmrg an additional clock line. DDC2 is capable of transmitting EDID1 1805b261ecSmrg and EDID2 block as well as a VDIF block on display devices that 1905b261ecSmrg support these. 2005b261ecSmrg Display devices switch into the DDC2 mode as soon as they detect 214642e01fSmrg activity on the DDC clock line. Once the are in DDC2 mode they 2205b261ecSmrg stop transmitting DDC1 signals until the next power cycle. 2305b261ecSmrg 2405b261ecSmrg Some graphics chipset configurations which are not capable of 2505b261ecSmrg DDC2 might still be able to read DDC1 data. Where available 264642e01fSmrg DDC2 it is preferable. 2705b261ecSmrg 2805b261ecSmrg All relevant prototypes and defines are in xf86DDC.h. 2905b261ecSmrg DDC2 additionally requires I2C support. The I2C prototypes 3005b261ecSmrg are in xf86i2c.h. 3105b261ecSmrg 3205b261ecSmrg DDC1 Support: 3305b261ecSmrg 3405b261ecSmrg The driver has to provide a read function which waits for the 3505b261ecSmrg end of the next Vsync signal and reads in and returns the status 3605b261ecSmrg of the DDC line: 3705b261ecSmrg 3805b261ecSmrg unsigned int XXX_ddc1Read(ScrnInfoPtr pScrn) 3905b261ecSmrg 404642e01fSmrg Additionally a function is required to increase the Vsync 4105b261ecSmrg frequency to max. 25 kHz. 4205b261ecSmrg 4305b261ecSmrg void XXX_ddc1SetSpeed(ScrnInfoPtr pScrn, xf86ddcSpeed speed) 4405b261ecSmrg 4505b261ecSmrg If the speed argument is DDC_FAST the function should increase 4605b261ecSmrg the Vsync frequency on DDC_SLOW it should restore the original 4705b261ecSmrg value. For convenience a generic ddc1SetSpeed() function is provided 4805b261ecSmrg in the vga module for VGA-like chipsets. 4905b261ecSmrg 5005b261ecSmrg void vgaHWddc1SetSpeed(ScrnInfoPtr pScrn, sf86ddcSpeed speed). 5105b261ecSmrg 5205b261ecSmrg To read out the DDC1 data the driver should call 5305b261ecSmrg 5405b261ecSmrg xf86MonPtr xf86DoEDID_DDC1(int scrnIndex, 5505b261ecSmrg void (*DDC1SetSpeed)(ScrnInfoPtr, xf86ddcSpeed), 5605b261ecSmrg unsigned int (*DDC1Read)(ScrnInfoPtr)) 5705b261ecSmrg 5805b261ecSmrg in PreInit(). DDC1SetSpeed is a pointer to the SetSpeed() 5905b261ecSmrg function, DDC1Read has to point to the DDC1 read function. 6005b261ecSmrg The function will return a pointer to the xf86Monitor structure 614642e01fSmrg which contains all information retrieved by DDC. 6205b261ecSmrg NULL will be returned on failure. 6305b261ecSmrg 6405b261ecSmrg DDC2 Support 6505b261ecSmrg 6605b261ecSmrg To read out DDC2 information I2C has to be initialized first. 6705b261ecSmrg (See documentation for the i2c module). 6805b261ecSmrg The function 6905b261ecSmrg 7005b261ecSmrg xf86MonPtr xf86DoEDID_DDC2(int scrnIndex, I2CBusPtr pBus) 7105b261ecSmrg 7205b261ecSmrg is provided to read out and process DDC2 data. A pointer 7305b261ecSmrg to the I2CBusRec of the appropriate I2C Bus has to be passed 7405b261ecSmrg as the second argument. 7505b261ecSmrg The function will return a pointer to the xf86Monitor structure 764642e01fSmrg which contains all information retrieved by DDC. 7705b261ecSmrg NULL will be returned on failure. 7805b261ecSmrg 7905b261ecSmrg Printing monitor parameters 8005b261ecSmrg 8105b261ecSmrg To print out the information contained in the xf86Monitor 8205b261ecSmrg structure the function 8305b261ecSmrg 8405b261ecSmrg xf86MonPtr xf86PrintEDID(xf86MonPtr monitor) 8505b261ecSmrg 8605b261ecSmrg is provided. 8705b261ecSmrg 8805b261ecSmrg Further processing of the xf86Monitor structure is not yet 894642e01fSmrg implemented. However, it is planned to use the information 9005b261ecSmrg about video modes, gamma values etc. 9105b261ecSmrg Therefore it is strongly recommended to read out DDC data 9205b261ecSmrg before any video mode processing is done. 9305b261ecSmrg 9405b261ecSmrg 9505b261ecSmrg 9605b261ecSmrg 9705b261ecSmrg$XFree86: xc/programs/Xserver/hw/xfree86/ddc/DDC.HOWTO,v 1.2 1998/12/06 13:30:39 dawes Exp $ 98