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History log of /src/sys/arch/aarch64/conf/files.aarch64
RevisionDateAuthorComments
 1.45  09-May-2024  pho port-arm/58194: Resurrect vmt(4) from bitrot

On this architecture vmt(4) used to search for a node "/hypervisor" in the
FDT and probed the VMware hypervisor call only when the node was
found. However, things appear to have changed and VMware no longer provides
the FDT node.

Since vmt(4) doesn't actually need to read anything from FDT, and the
hypervisor call logically resides in virtual CPUs themselves, it would be
better to attach it directly to cpu, just like how it's probed on x86.
 1.44  18-Feb-2024  andvar Change KDB to KGDB, including "sys/kgdb.h", which were likely meant to be defined.

Also comment out kgdb_machdep.c in files.aarch64, it doesn't exist yet.
 1.43  20-Apr-2023  skrll Provide a shared pmap_devmap implementation and convert all pmap_devmap
arrays to use DEVMAP_ENTRY{,_END}
 1.42  05-Nov-2022  skrll G/C
 1.41  03-Nov-2022  skrll Provide MI PMAP support on AARCH64
 1.40  28-Oct-2022  skrll MI PMAP EFI_RUNTIME support
 1.39  15-Oct-2022  jmcneill Use "non-posted" instead of "strongly ordered" to describe nGnRnE mappings

Rename the following defines:
- _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED to BUS_SPACE_MAP_NONPOSTED
- PMAP_DEV_SO to PMAP_DEV_NP
- LX_BLKPAG_ATTR_DEVICE_MEM_SO to LX_BLKPAG_ATTR_DEVICE_MEM_NP
Rename the following option:
- AARCH64_DEVICE_MEM_STRONGLY_ORDERED to AARCH64_DEVICE_MEM_NONPOSTED
 1.38  25-Jun-2022  jmcneill Remove GIC_SPLFUNCS.
 1.37  31-Jan-2022  ryo add support Hardware updates to Access flag and Dirty state (FEAT_HAFDBS)

- The DBM bit of the PTE is now used to determine if it is writable, and
the AF bit is treated entirely as a reference bit. A valid PTE is always
treated as readable. There can be no valid PTE that is not readable.
- LX_BLKPAG_OS_{READ,WRITE} are used only for debugging purposes,
and has been superseded by LX_BLKPAG_AF and LX_BLKPAG_DBM.
- Improve comment

The need for reference/modify emulation has been eliminated,
and access/permission faults have been reduced, however,
there has been little change in overall performance.
 1.36  25-Nov-2021  ryo add support COMPAT_LINUX32 for aarch64
 1.35  30-Oct-2021  jmcneill Implement gic_splraise and the gic_splx fast path in asm (armv8).
 1.34  10-Oct-2021  skrll Use sys/uvm/pmap/pmap_tlb.c on Aarch64 in the same way that some Arm, MIPS,
and some PPC kernels do. This removes the limitation of 256 processes on
CPUs with 8bit ASID field, e.g. Apple M1.

Additionally the following changes have been made

- removed a couple of unnecessary aarch64_tlbi_all calls
- removed any invalidation after freeing page tables due to
_pmap_sweep_pdp. This was never necessary afaict.
- all kernel mappings are marked global and userland mapping not-global.

Performance testing hasn't show a significant difference. The data here
is from building a kernel on an lx2k system with nvme.

before
1489.6u 400.4s 2:40.65 1176.5% 228+224k 0+32289io 57pf+0w
1482.6u 403.2s 2:38.49 1189.9% 228+222k 0+32274io 46pf+0w
1485.4u 402.2s 2:37.27 1200.2% 228+222k 0+32275io 12pf+0w

after
1493.9u 404.6s 2:37.50 1205.4% 227+221k 0+32265io 48pf+0w
1485.0u 408.0s 2:38.54 1194.0% 227+222k 0+32272io 36pf+0w
1484.3u 407.0s 2:35.88 1213.3% 228+224k 0+32268io 14pf+0w

>>> stats.ttest_ind([160.65,158.49,157.27], [157.5,158.54,155.88])
Ttest_indResult(statistic=1.1923622711296888, pvalue=0.2990182944606766)
>>>
 1.33  23-Sep-2021  ryo add support COMPAT_LINUX for aarch64
 1.32  06-Aug-2021  jmcneill Arm: Add support for SMC Calling Convention

Arm DEN0028 defines a calling mechanism used with Secure Monitor Call (SMC)
and Hypervisor Call (HVC) instructions. To discover SMCCC, we must:

1) Find the PSCI conduit (either via ACPI FADT, or Device Tree)
2) Use PSCI_VERSION to determine whether PSCI_FEATURES is supported
3) Call PSCI_FEATURES with SMCCC_VERSION to determine the implementation
version.
 1.31  24-Jul-2021  jmcneill aarch64: Remove empty source file and references to it.
 1.30  21-Oct-2020  christos branches: 1.30.6;
make process_machdep.c included always since it provides register i/o used by
sys_process_getlwpstatus.c which is always included.
 1.29  20-Oct-2020  christos harmonize process_machdep.c inclusion.
 1.28  29-Sep-2020  jmcneill Collapse all CPU_CORTEXA<n> options into CPU_CORTEX and do runtime
detection instead of ifdefs where required.
 1.27  12-Aug-2020  skrll Part III of ad's performance improvements for aarch64

- Assembly language stubs for mutex_enter() and mutex_exit().
 1.26  25-Jul-2020  riastradh Implement ChaCha with NEON on ARM.

XXX Needs performance measurement.
XXX Needs adaptation to arm32 neon which has half the registers.
 1.25  17-Jul-2020  ryo Add options PMAPBOOT_DEBUG to dump TTBR when pmapboot_enter().
Formerly DEBUG_MMU in locore.S, but there was a bit of confusion.
 1.24  29-Jun-2020  riastradh New permutation-based AES implementation using ARM NEON.

Also derived from Mike Hamburg's public-domain vpaes code.
 1.23  29-Jun-2020  riastradh Implement AES in kernel using ARMv8.0-AES on aarch64.
 1.22  18-Apr-2020  skrll PMAP_DEBUG has been deleted on arm
 1.21  13-Apr-2020  maxv Add KASAN-DMA support on aarch64, same as amd64. Discussed with skrll@.
 1.20  15-Feb-2020  skrll branches: 1.20.4;
Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}
 1.19  03-Feb-2020  ryo add support pmap_pv(9)

Patch originally from jmcneill@. thanks
 1.18  21-Jan-2020  skrll Small re-org. NFCI.
 1.17  15-Jan-2020  mrg port the arm64 cpu topology setup for big.little to arm.

rename arm64 cpu_do_topology() to arm_cpu_do_topology() and
call it from both arm cpu_attach().

replace both aarch64_set_topology() inline code in arm
cpu_attach() with new arm_cpu_do_topology(), which is called
by the arm64 locore as well (possibly not needed, which would
allow it to become static.)

not yet tested on a real big.little armv7 system. tested
on rockpro64 and pinebook pro.
 1.16  28-Dec-2019  jmcneill branches: 1.16.2;
Do not use Early Write Acknowledge for PCIe I/O and config space.
 1.15  27-Dec-2019  jmcneill Enable early write acknowledge for device memory mappings.
 1.14  20-Nov-2019  pgoyette Move all non-emulation-specific coredump code into the coredump module,
and remove all #ifdef COREDUMP conditional compilation. Now, the
coredump module is completely separated from the emulation modules, and
they can all be independently loaded and unloaded.

Welcome to 9.99.18 !
 1.13  27-Jan-2019  pgoyette branches: 1.13.4;
Merge the [pgoyette-compat] branch
 1.12  05-Dec-2018  jmcneill Add needs-flag to tprof_armv8.c
 1.11  05-Dec-2018  jmcneill Split armv7/armv8 tprof backend config logic from the fdt bus glue.
 1.10  18-Nov-2018  skrll Add CPU_THUNDERX which sets COHERENCY_UNIT and CACHE_LINE_SIZE to 128
 1.9  28-Oct-2018  jmcneill Add support for EFI runtime services on aarch64.
 1.8  18-Oct-2018  skrll Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively
 1.7  12-Oct-2018  ryo add initial support of COMPAT_NETBSD32 on AArch64.
arm ELF32 EABI binaries could be execute in AArch32 state on AArch64. A32 THUMB mode is not supported yet.
 1.6  06-Oct-2018  skrll Whitespace
 1.5  04-Oct-2018  ryo cleanup locore, and changed the way to map memories during boot.
- add functions bootpage_enter() and bootpage_alloc() to adapt various layout
of physical memory map. especially for 64bit physical memory layout.
pmapboot_alloc() allocates pagetable pages from _end[].
- changed to map only the required amount for PA=VA identity mapping
(kernel image, UART device, and FDT blob) with L2_BLOCK(2Mbyte).
- changing page permission for kernel image, and making KSEG mapping are done
at cpu_kernel_vm_init() instead of at locore.
- optimize PTE entries with PTE Contiguous bit. it is enabled on devmap only for now.

reviewed by skrll@, thanks.
 1.4  21-Sep-2018  jakllsch catch up to files.arm's recent "opt_console.h" changes
 1.3  01-Apr-2018  ryo branches: 1.3.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
 1.2  16-Aug-2017  nisimura branches: 1.2.2;
retire copyinout.S and fusu.S
 1.1  10-Aug-2014  matt branches: 1.1.4; 1.1.6;
Preliminary files for AARCH64 (64-bit ARM) support.
Enough for a distribution build.
 1.1.6.1  28-Aug-2017  skrll Sync with HEAD
 1.1.4.3  03-Dec-2017  jdolecek update from HEAD
 1.1.4.2  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.1.4.1  10-Aug-2014  tls file files.aarch64 was added on branch tls-maxphys on 2014-08-20 00:02:39 +0000
 1.2.2.6  26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.2.2.5  26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.2.2.4  20-Oct-2018  pgoyette Sync with head
 1.2.2.3  02-Oct-2018  pgoyette Use a hook callback to allow sparc fpu code to determine if a process
is running under sunos emulation (in which case, fpu cleanup uses a
different set of fpu_codes[]).
 1.2.2.2  30-Sep-2018  pgoyette Ssync with HEAD
 1.2.2.1  07-Apr-2018  pgoyette Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
 1.3.2.3  21-Apr-2020  martin Sync with HEAD
 1.3.2.2  08-Apr-2020  martin Merge changes from current as of 20200406
 1.3.2.1  10-Jun-2019  christos Sync with HEAD
 1.13.4.1  29-Dec-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #586):

sys/arch/arm/nvidia/tegra_pcie.c: revision 1.27
sys/arch/aarch64/aarch64/pmap.c: revision 1.57
sys/arch/aarch64/aarch64/locore.S: revision 1.48
sys/arch/aarch64/include/armreg.h: revision 1.29
sys/arch/aarch64/aarch64/pmap.c: revision 1.58
sys/arch/aarch64/aarch64/locore.S: revision 1.49
sys/arch/arm/acpi/acpipchb.c: revision 1.14
sys/arch/aarch64/aarch64/genassym.cf: revision 1.16
sys/arch/arm/acpi/acpi_machdep.c: revision 1.13
sys/arch/aarch64/include/pmap.h: revision 1.27
sys/arch/aarch64/aarch64/genassym.cf: revision 1.17
sys/arch/aarch64/include/pmap.h: revision 1.28
sys/arch/arm/fdt/pcihost_fdtvar.h: revision 1.3
sys/arch/arm/include/bus_defs.h: revision 1.14
sys/arch/aarch64/aarch64/bus_space.c: revision 1.9
sys/arch/arm/fdt/pcihost_fdt.c: revision 1.12
sys/arch/aarch64/conf/files.aarch64: revision 1.15
sys/arch/aarch64/conf/files.aarch64: revision 1.16
sys/arch/arm/rockchip/rk3399_pcie.c: revision 1.9

Enable early write acknowledge for device memory mappings.

Do not use Early Write Acknowledge for PCIe I/O and config space.
 1.16.2.3  29-Feb-2020  ad Sync with head.
 1.16.2.2  25-Jan-2020  ad Sync with head.
 1.16.2.1  17-Jan-2020  ad Sync with head.
 1.20.4.1  20-Apr-2020  bouyer Sync with HEAD
 1.30.6.1  01-Aug-2021  thorpej Sync with HEAD.

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