Update to support EFI runtime outside the kernel virtual address space
by creating an EFI RT pmap that can be activated / deactivated when
required.

Adds support for EFI RT to ARM_MMU_EXTENDED (ASID) 32-bit Arm machines.

On Arm64 the usage of pmapboot_enter is reduced and the mappings are
created much later in the boot process -- now in cpu_startup_hook.
Backward compatiblity for KVA mapped RT from old bootaa64.efi is
maintained.

Adding support to other platforms should be easier as a result.

Some KASAN fixes and tweaks

- don't access BSS variables when __md_early
- centralise the INIT_ARM_STACK_{SHIFT,SIZE} defines and create a new
INIT_ARM_TOTAL_STACK
- Only create L1PT entries in kasan_md_shadow_map_page if
arm32_kernel_vm_init hasn't created the L2PTs (and their L1PT entries)
- Add some comments to explain what's going on

Fix typo

Use the stack provided by armv6_start.S rather than svcstk. This saves
some bss too.

Spell initarm correctly in comments

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

branches: 1.38.2; 1.38.4;
Fix a comment

Make the initial svcstack is doubleword aligned if EABI.

branches: 1.36.2;
whitespace cleanup

branches: 1.35.2;
Write out register pairs for strd.

For load/store double, name the second register explicitly.

Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>

branches: 1.32.2;
If possible, use strd to clear .bss

Don't include <machine/param.h> since we should be getting that stuff from
"assym.h"

Fix missing registers (don't make then implicit).

Make sure SPSR[23:8] is set to a known valid value (taken from CPSR).

branches: 1.28.2;
Always cpu_info_store as the 3rd work unless TPIDRPRW_IS_CURLWP and then
it needs to be lwp0. Fix IGEPV2 boot problem.

Rename ARM options PROCESS_ID_IS_CUR{CPU,LWP} to TPIDRPRW_IS_CUR{CPU,LWP}
since TPIDRPRW is the cp15 register name.
Initialize it early in start along with CI_ARM_CPUID.
Remove other initializations.
We alays have ci_curlwp.
Enable TIPRPRW_IS_CURCPU in std.beagle.
[tested on a beaglboard (cortex-a8)]

Move the standard definitions of the {UND,IRQ,FIQ,ABT}_STACK_SIZE to
<arm32/machdep.h>
Move the extern for cpu_reset_address to the same file.
Add cpu_reset_address_paddr.
Kill cpu_reset_v4_MMU_disable.
if cpu_reset_address is NULL, then the MMU will be disabled.

branches: 1.25.8; 1.25.16;
Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.

branches: 1.24.12; 1.24.14; 1.24.16;
Use IF32_bits instead of I32_bit | F32_bit

branches: 1.23.2; 1.23.6;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.22.6; 1.22.8; 1.22.10;
Remove arm support for IPKDB.

It hasn't worked since arm was broken out from arm32 in Jan 2001, and
no-one has noticed or cared to fix it.

Update a comment.

Push a switchframe in dumpsys and cpu_switchto, but as dumpsys calls
other funcs a switchframe needs to be a multiple of 8 bytes. Stash sp as
well in the switchframe to bump it to 24bytes.

Setup the switchframe appropriately in cpu_lwp_fork.

Remove savectx - nothing uses it.

All of this make gdb's life much easier when dealing with crash dumps and
live kernels.

Reviewd by chris.

Add support for kcore headers to arm32 kernel core dumps.

The kcore code is based on i386's kcore header handling.

Having an asm stub for dumpsys, to dump the registers onto the stack, and
then call the C code to do the memory dump is based on amd64's core dump
code.

This allows a successful core dump on cats.

Part of fixing PR cats/18026.

branches: 1.18.46; 1.18.50; 1.18.52; 1.18.58; 1.18.60; 1.18.66;
merge ktrace-lwp.

foreach NOTEACHED make the comment say NOTREACHED

branches: 1.16.12;
Fix syntax error from 1.9. I guess IPKDB isn't used very much...

Uppercase CPU, plural is CPUs.

branches: 1.14.2;
Reinstate one change from rev. 1.12, but differently. Preload r2 with
0 before frobbing the control register, and use r2 in the ARMv4 TLB
flush.

Back out previous. There were several problems with the patch that
was checked in:
* It was not actually disabling the MMU, and so jumping to the
reset vector would happily cause a panic(), since it would be
the kernel's reset vector, not the ROM's.
* In the event the system was using high vectors, VECRELOC was not
getting cleared, which has the potential to wreak havoc when re-entering
the ROM.
* It was totally broken for CPUs < ARMv4; you still need to disable
the MMU on those, just need to skip the ARMv4 TLB flush.
* The code that was checked in would only work if the kernel is mapped
VA==PA. For systems where the kernel is NOT mapped VA==PA, you only
get the prefetch depth # of insns (2) after the MMU is turned off before
you have fix the PC.

Backing out the change fixes rebooting on several evbarm platforms.

Fix multiple bugs in the way we do the v4 MMU disable -- it was blasting way
too many bits (including some reserved ones) and was writing the wrong value
for the TLB flush.
Also, if the flag is off, don't write the control register!

make atomic_{set,clear}_bit() inline for arm32 ports, and
add <machine/atomic.h> for them.

branches: 1.10.2;
fix a bug sneaked into cpu_reset() in "- . - 8 purge"
(s/mov pc,lr/mov lr,pc/)

Instead of "add rd, pc, #foo - . - 8", use either "adr rd, foo" or (where
appropriate) "mov lr, pc". This makes things slightly less confusing and
ugly.

More local label fixups.

* Use local label names (.Lfoo vs. (Lfoo or foo))
* When moving from cpsr, use "cpsr" instead of "cpsr_all" (which is
provided, but doesn't make sense since mrs doesn't support fields
like msr does).

branches: 1.6.2;
Make a comment describe what the code actually does.

Always provide kernel_text.

* Clean up some comments/whitespace.
* Don't construct a fake trap frame and pass it to main(); that hasn't
been needed for some time.
* panic if main() returns.

Overhaul of the ARM cache code. This is mostly a simplification
pass. Rather than providing a whole slew of cache operations that
aren't ever used, distill them down to some useful primitives:

icache_sync_all Synchronize I-cache
icache_sync_range Synchronize I-cache range

dcache_wbinv_all Write-back and Invalidate D-cache
dcache_wbinv_range Write-back and Invalidate D-cache range
dcache_inv_range Invalidate D-cache range
dcache_wb_range Write-back D-cache range

idcache_wbinv_all Write-back and Invalidate D-cache,
Invalidate I-cache
idcache_wbinv_range Write-back and Invalidate D-cache,
Invalidate I-cache range

Note: This does not yet include an overhaul of the actual asm files
that implement the primitives. Instead, we've provided a safe default
for each CPU type, and the individual CPU types can now be optimized
one at a time.

* Share a common vector page between arm26 and arm32.
* Use a common set of exception handlers for all arm32 platforms.
* New FIQ framework based on discussions with Ben Harris, shared
between arm26 and arm32.

branches: 1.1.2; 1.1.8;
finish moving common arm32 bits out into arm/arm32.