Cross Reference: /src/sys/arch/arm/include/vfpreg.h

History log of /src/sys/arch/arm/include/vfpreg.h
Revision	Date	Author	Comments
1.17	07-Sep-2019	tnn	Cortex A12 is marketed as A17 but has a distinct part number observed on Rockchip RK3288
1.16	26-May-2017	jmcneill	branches: 1.16.10; Recognize Cortex-A57 FPU, GIC, and Generic Timer.
1.15	03-Mar-2016	skrll	Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs. While I'm here add some A57/A72 info as well. My RPI3 works with FB console - the uart needs some help with its clocks.
1.14	09-Feb-2015	slp	Add VFP IDs for QEMU's emulated Cortex-A15.
1.13	18-Mar-2014	matt	branches: 1.13.4; 1.13.6; Enable VFP on MV88SV58XX
1.12	24-Feb-2014	christos	consistency in include protection
1.11	23-Jan-2014	skrll	Fix typo in #define name
1.10	02-Aug-2013	matt	Add VFP_FPSCR_{QC,AHP} bits
1.9	20-Jun-2013	matt	branches: 1.9.2; Add support for the Cortex-A15 Neon/VFP unit
1.8	12-Feb-2013	matt	More fully document FPEXC register
1.7	12-Feb-2013	matt	Fix some FPEXC bit definitions
1.6	22-Sep-2012	matt	Only use CPACR register for ARM11 and CORTEX cores. Add VFP ids for other CORTEX CPUs.
1.5	22-Sep-2012	matt	Before testing for VFP, make sure CP10 is enabled. (And CP11 for Neon too).
1.4	16-Aug-2012	matt	branches: 1.4.2; Already uses _C someplace, use _CSUM instead
1.3	15-Aug-2012	matt	Add macros for all of the E and C flags in the FPSCR.
1.2	11-Aug-2012	matt	Full expand FPEXC and FPSCR definitions
1.1	15-Mar-2008	rearnsha	branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8; 1.1.10; 1.1.48; 1.1.56; VFP support.
1.1.56.1	21-Nov-2012	matt	Add aeabi.h, cpuconf.h, and vfpreg.h
1.1.48.2	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.1.48.1	30-Oct-2012	yamt	sync with head
1.1.10.2	03-Apr-2008	mjf	Sync with HEAD.
1.1.10.1	15-Mar-2008	mjf	file vfpreg.h was added on branch mjf-devfs2 on 2008-04-03 12:42:12 +0000
1.1.8.2	24-Mar-2008	keiichi	sync with head.
1.1.8.1	15-Mar-2008	keiichi	file vfpreg.h was added on branch keiichi-mipv6 on 2008-03-24 07:14:54 +0000
1.1.6.2	23-Mar-2008	matt	sync with HEAD
1.1.6.1	15-Mar-2008	matt	file vfpreg.h was added on branch matt-armv6 on 2008-03-23 02:03:55 +0000
1.1.4.2	21-Mar-2008	chris	Sync with head.
1.1.4.1	15-Mar-2008	chris	file vfpreg.h was added on branch chris-arm-intr-rework on 2008-03-21 13:34:41 +0000
1.1.2.2	17-Mar-2008	yamt	sync with head.
1.1.2.1	15-Mar-2008	yamt	file vfpreg.h was added on branch yamt-lazymbuf on 2008-03-17 09:14:15 +0000
1.4.2.5	03-Dec-2017	jdolecek	update from HEAD
1.4.2.4	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.4.2.3	23-Jun-2013	tls	resync from head
1.4.2.2	25-Feb-2013	tls	resync with head
1.4.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.9.2.2	18-May-2014	rmind	sync with head
1.9.2.1	28-Aug-2013	rmind	sync with head
1.13.6.3	28-Aug-2017	skrll	Sync with HEAD
1.13.6.2	19-Mar-2016	skrll	Sync with HEAD
1.13.6.1	06-Apr-2015	skrll	Sync with HEAD
1.13.4.1	26-Jul-2017	snj	Pull up following revision(s) (requested by jmcneill in ticket #1435): sys/arch/arm/arm32/cpu.c: 1.113 via patch sys/arch/arm/broadcom/bcm2835_bsc.c: 1.6 via patch sys/arch/arm/broadcom/bcm2835_plcom.c: 1.4 via patch sys/arch/arm/cortex/gtmr.c: 1.18 via patch sys/arch/arm/include/armreg.h: 1.110 via patch sys/arch/arm/include/vfpreg.h: 1.15 via patch sys/arch/arm/vfp/vfp_init.c: 1.50 via patch sys/arch/evbarm/rpi/rpi_machdep.c: 1.59, 1.70-1.72 via patch sys/arch/evbarm/rpi/vcprop.h: 1.16 Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs. While I'm here add some A57/A72 info as well. My RPI3 works with FB console - the uart needs some help with its clocks. -- Do invalidate the cache as RPI2 build with Clang can't fetch the memory config otherwise. -- Use the VC property mailbox to request the UART clock rate and use it appropriately Newer firmwares use 48MHz -- Disable BSC0 on Raspberry Pi 3 and Zero W boards. -- Interrupts are enabled before the timer is configured. Ensure that the timer is disabled when attaching so it doesn't go crazy between the time interrupts are enabled and clocks are initialized. My RPI3 makes it multi-user now. -- Enable UART0 (PL011) on GPIO header for Raspberry Pi 3 / Zero W
1.16.10.1	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411

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