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History log of /src/sys/arch/arm/marvell/files.marvell
RevisionDateAuthorComments
 1.18  07-Jan-2017  kiyohara Add support Marvell Dove.
Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.
 1.17  03-Jun-2015  hsuenaga branches: 1.17.2;
add new cryptographic accelerator driver 'mvxpsec.'

this driver controls CESA unit as same as mvcesa, but uses DMA engines and
does CBC operations, HMAC operations by hardware. about 2 kbytes of data
are processed at one. supported algorithms are:

- DES-CBC, 3DES-CBC, AES-CBC
- HMAC-SHA1, HMAC-MD5

non-CBC algorithm such as AES-GCM is not supported by CESA's acceleration
engine. mvcesa is still useful to implement such algorithms as combination of
accelerated block cipher and software chaining.
 1.16  03-Jun-2015  hsuenaga separate buffer management codes 'mvxpbm.c' from if_mvxpe.c.

the buffer management(ex. fill the rx descriptors/buffers) is done by H/W in
ARMADA XP/380, and is done by S/W in ARMADA 370. the H/W BM support is not yet
implemented, so all devices use the S/W management mode at this time.
 1.15  03-Jun-2015  hsuenaga move Marvell ARMADA SoC's device driver definitions from arm/marvell
to dev/marvell.
 1.14  03-May-2015  hsuenaga add new ethernet driver mvxpe for recent MARVELL's SoC after ARMADA/XP.
this driver supports 'counter mode', and is disabled by default.

ARMADA SoC family has new ethernet controller acceleration mode called
'enhanced mode' or 'counter mode.' it seems that backward compatibility mode
used by if_mvgbe is still working, but the specification of the old mode
is completely disappeared from SoC's reference manual.

I tested the driver using MIRABOX(ARMADA/370).
 1.13  18-Mar-2014  matt branches: 1.13.6;
defflag MVSOC_CONSOLE_EARLY
 1.12  18-Mar-2014  matt Add MEMSIZE to opt_mvsoc.h
 1.11  18-Mar-2014  matt Move defparam opt_mvsoc.h to more appropriate place.
 1.10  30-Sep-2013  kiyohara Add ARMADAXP into opt_mvsoc.h.
And add mv78xx0.c. However not test long time.
 1.9  29-Aug-2013  kiyohara Fix build failed with ofppc.
Move 'attach mvspi at mvsoc' to arch/arm/marvell/files.marvell.
 1.8  29-May-2013  rkujawa branches: 1.8.2;
Add support for Armada XP PIC.

Obtained from Marvell, Semihalf.
 1.7  01-Aug-2012  kiyohara branches: 1.7.2;
Add mvsocts.
 1.6  27-Jul-2012  kiyohara Add mvcesa.
 1.5  19-Jun-2012  hans Add support for the watchdog timer in mvsoctmr.
Tested on DreamPlug system.
 1.4  12-Mar-2011  nonaka branches: 1.4.4; 1.4.10;
mvsoc needs pic_splfuncs.
 1.3  05-Mar-2011  matt branches: 1.3.2;
Add contributed Marvell Kirkwood RTC driver from Brett Slager
Fixes PR 44004
 1.2  06-Oct-2010  kiyohara branches: 1.2.2; 1.2.4; 1.2.6;
Comment-out mvcesa. It not exists now.
 1.1  03-Oct-2010  kiyohara Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood)
Discovery Innovation not yet.
 1.2.6.1  06-Jun-2011  jruoho Sync with HEAD.
 1.2.4.2  22-Oct-2010  uebayasi Sync with HEAD (-D20101022).
 1.2.4.1  06-Oct-2010  uebayasi file files.marvell was added on branch uebayasi-xip on 2010-10-22 09:23:11 +0000
 1.2.2.2  09-Oct-2010  yamt sync with head
 1.2.2.1  06-Oct-2010  yamt file files.marvell was added on branch yamt-nfs-mp on 2010-10-09 03:31:39 +0000
 1.3.2.4  21-Apr-2011  rmind sync with head
 1.3.2.3  06-Mar-2011  rmind sync with head (and fix few botches with this)
 1.3.2.2  05-Mar-2011  rmind sync with head
 1.3.2.1  05-Mar-2011  rmind file files.marvell was added on branch rmind-uvmplock on 2011-03-05 20:49:37 +0000
 1.4.10.1  13-Jan-2013  bouyer Pull up following revision(s) (requested by riz in ticket #770):
sys/arch/arm/marvell/files.marvell: revision 1.5
sys/arch/arm/marvell/mvsoctmr.c: revision 1.4
sys/arch/arm/marvell/mvsoctmr.c: revision 1.5
sys/arch/arm/marvell/mvsoctmr.c: revision 1.6
sys/arch/arm/marvell/mvsoctmr.c: revision 1.7
Add support for the watchdog timer in mvsoctmr.
Tested on DreamPlug system.
When disabling watchdog timer, do not set the counter to 0.
Having the watchdog counter at 0 and having WDRstOutEn set to 1 causes
immediate watchdog reset on my 88F5182 A2.
Remove duplicate global variable.
The maximum watchdog period is dependant on mvTclk; calculate at runtime.
This gets the maximum period up to 25 seconds at 166⅔MHz mvTclk.
 1.4.4.2  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.4.4.1  30-Oct-2012  yamt sync with head
 1.7.2.3  03-Dec-2017  jdolecek update from HEAD
 1.7.2.2  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.7.2.1  23-Jun-2013  tls resync from head
 1.8.2.1  18-May-2014  rmind sync with head
 1.13.6.2  05-Feb-2017  skrll Sync with HEAD
 1.13.6.1  06-Jun-2015  skrll Sync with HEAD
 1.17.2.1  20-Mar-2017  pgoyette Sync with HEAD

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