Cross Reference: /src/sys/arch/arm/marvell/mvsocreg.h

History log of /src/sys/arch/arm/marvell/mvsocreg.h
Revision	Date	Author	Comments
1.14	07-Jan-2025	andvar	Fix typos in the word 'Control' in comments.
1.13	07-Jan-2017	kiyohara	branches: 1.13.52; Add support Marvell Dove. Also <SoC>_intr_bootstrap() rename to <SoC>_bootstrap(). And SoC init func, getclk into that.
1.12	03-Jun-2015	hsuenaga	branches: 1.12.2; dump Mbus settins on boot if AV_VERBOSE or AV_DEBUG is enabled.
1.11	19-May-2015	hsuenaga	fix Marvell Coherency Barrier register address. configure coherency bus maintance broadcast using MPIDR. we need to configure this regardless of 'options MULTIPROCESSOR.'
1.10	14-May-2015	hsuenaga	add synchronization barrier for AURORA_IO_CACHE_COHERENCY. cleanup MARVELL L2 cache code.
1.9	17-Feb-2014	kiyohara	branches: 1.9.6; Add some MVSOC_MLMB_ definitions for supporting DDR3.
1.8	23-Dec-2013	kiyohara	Support to check the clock gating for Armada XP in armadaxp.c. Also move the checking for clock gate of Kirkwood into kirkwood.c.
1.7	23-Dec-2013	kiyohara	Move Misc Registers from mvsocreg.h to armadaxpreg.h. These registers only Armada XP. The misc_base initializes in initarm() instead of mvsoc_bootstrap().
1.6	20-Nov-2013	kiyohara	Add defines for MISC registers.
1.5	30-Sep-2013	kiyohara	Remove #ifdef ARMADAXP. It is OK !ARMADAXP.
1.4	29-May-2013	rkujawa	branches: 1.4.2; Add support for mvsoc-based Armada XP peripherals. Obtained from Marvell, Semihalf.
1.3	19-Oct-2012	msaitoh	Add CLKGATING_BIT for some devices. This change prevent some boards that a device's clock is stopped from hangup.
1.2	01-Feb-2011	jakllsch	branches: 1.2.2; 1.2.6; 1.2.12; 1.2.16; Address 3rd issue in PR#43990. Different implementation but same method as suggested.
1.1	03-Oct-2010	kiyohara	branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8; Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood) Discovery Innovation not yet.
1.1.8.1	08-Feb-2011	bouyer	Sync with HEAD
1.1.6.1	06-Jun-2011	jruoho	Sync with HEAD.
1.1.4.2	22-Oct-2010	uebayasi	Sync with HEAD (-D20101022).
1.1.4.1	03-Oct-2010	uebayasi	file mvsocreg.h was added on branch uebayasi-xip on 2010-10-22 09:23:12 +0000
1.1.2.2	09-Oct-2010	yamt	sync with head
1.1.2.1	03-Oct-2010	yamt	file mvsocreg.h was added on branch yamt-nfs-mp on 2010-10-09 03:31:40 +0000
1.2.16.4	03-Dec-2017	jdolecek	update from HEAD
1.2.16.3	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.2.16.2	23-Jun-2013	tls	resync from head
1.2.16.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.2.12.1	11-Dec-2012	riz	sys/arch/arm/marvell/mvsoc.c patch sys/arch/arm/marvell/mvsocreg.h patch Add CLKGATING_BIT, enable it for some 88F6281 devices, and don't configure devices if their clock is disabled. [msaitoh, ticket #737]
1.2.6.2	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.2.6.1	30-Oct-2012	yamt	sync with head
1.2.2.2	05-Mar-2011	rmind	sync with head
1.2.2.1	01-Feb-2011	rmind	file mvsocreg.h was added on branch rmind-uvmplock on 2011-03-05 20:49:37 +0000
1.4.2.1	18-May-2014	rmind	sync with head
1.9.6.2	05-Feb-2017	skrll	Sync with HEAD
1.9.6.1	06-Jun-2015	skrll	Sync with HEAD
1.12.2.1	20-Mar-2017	pgoyette	Sync with HEAD
1.13.52.1	02-Aug-2025	perseant	Sync with HEAD

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