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mvsocreg.h revision 1.10 
      1 /*	$NetBSD: mvsocreg.h,v 1.10 2015/05/14 05:39:32 hsuenaga Exp $	*/
      2 /*
      3  * Copyright (c) 2007, 2008 KIYOHARA Takashi
      4  * All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     17  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
     24  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25  * POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 
     28 #ifndef _MVSOCREG_H_
     29 #define _MVSOCREG_H_
     30 
     31 #define MVSOC_UNITID_MASK		0xf
     32 #define MVSOC_UNITID_DDR		0x0	/* DDR registers */
     33 #define MVSOC_UNITID_DEVBUS		0x1	/* Device Bus registers */
     34 #define MVSOC_UNITID_MLMB		0x2	/* Mbus-L to Mbus Bridge reg */
     35 #define MVSOC_UNITID_PEX		0x4	/* PCI Express Interface reg */
     36 
     37 
     38 /*
     39  * Physical address of integrated peripherals
     40  */
     41 
     42 #define UNITID2PHYS(uid)	((MVSOC_UNITID_ ## uid) << 16)
     43 
     44 /*
     45  * DDR SDRAM Controller Registers
     46  */
     47 #define MVSOC_DDR_BASE		(UNITID2PHYS(DDR))	/* 0x00000 */
     48 
     49 /* DDR SDRAM Contriller Address Decode Registers */
     50 #define MVSOC_DSC_BASE			0x01500	/* DDR SDRAM Ctrl Addr Reg */
     51 #define MVSOC_DSC_NCS			4
     52 #define MVSOC_DSC_CSBAR(x)		((x) * 8)
     53 #define MVSOC_DSC_CSBAR_BASE_MASK	0xff000000
     54 #define MVSOC_DSC_CSSR(x)		((x) * 8 + 4)
     55 #define MVSOC_DSC_CSSR_WINEN		0x00000001
     56 #define MVSOC_DSC_CSSR_SIZE_MASK	0xff000000
     57 
     58 /*
     59  * Device Bus
     60  */
     61 #define MVSOC_DEVBUS_BASE	(UNITID2PHYS(DEVBUS))	/* 0x10000 */
     62 
     63 /*
     64  * General Purpose Port Registers
     65  */
     66 #define MVSOC_GPP_BASE		(MVSOC_DEVBUS_BASE + 0x0100)
     67 
     68 /*
     69  * Two-Wire Serial Interface Registers
     70  */
     71 #define MVSOC_TWSI_BASE		(MVSOC_DEVBUS_BASE + 0x1000)
     72 
     73 /*
     74  * UART Interface Registers
     75  */
     76 				/* NS16550 compatible */
     77 #define MVSOC_COM0_BASE		(MVSOC_DEVBUS_BASE + 0x2000)
     78 #define MVSOC_COM1_BASE		(MVSOC_DEVBUS_BASE + 0x2100)
     79 
     80 /*
     81  * Mbus-L to Mbus Bridge Registers
     82  */
     83 #define MVSOC_MLMB_BASE		(UNITID2PHYS(MLMB))	/* 0x20000 */
     84 
     85 /* CPU Address Map Registers */
     86 #define MVSOC_MLMB_WCR(w)		  ((w) < 8 ? ((w) << 4) + 0x0 :\
     87 						     (((w) - 8) << 3) + 0x90)
     88 #define MVSOC_MLMB_WCR_WINEN			(1 << 0)
     89 #define MVSOC_MLMB_WCR_TARGET(t)		(((t) & 0xf) << 4)
     90 #define MVSOC_MLMB_WCR_ATTR(a)			(((a) & 0xff) << 8)
     91 #define MVSOC_MLMB_WCR_SIZE_MASK		0xffff0000
     92 #define MVSOC_MLMB_WCR_SIZE(s)		  (((s) - 1) & MVSOC_MLMB_WCR_SIZE_MASK)
     93 #define MVSOC_MLMB_WBR(w)		  ((w) < 8 ? ((w) << 4) + 0x4 :\
     94 						     (((w) - 8) << 3) + 0x94)
     95 #define MVSOC_MLMB_WBR_BASE_MASK		0xffff0000
     96 #define MVSOC_MLMB_WRLR(w)		  (((w) << 4) + 0x8)
     97 #define MVSOC_MLMB_WRLR_REMAP_MASK		0xffff0000
     98 #define MVSOC_MLMB_WRHR(w)		  (((w) << 4) + 0xc)
     99 #define MVSOC_MLMB_IRBAR		  0x080 /* Internal regs Base Address */
    100 #define MVSOC_MLMB_IRBAR_BASE_MASK		0xfff00000
    101 
    102 /* CPU Control and Status Registers */
    103 #define MVSOC_MLMB_CPUCR		  0x100	/* CPU Configuration Register */
    104 #define MVSOC_MLMB_CPUCSR		  0x104	/* CPU Control/Status Register*/
    105 #define MVSOC_MLMB_RSTOUTNMASKR		  0x108 /* RSTOUTn Mask Register */
    106 #define MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN    (1 << 2)
    107 #define MVSOC_MLMB_RSTOUTNMASKR_WDRSTOUTEN      (1 << 1)
    108 #define MVSOC_MLMB_RSTOUTNMASKR_PEXRSTOUTEN     (1 << 0)
    109 #define MVSOC_MLMB_SSRR			  0x10c	/* System Soft Reset Register */
    110 #define MVSOC_MLMB_SSRR_SYSTEMSOFTRST           (1 << 0)
    111 #define MVSOC_MLMB_MLMBICR		  0x110	/*Mb-L to Mb Bridge Intr Cause*/
    112 #define MVSOC_MLMB_MLMBIMR		  0x114	/*Mb-L to Mb Bridge Intr Mask */
    113 
    114 #define MVSOC_MLMB_CLKGATING		  0x11c	/* Clock Gating Control */
    115 #define MVSOC_MLMB_CLKGATING_LNR	  (1 << 13) /* Load New Ratio */
    116 #define MVSOC_MLMB_CLKGATING_GPH	  (1 << 12) /* Go To Power Half */
    117 #define MVSOC_MLMB_CLKGATING_GPS	  (1 << 11) /* Go To Power Save */
    118 #define MVSOC_MLMB_CLKGATING_CR		  (1 << 10) /* Production Realignment */
    119 #define MVSOC_MLMB_CLKGATING_BIT(n)	  (1 << (n))
    120 
    121 #define MVSOC_MLMB_L2CFG		  0x128	/* L2 Cache Config */
    122 
    123 #define MVSOC_MLMB_NWIN			  4
    124 #define MVSOC_MLMB_WINBAR(w)		  (((w) << 3) + 0x180)
    125 #define MVSOC_MLMB_WINBAR_BASE_MASK		0xff000000
    126 #define MVSOC_MLMB_WINCR(w)		  (((w) << 3) + 0x184)
    127 #define MVSOC_MLMB_WINCR_EN			(1 << 0)
    128 #define MVSOC_MLMB_WINCR_WINCS(x)		(((x) & 0x1c) >> 2)
    129 #define MVSOC_MLMB_WINCR_SIZE_MASK		0xff000000
    130 
    131 /* Coherent Fabric Control and Status */
    132 #define MVSOC_MLMB_CFU_CTRL		0x200
    133 #define MVSOC_MLMB_CFU_CTRL_PROP_ERR	(0x1 << 8)
    134 #define MVSOC_MLMB_CFU_CTRL_SNOOP_CPU0	(0x1 << 24)
    135 
    136 #define MVSOC_MLMB_CFU_CFG		0x228
    137 #define MVSOC_MLMB_CFU_CFG_L2_NOTIFY	(0x1 << 16)
    138 
    139 /* CIB registers offsets */
    140 #define MVSOC_MLMB_CIB_CTRL_CFG			0x280
    141 #define MVSOC_MLMB_CIB_CTRL_CFG_WB_EN		(0x1 << 0)
    142 #define MVSOC_MLMB_CIB_CTRL_CFG_STOP		(0x1 << 9)
    143 #define MVSOC_MLMB_CIB_CTRL_CFG_IGN_SHARE	(0x2 << 10)
    144 #define MVSOC_MLMB_CIB_CTRL_CFG_EMPTY		(0x1 << 13)
    145 
    146 /* CIB barrier register */
    147 #define MVSOC_MLMB_CIB_BARRIER			0x1810
    148 #define MVSOC_MLMB_CIB_BARRIER_TRIGGER		(0x1 << 0)
    149 
    150 #define MVSOC_TMR_BASE		(MVSOC_MLMB_BASE + 0x0300)
    151 
    152 /* CPU Doorbell Registers */
    153 #define MVSOC_MLMB_H2CDR		  0x400	/* Host-to-CPU Doorbell */
    154 #define MVSOC_MLMB_H2CDMR		  0x404	/* Host-to-CPU Doorbell Mask */
    155 #define MVSOC_MLMB_C2HDR		  0x408	/* CPU-to-Host Doorbell */
    156 #define MVSOC_MLMB_C2HDMR		  0x40c	/* CPU-to-Host Doorbell Mask */
    157 
    158 /* Local to System Bridge Interrupt {Cause,Mask} Register bits */
    159 #define MVSOC_MLMB_MLMBI_CPUSELFINT		0
    160 #define MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ	1
    161 #define MVSOC_MLMB_MLMBI_CPUTIMER1INTREQ	2
    162 #define MVSOC_MLMB_MLMBI_CPUWDTIMERINTREQ	3
    163 #define MVSOC_MLMB_MLMBI_ACCESSERR		4
    164 #define MVSOC_MLMB_MLMBI_BIT64ERR		5
    165 #define MVSOC_MLMB_MLMBI_CPUTIMER2INTREQ	6
    166 #define MVSOC_MLMB_MLMBI_CPUTIMER3INTREQ	7
    167 
    168 #define MVSOC_MLMB_MLMBI_NIRQ			8
    169 
    170 /*
    171  * PCI-Express Interface Registers
    172  */
    173 #define MVSOC_PEX_BASE		(UNITID2PHYS(PEX))	/* 0x40000 */
    174 
    175 #endif	/* _MVSOCREG_H_ */
    176