Cross Reference: /src/sys/arch/arm/marvell/mvsoctmrreg.h

History log of /src/sys/arch/arm/marvell/mvsoctmrreg.h
Revision	Date	Author	Comments
1.4	17-Feb-2014	kiyohara	Add comment 'Armada XP only' to 25MHz bit. Also it is documented to errata?
1.3	14-Oct-2013	kiyohara	Add timer 2 and 3 for Discovery Innovation.
1.2	01-May-2013	rkujawa	branches: 1.2.4; Add support for timers on Armada XP. Obtained from Marvell, Semihalf.
1.1	03-Oct-2010	kiyohara	branches: 1.1.2; 1.1.4; 1.1.10; 1.1.14; 1.1.24; Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood) Discovery Innovation not yet.
1.1.24.2	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.1.24.1	23-Jun-2013	tls	resync from head
1.1.14.1	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.1.10.2	05-Mar-2011	rmind	sync with head
1.1.10.1	03-Oct-2010	rmind	file mvsoctmrreg.h was added on branch rmind-uvmplock on 2011-03-05 20:49:37 +0000
1.1.4.2	22-Oct-2010	uebayasi	Sync with HEAD (-D20101022).
1.1.4.1	03-Oct-2010	uebayasi	file mvsoctmrreg.h was added on branch uebayasi-xip on 2010-10-22 09:23:12 +0000
1.1.2.2	09-Oct-2010	yamt	sync with head
1.1.2.1	03-Oct-2010	yamt	file mvsoctmrreg.h was added on branch yamt-nfs-mp on 2010-10-09 03:31:40 +0000
1.2.4.1	18-May-2014	rmind	sync with head

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