Home | History | Annotate | Line # | Download | only in marvell
mvsoctmrreg.h revision 1.4 
      1 /*	$NetBSD: mvsoctmrreg.h,v 1.4 2014/02/17 05:11:25 kiyohara Exp $	*/
      2 /*
      3  * Copyright (c) 2007 KIYOHARA Takashi
      4  * All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     17  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
     24  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25  * POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 #ifndef _MVSOCTMRREG_H_
     28 #define _MVSOCTMRREG_H_
     29 
     30 #define MVSOCTMR_SIZE		0x100
     31 
     32 #define MVSOCTMR_CTCR		0x00		/* CPU Timers Control */
     33 #define MVSOCTMR_TESR		0x04		/* CPU Timers Event Status */
     34 #define MVSOCTMR_RELOAD(n)	(0x10 + (n) * 8)/* CPU Timer(n) Reload */
     35 #define MVSOCTMR_TIMER(n)	(0x14 + (n) * 8)/* CPU Timer(n) */
     36 
     37 #define MVSOCTMR_TIMER0		0
     38 #define MVSOCTMR_TIMER1		1
     39 #define MVSOCTMR_WATCHDOG	2
     40 #define MVSOCTMR_TIMER2		4	/* Discovery Innovation only */
     41 #define MVSOCTMR_TIMER3		5	/* Discovery Innovation only */
     42 
     43 /* CPU Timers Control Register (MVSOCTMR_CTCR) */
     44 #define MVSOCTMR_CTCR_CPUTIMEREN(n)	(1 << ((n) * 2))
     45 #define MVSOCTMR_CTCR_CPUTIMERAUTO(n)	(1 << ((n) * 2 + 1))
     46 #define MVSOCTMR_CTCR_25MHZEN(n)	(1 << ((n) + 11)) /* Armada XP only */
     47 
     48 #endif	/* !_MVSOCTMRREG_H_ */
     49