Cross Reference: /src/sys/arch/arm/nvidia/tegra

History log of /src/sys/arch/arm/nvidia/tegra_ahcisata.c
Revision	Date	Author	Comments
1.18	27-Jan-2021	thorpej	Rename of_match_compat_data() to of_compatible_match(). Similarly, rename of_search_compatible() to of_compatible_lookup(). Standardize on of_compatible_match() for driver matching, and adapt all call sites.
1.17	27-Jan-2021	thorpej	Use DEVICE_COMPAT_EOL.
1.16	25-Jan-2021	thorpej	Since we're using designated initialisers for compat data, we should use a completely empty initializer for the sentinel.
1.15	18-Jan-2021	thorpej	Remove "struct of_compat_data" and replace its usage with "struct device_compatible_entry"; they are ABI-compatible. Fix several "loses const qualifier" bugs encountered during this conversion.
1.14	15-Jan-2021	jmcneill	use fdtbus_intr_establish_xname
1.13	28-Dec-2020	jmcneill	Remove the AHCI_QUIRK_SKIP_RESET quirk now that the underlying issue is fixed.
1.12	14-Dec-2018	skrll	branches: 1.12.4; 1.12.12; Support SATA on TEGRA210 Thanks to jmcneill for help with this.
1.11	19-Sep-2017	jmcneill	branches: 1.11.2; 1.11.4; 1.11.6; The xusbpad driver is tegra 124 specific so split it out into a separate driver. Add (not yet working) tegra 210 support to the xusb driver.
1.10	16-Apr-2017	jmcneill	Add support for multiple clock domains in clk API.
1.9	22-Dec-2015	jmcneill	branches: 1.9.2; 1.9.4; Switch Tegra over to fdt based clocks and reset controls.
1.8	13-Dec-2015	jmcneill	Use fdt for device enumeration.
1.7	15-Oct-2015	jmcneill	disable SATA sleep feature
1.6	24-May-2015	jmcneill	set AHCI_QUIRK_SKIP_RESET quirk
1.5	15-May-2015	jmcneill	more Tegra SATA init
1.4	14-May-2015	jmcneill	fix SATA controller init
1.3	10-May-2015	jmcneill	Tegra SATA ungating support
1.2	26-Apr-2015	jmcneill	fix bus space handle for ahcisata
1.1	29-Mar-2015	jmcneill	branches: 1.1.2; NVIDIA Tegra K1 support, work in progress.
1.1.2.5	28-Aug-2017	skrll	Sync with HEAD
1.1.2.4	27-Dec-2015	skrll	Sync with HEAD (as of 26th Dec)
1.1.2.3	06-Jun-2015	skrll	Sync with HEAD
1.1.2.2	06-Apr-2015	skrll	Sync with HEAD
1.1.2.1	29-Mar-2015	skrll	file tegra_ahcisata.c was added on branch nick-nhusb on 2015-04-06 15:17:53 +0000
1.9.4.1	21-Apr-2017	bouyer	Sync with HEAD
1.9.2.1	26-Apr-2017	pgoyette	Sync with HEAD
1.11.6.1	10-Jun-2019	christos	Sync with HEAD
1.11.4.1	26-Dec-2018	pgoyette	Sync with HEAD, resolve a few conflicts
1.11.2.2	03-Dec-2017	jdolecek	update from HEAD
1.11.2.1	19-Sep-2017	jdolecek	file tegra_ahcisata.c was added on branch tls-maxphys on 2017-12-03 11:35:54 +0000
1.12.12.2	03-Apr-2021	thorpej	Sync with HEAD.
1.12.12.1	03-Jan-2021	thorpej	Sync w/ HEAD.
1.12.4.1	30-Dec-2020	martin	Pull up following revision(s) (requested by jmcneill in ticket #1167): sys/dev/ic/ahcisata_core.c: revision 1.84 sys/dev/ic/ahcisata_core.c: revision 1.85 sys/dev/ic/ahcisata_core.c: revision 1.88 sys/dev/ic/ahcisata_core.c: revision 1.89 sys/arch/arm/nvidia/tegra_ahcisata.c: revision 1.13 sys/dev/ic/ahcisatavar.h: revision 1.26 sys/dev/ic/ahcisata_core.c: revision 1.90 sys/dev/ic/ahcisata_core.c: revision 1.91 sys/dev/ic/ahcisata_core.c: revision 1.92 sys/dev/ata/satareg.h: revision 1.6 ahci_exec_fis: wait for the correct amount of time when AT_WAIT is set Retry clearing WDCTL_RST a few times before giving up. Makes SATA work in Solidrun Honeycomb LX2K. AHCI 1.3.1 specification says that it is good practice for system software to 'zero-out' the memory allocated and referenced by PxCLB and PxFB. ahci_intr: use ffs in the port bitmask instead of looping over all 32 bits AHCI 1.3.1 section 5.5.3 "Processing Completed Commands" says that we should clear PxIS before IS.IPS. Add G3 and DevSleep definitions. This changes the mask used by SControl_IPM_NONE from 0x3 to 0x7. Make sure to ack IS after PxIS when polling and when using multiple MSI-X messages. Remove the AHCI_QUIRK_SKIP_RESET quirk now that the underlying issue is fixed.

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