tegra_ahcisata.c revision 1.9
1 /* $NetBSD: tegra_ahcisata.c,v 1.9 2015/12/22 22:10:36 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.9 2015/12/22 22:10:36 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <dev/ata/atavar.h> 40 #include <dev/ic/ahcisatavar.h> 41 42 #include <arm/nvidia/tegra_var.h> 43 #include <arm/nvidia/tegra_pmcreg.h> 44 #include <arm/nvidia/tegra_ahcisatareg.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #define TEGRA_AHCISATA_OFFSET 0x7000 49 50 static int tegra_ahcisata_match(device_t, cfdata_t, void *); 51 static void tegra_ahcisata_attach(device_t, device_t, void *); 52 53 struct tegra_ahcisata_softc { 54 struct ahci_softc sc; 55 bus_space_tag_t sc_bst; 56 bus_space_handle_t sc_bsh; 57 void *sc_ih; 58 struct clk *sc_clk_sata; 59 struct clk *sc_clk_sata_oob; 60 struct clk *sc_clk_cml1; 61 struct clk *sc_clk_pll_e; 62 struct fdtbus_reset *sc_rst_sata; 63 struct fdtbus_reset *sc_rst_sata_oob; 64 struct fdtbus_reset *sc_rst_sata_cold; 65 66 struct tegra_gpio_pin *sc_pin_power; 67 }; 68 69 static const char * const tegra_ahcisata_supplies[] = { 70 "hvdd-supply", 71 "vddio-supply", 72 "avdd-supply", 73 "target-5v-supply", 74 "target-12v-supply" 75 }; 76 77 static void tegra_ahcisata_init(struct tegra_ahcisata_softc *); 78 static int tegra_ahcisata_init_clocks(struct tegra_ahcisata_softc *); 79 80 CFATTACH_DECL_NEW(tegra_ahcisata, sizeof(struct tegra_ahcisata_softc), 81 tegra_ahcisata_match, tegra_ahcisata_attach, NULL, NULL); 82 83 static int 84 tegra_ahcisata_match(device_t parent, cfdata_t cf, void *aux) 85 { 86 const char * const compatible[] = { "nvidia,tegra124-ahci", NULL }; 87 struct fdt_attach_args * const faa = aux; 88 89 return of_match_compatible(faa->faa_phandle, compatible); 90 } 91 92 static void 93 tegra_ahcisata_attach(device_t parent, device_t self, void *aux) 94 { 95 struct tegra_ahcisata_softc * const sc = device_private(self); 96 struct fdt_attach_args * const faa = aux; 97 const int phandle = faa->faa_phandle; 98 bus_addr_t ahci_addr, sata_addr; 99 bus_size_t ahci_size, sata_size; 100 struct fdtbus_regulator *reg; 101 char intrstr[128]; 102 int error, n; 103 104 if (fdtbus_get_reg(phandle, 0, &ahci_addr, &ahci_size) != 0) { 105 aprint_error(": couldn't get ahci registers\n"); 106 return; 107 } 108 if (fdtbus_get_reg(phandle, 1, &sata_addr, &sata_size) != 0) { 109 aprint_error(": couldn't get sata registers\n"); 110 return; 111 } 112 sc->sc_clk_sata = fdtbus_clock_get(phandle, "sata"); 113 if (sc->sc_clk_sata == NULL) { 114 aprint_error(": couldn't get clock sata\n"); 115 return; 116 } 117 sc->sc_clk_sata_oob = fdtbus_clock_get(phandle, "sata-oob"); 118 if (sc->sc_clk_sata_oob == NULL) { 119 aprint_error(": couldn't get clock sata-oob\n"); 120 return; 121 } 122 sc->sc_clk_cml1 = fdtbus_clock_get(phandle, "cml1"); 123 if (sc->sc_clk_cml1 == NULL) { 124 aprint_error(": couldn't get clock cml1\n"); 125 return; 126 } 127 sc->sc_clk_pll_e = fdtbus_clock_get(phandle, "pll_e"); 128 if (sc->sc_clk_pll_e == NULL) { 129 aprint_error(": couldn't get clock pll_e\n"); 130 return; 131 } 132 sc->sc_rst_sata = fdtbus_reset_get(phandle, "sata"); 133 if (sc->sc_rst_sata == NULL) { 134 aprint_error(": couldn't get reset sata\n"); 135 return; 136 } 137 sc->sc_rst_sata_oob = fdtbus_reset_get(phandle, "sata-oob"); 138 if (sc->sc_rst_sata_oob == NULL) { 139 aprint_error(": couldn't get reset sata-oob\n"); 140 return; 141 } 142 sc->sc_rst_sata_cold = fdtbus_reset_get(phandle, "sata-cold"); 143 if(sc->sc_rst_sata_cold == NULL) { 144 aprint_error(": couldn't get reset sata-cold\n"); 145 return; 146 } 147 148 sc->sc_bst = faa->faa_bst; 149 error = bus_space_map(sc->sc_bst, sata_addr, sata_size, 0, &sc->sc_bsh); 150 if (error) { 151 aprint_error(": couldn't map sata registers: %d\n", error); 152 return; 153 } 154 155 sc->sc.sc_atac.atac_dev = self; 156 sc->sc.sc_dmat = faa->faa_dmat; 157 sc->sc.sc_ahcit = faa->faa_bst; 158 sc->sc.sc_ahcis = ahci_size; 159 error = bus_space_map(sc->sc.sc_ahcit, ahci_addr, ahci_size, 0, 160 &sc->sc.sc_ahcih); 161 if (error) { 162 aprint_error(": couldn't map ahci registers: %d\n", error); 163 return; 164 } 165 sc->sc.sc_ahci_quirks = AHCI_QUIRK_SKIP_RESET; 166 167 aprint_naive("\n"); 168 aprint_normal(": SATA\n"); 169 170 for (n = 0; n < __arraycount(tegra_ahcisata_supplies); n++) { 171 const char *supply = tegra_ahcisata_supplies[n]; 172 reg = fdtbus_regulator_acquire(phandle, supply); 173 if (reg == NULL) { 174 aprint_error_dev(self, "couldn't acquire %s\n", supply); 175 continue; 176 } 177 if (fdtbus_regulator_enable(reg) != 0) { 178 aprint_error_dev(self, "couldn't enable %s\n", supply); 179 } 180 fdtbus_regulator_release(reg); 181 } 182 183 if (tegra_ahcisata_init_clocks(sc) != 0) 184 return; 185 186 tegra_xusbpad_sata_enable(); 187 188 tegra_ahcisata_init(sc); 189 190 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 191 aprint_error_dev(self, "failed to decode interrupt\n"); 192 return; 193 } 194 195 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, 0, 196 ahci_intr, &sc->sc); 197 if (sc->sc_ih == NULL) { 198 aprint_error_dev(self, "failed to establish interrupt on %s\n", 199 intrstr); 200 return; 201 } 202 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 203 204 ahci_attach(&sc->sc); 205 } 206 207 static void 208 tegra_ahcisata_init(struct tegra_ahcisata_softc *sc) 209 { 210 bus_space_tag_t bst = sc->sc_bst; 211 bus_space_handle_t bsh = sc->sc_bsh; 212 213 const u_int gen1_tx_amp = 0x18; 214 const u_int gen1_tx_peak = 0x04; 215 const u_int gen2_tx_amp = 0x18; 216 const u_int gen2_tx_peak = 0x0a; 217 218 /* Set RX idle detection source and disable RX idle detection interrupt */ 219 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG, 220 TEGRA_SATA_AUX_MISC_CNTL_1_AUX_OR_CORE_IDLE_STATUS_SEL, 0); 221 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_RX_STAT_INT_REG, 222 TEGRA_SATA_AUX_RX_STAT_INT_SATA_RX_STAT_INT_DISABLE, 0); 223 224 /* Prevent automatic OOB sequence when coming out of reset */ 225 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG, 226 0, TEGRA_SATA_AUX_MISC_CNTL_1_OOB_ON_POR); 227 228 /* Disable device sleep */ 229 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG, 230 0, TEGRA_SATA_AUX_MISC_CNTL_1_SDS_SUPPORT); 231 232 /* Enable IFPS device block */ 233 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_CONFIGURATION_REG, 234 TEGRA_SATA_CONFIGURATION_EN_FPCI, 0); 235 236 /* PHY config */ 237 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_INDEX_REG, 238 TEGRA_T_SATA0_INDEX_CH1); 239 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_REG, 240 __SHIFTIN(gen1_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP) | 241 __SHIFTIN(gen1_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK), 242 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP | 243 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK); 244 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_REG, 245 __SHIFTIN(gen2_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP) | 246 __SHIFTIN(gen2_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK), 247 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP | 248 TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK); 249 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL11_REG, 250 __SHIFTIN(0x2800, TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ)); 251 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL2_REG, 252 __SHIFTIN(0x23, TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1)); 253 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_INDEX_REG, 0); 254 255 /* Backdoor update the programming interface field and class code */ 256 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG, 257 TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN, 0); 258 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_BKDOOR_CC_REG, 259 __SHIFTIN(0x1016, TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE) | 260 __SHIFTIN(0x1, TEGRA_T_SATA0_BKDOOR_CC_PROG_IF)); 261 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG, 262 0, TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN); 263 264 /* Enable access and bus mastering */ 265 tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG1_REG, 266 TEGRA_T_SATA0_CFG1_SERR | 267 TEGRA_T_SATA0_CFG1_BUS_MASTER | 268 TEGRA_T_SATA0_CFG1_MEM_SPACE | 269 TEGRA_T_SATA0_CFG1_IO_SPACE, 270 0); 271 272 /* MMIO setup */ 273 bus_space_write_4(bst, bsh, TEGRA_SATA_FPCI_BAR5_REG, 274 __SHIFTIN(0x10000, TEGRA_SATA_FPCI_BAR_START)); 275 bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CFG9_REG, 276 __SHIFTIN(0x8000, TEGRA_T_SATA0_CFG9_BASE_ADDRESS)); 277 278 /* Enable interrupts */ 279 tegra_reg_set_clear(bst, bsh, TEGRA_SATA_INTR_MASK_REG, 280 TEGRA_SATA_INTR_MASK_IP_INT, 0); 281 } 282 283 static int 284 tegra_ahcisata_init_clocks(struct tegra_ahcisata_softc *sc) 285 { 286 device_t self = sc->sc.sc_atac.atac_dev; 287 struct clk *pll_p_out0; 288 int error; 289 290 pll_p_out0 = clk_get("pll_p_out0"); 291 if (pll_p_out0 == NULL) { 292 aprint_error_dev(self, "couldn't find pll_p_out0\n"); 293 return ENOENT; 294 } 295 296 /* Assert resets */ 297 fdtbus_reset_assert(sc->sc_rst_sata); 298 fdtbus_reset_assert(sc->sc_rst_sata_cold); 299 300 /* Set SATA_OOB clock source to PLLP, 204MHz */ 301 error = clk_set_parent(sc->sc_clk_sata_oob, pll_p_out0); 302 if (error) { 303 aprint_error_dev(self, "couldn't set sata-oob parent: %d\n", 304 error); 305 return error; 306 } 307 error = clk_set_rate(sc->sc_clk_sata_oob, 204000000); 308 if (error) { 309 aprint_error_dev(self, "couldn't set sata-oob rate: %d\n", 310 error); 311 return error; 312 } 313 314 /* Set SATA clock source to PLLP, 102MHz */ 315 error = clk_set_parent(sc->sc_clk_sata, pll_p_out0); 316 if (error) { 317 aprint_error_dev(self, "couldn't set sata parent: %d\n", error); 318 return error; 319 } 320 error = clk_set_rate(sc->sc_clk_sata, 102000000); 321 if (error) { 322 aprint_error_dev(self, "couldn't set sata rate: %d\n", error); 323 return error; 324 } 325 326 /* Ungate SAX partition in the PMC */ 327 tegra_pmc_power(PMC_PARTID_SAX, true); 328 delay(20); 329 330 /* Remove clamping from SAX partition in the PMC */ 331 tegra_pmc_remove_clamping(PMC_PARTID_SAX); 332 delay(20); 333 334 /* Un-gate clocks and enable CML clock for SATA */ 335 error = clk_enable(sc->sc_clk_sata); 336 if (error) { 337 aprint_error_dev(self, "couldn't enable sata: %d\n", error); 338 return error; 339 } 340 error = clk_enable(sc->sc_clk_sata_oob); 341 if (error) { 342 aprint_error_dev(self, "couldn't enable sata-oob: %d\n", error); 343 return error; 344 } 345 error = clk_enable(sc->sc_clk_cml1); 346 if (error) { 347 aprint_error_dev(self, "couldn't enable cml1: %d\n", error); 348 return error; 349 } 350 351 /* De-assert resets */ 352 fdtbus_reset_deassert(sc->sc_rst_sata); 353 fdtbus_reset_deassert(sc->sc_rst_sata_cold); 354 355 return 0; 356 } 357
Indexes created Fri Sep 26 08:10:20 GMT 2025