Cross Reference: /src/sys/arch/arm/sunxi/sunxi_ccu

History log of /src/sys/arch/arm/sunxi/sunxi_ccu_phase.c
Revision	Date	Author	Comments
1.1	17-Jul-2017	jmcneill	branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8; Add SDMMC[012] sample/output clock phase controls.
1.1.8.2	03-Dec-2017	jdolecek	update from HEAD
1.1.8.1	17-Jul-2017	jdolecek	file sunxi_ccu_phase.c was added on branch tls-maxphys on 2017-12-03 11:35:56 +0000
1.1.6.2	28-Aug-2017	skrll	Sync with HEAD
1.1.6.1	17-Jul-2017	skrll	file sunxi_ccu_phase.c was added on branch nick-nhusb on 2017-08-28 17:51:32 +0000
1.1.4.2	25-Jul-2017	snj	Pull up following revision(s) (requested by jmcneill in ticket #143): sys/arch/arm/sunxi/files.sunxi: revision 1.12 sys/arch/arm/sunxi/sun8i_h3_ccu.c: revision 1.8 sys/arch/arm/sunxi/sunxi_ccu.c: revision 1.6 sys/arch/arm/sunxi/sunxi_ccu.h: revision 1.7 sys/arch/arm/sunxi/sunxi_ccu_phase.c: revision 1.1 sys/arch/arm/sunxi/sunxi_mmc.c: revision 1.3 sys/arch/arm/sunxi/sunxi_mmc.h: revision 1.2 Add SDMMC[012] sample/output clock phase controls. -- Add support for eMMC DDR52 transfer mode.
1.1.4.1	17-Jul-2017	snj	file sunxi_ccu_phase.c was added on branch netbsd-8 on 2017-07-25 02:03:16 +0000
1.1.2.2	17-Jul-2017	jmcneill	2360748
1.1.2.1	17-Jul-2017	jmcneill	file sunxi_ccu_phase.c was added on branch perseant-stdc-iso10646 on 2017-07-17 23:26:18 +0000

OpenGrok