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History log of /src/sys/arch/mips/cavium/octeon_misc.c
RevisionDateAuthorComments
 1.2  06-Feb-2022  andvar fix various typos in comments, log messages and documentation.
mainly s/aparently/apparently/ and s/implmented/implemented/.
 1.1  15-Jun-2020  simonb Finish CPU core support for Octeon Cavium CN70XX:
- decode actual CPU name
- per CPU core reset logic (partially adapted from OpenBSD)
- handle Octeon 3 ioclock rate differences to other cores (from OpenBSD)

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