| History log of /src/sys/arch/mips/include/cache.h |
| Revision | | Date | Author | Comments |
| 1.17 |
| 03-May-2025 |
riastradh | mips: Include opt_cputype.h before any of the flags it defines.
PR port-evbmips/59385: PGSHIFT is inconsistently defined on MIPS
|
| 1.16 |
| 27-Jul-2020 |
skrll | branches: 1.16.26;
s/MODULE/_MODULE/
spotted by chuq@
|
| 1.15 |
| 26-Jul-2020 |
simonb | #define<tab>
Nuke trailing whitespace.
|
| 1.14 |
| 18-Aug-2016 |
skrll | Need to compile in cache alias support when MIPS3 or MIPS4
|
| 1.13 |
| 11-Jul-2016 |
matt | Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
|
| 1.12 |
| 07-Jun-2015 |
matt | Multiple inclusion protection
|
| 1.11 |
| 15-Mar-2011 |
matt | branches: 1.11.14; 1.11.32;
Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.
|
| 1.10 |
| 20-Feb-2011 |
matt | Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
|
| 1.9 |
| 11-Dec-2005 |
christos | branches: 1.9.96; 1.9.100; 1.9.106; 1.9.108;
merge ktrace-lwp.
|
| 1.8 |
| 26-Mar-2005 |
tsutsui | Add a workaround to handle virtual alias which may cause data corruption
on R5000/Rm52xx machines:
- Add a new global variable mips_cache_virtual_alias in mips/cache.c,
which indicates that VIPT cache on the CPU could cause virtual alias
and software support is required to handle it. (i.e. no VCED/VCEI)
- Add several cache flush/invalidate ops around KSEG0 access which
might cause virtual alias if mips_cache_virtual_alias is true.
(note checking mips_sdcache_line_size isn't valid for R5000/Rm52xx
because only R4000/R4400 with L2 cache have VCED/VCEI)
- Remove a global variable mips_sdcache_forceinv, which is now superseded
by new mips_cache_virtual_alias.
While here, also change some R4000/R4400 cache ops:
- Don't override mips_cache_alias_mask and mips_cache_prefer_mask with
values based on MIPS3_MAX_PCACHE_SIZE for R4000/R4400 with L2 cache
because it's still worth to reduce VCED/VCEI.
- Flush dcache in pmap_zero_page(9) unconditionally on all MIPS_HAS_R4K_MMU
CPUs and remove cache flush code from cpu_lwp_fork() in vm_machdep.c.
Thanks to Markus W Kilbinger for testing patches on port-cobalt/port-mips.
XXX This fix is just a workaround because it doesn't handle all possible
XXX virtual aliases. As discussed on port-mips, maybe the real fix
XXX for virtual alias is to change MI UVM to adapt it to VIPT cache.
XXX (all VA mappings against the same PA must have the same VAC index etc.)
|
| 1.7 |
| 01-Mar-2005 |
sekiya | branches: 1.7.2;
Add a hint variable (mips_sdcache_forceinv, explicitly initialized to zero)
that tells pmap_zero_page() and pmap_copy_page() to unconditionally invalidate
pages for r5k-class CPUs with secondary cache.
This behavior must be explicitly enabled by setting mips_sdcache_forceinv to 1.
This is the last bit of a patch that has been kicked around since 2000 between
rafal@, tsutsui@, and myself.
|
| 1.6 |
| 17-Feb-2003 |
simonb | branches: 1.6.2; 1.6.10; 1.6.12;
No need to protect headers with #ifdef _KERNEL if they're never installed
in /usr/include.
|
| 1.5 |
| 17-Dec-2002 |
simonb | Add support for caches where the data cache is fully coherent, and
either requires flushing either only when the I cache ops are used
or not at all. Currently only used by MIPS32/MIPS64 cache code.
|
| 1.4 |
| 09-Nov-2002 |
thorpej | Make cache size/mask variables unsigned.
|
| 1.3 |
| 19-Nov-2001 |
thorpej | branches: 1.3.2;
Add mips_dcache_align and mips_dcache_align_mask variables that
contain information suitable for allowing other parts of the kernel
to determine if a memory region is aligned to the largest data cache
line size present in the system.
Add a mips_dcache_compute_align() function which must be called whenever
one of the data cache line size variables is changed, in order to
compute mips_dcache_align and mips_dcache_align_mask.
|
| 1.2 |
| 14-Nov-2001 |
thorpej | branches: 1.2.2;
Merge the thorpej-mips-cache branch onto the trunk. This is an
overhaul of how caches are handled for NetBSD's MIPS ports.
|
| 1.1 |
| 24-Oct-2001 |
thorpej | branches: 1.1.2;
file cache.h was initially added on branch thorpej-mips-cache.
|
| 1.1.2.1 |
| 24-Oct-2001 |
thorpej | New MIPS cache primitives and code to configure which ones are used.
|
| 1.2.2.4 |
| 19-Dec-2002 |
thorpej | Sync with HEAD.
|
| 1.2.2.3 |
| 11-Nov-2002 |
nathanw | Catch up to -current
|
| 1.2.2.2 |
| 01-Feb-2002 |
gmcgarry | Pull-up cache ops from -current
|
| 1.2.2.1 |
| 14-Nov-2001 |
gmcgarry | file cache.h was added on branch nathanw_sa on 2002-02-01 04:57:44 +0000
|
| 1.3.2.2 |
| 10-Jan-2002 |
thorpej | Sync kqueue branch with -current.
|
| 1.3.2.1 |
| 19-Nov-2001 |
thorpej | file cache.h was added on branch kqueue on 2002-01-10 19:45:59 +0000
|
| 1.6.12.2 |
| 26-Mar-2005 |
yamt | sync with head.
|
| 1.6.12.1 |
| 19-Mar-2005 |
yamt | sync with head. xen and whitespace. xen part is not finished.
|
| 1.6.10.1 |
| 29-Apr-2005 |
kent | sync with -current
|
| 1.6.2.2 |
| 01-Apr-2005 |
skrll | Sync with HEAD.
|
| 1.6.2.1 |
| 04-Mar-2005 |
skrll | Sync with HEAD.
Hi Perry!
|
| 1.7.2.1 |
| 21-Nov-2005 |
tron | Pull up following revision(s) (requested by tsutsui in ticket #961):
sys/arch/mips/mips/cache.c: revision 1.27
sys/arch/mips/include/cache.h: revision 1.8
sys/arch/mips/mips/pmap.c: revision 1.158
sys/arch/mips/mips/vm_machdep.c: revision 1.106
sys/arch/mips/mips/mem.c: revision 1.30
sys/arch/mips/include/pmap.h: revision 1.47
Add a workaround to handle virtual alias which may cause data corruption
on R5000/Rm52xx machines:
- Add a new global variable mips_cache_virtual_alias in mips/cache.c,
which indicates that VIPT cache on the CPU could cause virtual alias
and software support is required to handle it. (i.e. no VCED/VCEI)
- Add several cache flush/invalidate ops around KSEG0 access which
might cause virtual alias if mips_cache_virtual_alias is true.
(note checking mips_sdcache_line_size isn't valid for R5000/Rm52xx
because only R4000/R4400 with L2 cache have VCED/VCEI)
- Remove a global variable mips_sdcache_forceinv, which is now superseded
by new mips_cache_virtual_alias.
While here, also change some R4000/R4400 cache ops:
- Don't override mips_cache_alias_mask and mips_cache_prefer_mask with
values based on MIPS3_MAX_PCACHE_SIZE for R4000/R4400 with L2 cache
because it's still worth to reduce VCED/VCEI.
- Flush dcache in pmap_zero_page(9) unconditionally on all MIPS_HAS_R4K_MMU
CPUs and remove cache flush code from cpu_lwp_fork() in vm_machdep.c.
Thanks to Markus W Kilbinger for testing patches on port-cobalt/port-mips.
XXX This fix is just a workaround because it doesn't handle all possible
XXX virtual aliases. As discussed on port-mips, maybe the real fix
XXX for virtual alias is to change MI UVM to adapt it to VIPT cache.
XXX (all VA mappings against the same PA must have the same VAC index etc.)
|
| 1.9.108.1 |
| 05-Mar-2011 |
bouyer | Sync with HEAD
|
| 1.9.106.1 |
| 06-Jun-2011 |
jruoho | Sync with HEAD.
|
| 1.9.100.2 |
| 21-Apr-2011 |
rmind | sync with head
|
| 1.9.100.1 |
| 05-Mar-2011 |
rmind | sync with head
|
| 1.9.96.8 |
| 19-Jan-2012 |
matt | When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.
The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.
Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
|
| 1.9.96.7 |
| 12-Jan-2012 |
matt | Add an optimization for UP system with non-virtually tagged caches (which are
most of them these days).
If a page needs to be have an icache_sync performed and the page has a direct
map alias (XKPHYS or KSEG0), then don't do an index op; instead do a range op
on the XKPHYS or KSEG0 address. This results in unneeded fewer cache line
invalidations.
|
| 1.9.96.6 |
| 27-Dec-2011 |
matt | Make these play nice with modules.
|
| 1.9.96.5 |
| 23-Dec-2011 |
matt | Add multiple inclusion protection.
Add separate variable for dealing with icache virtual aliases
|
| 1.9.96.4 |
| 26-May-2011 |
matt | Add MIPS64_RMIXL (XLR/XLS) and MIPS64R2_RMIXL (XLP). This allows the kernel
to treat this special which is needed for MP support. When accessing the TLB,
always lock the TLB before hand. If in the miss handlers, the TLB is already
locked let trap deal with the exeception.
|
| 1.9.96.3 |
| 29-Apr-2011 |
matt | Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
|
| 1.9.96.2 |
| 26-Jan-2010 |
matt | Revamp pmap. Add exec page caching logic from powerpc oea pmap. Shrink struct
vm_page by placing the first pv_entry in it. Remove pv_flags since nothing
really needed it. Add pmap counters. Rework virtual cache alias logic.
Allow pmap_copy_page and pmap_zero_page to deal with non-KSEG0 mappable pages.
|
| 1.9.96.1 |
| 20-Jan-2010 |
matt | Revamp things a bit. Move of the globals mips uses into either cpu_info,
mips_options, or mips_cache_info. Make MALT64 be able to boot MULTIPROCESSOR.
(some pmap MP work).
|
| 1.11.32.2 |
| 05-Oct-2016 |
skrll | Sync with HEAD
|
| 1.11.32.1 |
| 22-Sep-2015 |
skrll | Sync with HEAD
|
| 1.11.14.1 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.16.26.1 |
| 02-Aug-2025 |
perseant | Sync with HEAD
|
