Cross Reference: /src/sys/arch/mips/include/cache

History log of /src/sys/arch/mips/include/cache_mipsNN.h
Revision	Date	Author	Comments
1.6	26-Jul-2020	simonb	#define<tab> Nuke trailing whitespace.
1.5	11-Jul-2016	matt	Change MIPS to use the common pmap code. Switch to 8KB pages on CPUs with a R4K MMU. Simplify cache code. Merge in most of changes from matt-mips64 branch
1.4	17-Feb-2003	simonb	branches: 1.4.126; 1.4.152; 1.4.172; No need to protect headers with #ifdef _KERNEL if they're never installed in /usr/include.
1.3	24-Nov-2002	simonb	New generic way-aware MIPS32/64 range-index cache functions with proper handling for phyiscally-indexed caches where the way size is greater than the page size. These work fine with pass 1 SB1 cores, so g/c those workarounds. Much thanks to Chris Demetriou for many suggestions and helping me get my head around all this.
1.2	03-Apr-2002	simonb	Include 2way cache ops for mips{32,64} CPUs.
1.1	05-Mar-2002	simonb	branches: 1.1.4; 1.1.8; Prototypes for MIPS32/64 cache ops.
1.1.8.4	11-Dec-2002	thorpej	Sync with HEAD.
1.1.8.3	17-Apr-2002	nathanw	Catch up to -current.
1.1.8.2	01-Apr-2002	nathanw	Catch up to -current. (CVS: It's not just a program. It's an adventure!)
1.1.8.1	05-Mar-2002	nathanw	file cache_mipsNN.h was added on branch nathanw_sa on 2002-04-01 07:40:57 +0000
1.1.4.3	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.1.4.2	16-Mar-2002	jdolecek	Catch up with -current.
1.1.4.1	05-Mar-2002	jdolecek	file cache_mipsNN.h was added on branch kqueue on 2002-03-16 15:58:33 +0000
1.4.172.1	05-Oct-2016	skrll	Sync with HEAD
1.4.152.1	03-Dec-2017	jdolecek	update from HEAD
1.4.126.2	19-Jan-2012	matt	When running an N32 kernel, run it with 64-bit addresses even though the kernel itself will only use 32-bit addresses. There are exceptions. bus_space_handles are now register_t instead of intptr_t. This allows them to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more KSEG2 space for the kernel to use. The cache range routines (but not index routines) now take a register_t instead of vaddr_t so they can too take a XKPHYS address. This allows the pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding massive icache invalidations. Since "cache" instruction effects are global to all CPUs and their caches, we can use the above to greatly simplify MP page isyncs. If using an O32 kernel with pages outside KSEG0, index ops still need to be performed since there isn't an a quick way of mapping the page.
1.4.126.1	27-Dec-2011	matt	Make these play nice with modules.

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