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History log of /src/sys/arch/mips/include/cache_octeon.h
RevisionDateAuthorComments
 1.5  26-Jul-2020  simonb #define<tab>
Nuke trailing whitespace.
 1.4  14-Jun-2020  simonb Define Octeon Cavium cache layouts for various cnMIPS cores.
 1.3  11-Apr-2019  simonb Fix tyop.
 1.2  11-Jul-2016  matt branches: 1.2.16; 1.2.20;
Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch
 1.1  29-Apr-2015  hikaru branches: 1.1.2;
Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.
 1.1.2.3  05-Oct-2016  skrll Sync with HEAD
 1.1.2.2  06-Jun-2015  skrll Sync with HEAD
 1.1.2.1  29-Apr-2015  skrll file cache_octeon.h was added on branch nick-nhusb on 2015-06-06 14:40:01 +0000
 1.2.20.1  10-Jun-2019  christos Sync with HEAD
 1.2.16.2  03-Dec-2017  jdolecek update from HEAD
 1.2.16.1  11-Jul-2016  jdolecek file cache_octeon.h was added on branch tls-maxphys on 2017-12-03 11:36:27 +0000

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