| History log of /src/sys/arch/mips/include/psl.h |
| Revision | | Date | Author | Comments |
| 1.19 |
| 30-Jul-2016 |
matt | KX needs to set on !O32 kernels
|
| 1.18 |
| 14-Dec-2009 |
matt | branches: 1.18.22; 1.18.40; 1.18.44;
Merge from matt-nb5-mips64
Merge mips-specific arch files.
|
| 1.17 |
| 11-Dec-2005 |
christos | branches: 1.17.78; 1.17.96;
merge ktrace-lwp.
|
| 1.16 |
| 07-Aug-2003 |
agc | Move UCB-licensed code from 4-clause to 3-clause licence.
Patches provided by Joel Baker in PR 22364, verified by myself.
|
| 1.15 |
| 05-Mar-2002 |
simonb | branches: 1.15.14;
Add support for MIPS32 and MIPS64 architectures:
Remove the unused PSL_USERCLR and BASEPRI macros.
|
| 1.14 |
| 11-Jul-2000 |
jeffs | branches: 1.14.4; 1.14.8;
For 64b clean 32b compilation, do not bother setting SX And KX.
The current code does not maintain these in SR, and they are not
needed by 32b kernel code for mips3/4 instructions.
|
| 1.13 |
| 15-May-2000 |
nisimura | branches: 1.13.4;
Remove unused PSL_USERCLR defines for processor status register.
|
| 1.12 |
| 31-Jan-1999 |
castor | branches: 1.12.8;
Remove genpubassym.cf stuff. The macro _MIPS_BSD_API allows selection of a
64-bit clean compilation model.
|
| 1.11 |
| 18-Jan-1999 |
castor | Remove vestiges of cpuarch.h. Revert to using cpuregs.h instead.
|
| 1.10 |
| 14-Jan-1999 |
castor | * Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.
* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.
* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.
* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
|
| 1.9 |
| 11-Sep-1998 |
jonathan | branches: 1.9.2;
Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.
Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.
Open issues:
* Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
Code derived from Per Fogelstrom's OpenBSD source doesn't work
on mips3 pmaxes with L2 cache.
* Still some port-specific #ifdefs, for interrupt enable and
pmax L2 cache-size. Needs more thought, but overlaps with
work-in-progress by Tohru and Tsubai on spl()s and related stuff.
|
| 1.8 |
| 22-Jun-1997 |
jonathan | * Change Sprite MACH_xxx prefix to MIPS_xxx.
* Use standard mips terminology (xxx_KSEG0, xxx_KSEG1) instead of the
(more meaningful) Sprite names (xxx_CACHED, xxx_UNCACHED).
|
| 1.7 |
| 21-Jun-1997 |
jonathan | More mips1/mips3 changes to cpuregs.h and psl.h:
* cpuregs.h:
Delete unused VMMACH_ names (e.g., duplicates of PTE bits in pte.h).
Change remaining VMMACH_xxx names to MIPS1_xxx or MIPS3_xx.
Fold remaining compile-time definitions into a single #ifdef MIPS3.
* Use MIPS1_ names in locore_r2000.S, mips3_ names in locore_r4000.S
* Garbage-collect MachHitFlushDCache()
* psl.h:
use MIPS1_, MIPS3_ symbolic names for Cause register bits.
change _R3K to MIPS1_, _R4K to MIPS3. Conditionalize for mips1 only,
mips3 only, or when both are defined, use runtime CPUISMIPS3 test.
|
| 1.6 |
| 16-Jun-1997 |
jonathan | Move merged pmax psl.h with mips1/mips3 support to mips/include/psl.h.
Change pmax/include/psl.h to just do #include <mips/psl.h>.
pmax/include/psl.h would go away completely if it wasn't stil required
by compat/common/kern_exit_43.c.
|
| 1.5 |
| 15-Jun-1997 |
mhitch | More merged MIPS1/MIPS3 support for DECstations.
|
| 1.4 |
| 26-Oct-1994 |
cgd | new RCS ID format.
|
| 1.3 |
| 27-May-1994 |
glass | bsd 4.4-lite pmax port as ported to NetBSD
|
| 1.2 |
| 27-May-1994 |
glass | upgrade to bsd 4.4-lite code base. only mod is rcsids
|
| 1.1 |
| 12-Oct-1993 |
deraadt | branches: 1.1.1;
Initial revision
|
| 1.1.1.1 |
| 12-Oct-1993 |
deraadt | pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
|
| 1.9.2.2 |
| 19-Nov-1998 |
nisimura | - Forgot to commit many files for vm_offset_t purge last Monday.
|
| 1.9.2.1 |
| 15-Oct-1998 |
nisimura | - cpuregs.h was modifed a bit, then renamed with cpuarch.h.
- mips_cpu.h has gone.
- CPU's register mnemonics in regdef.h is now a part of asm.h.
|
| 1.12.8.1 |
| 20-Nov-2000 |
bouyer | Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
|
| 1.13.4.1 |
| 18-Jul-2000 |
jeffs | Pull up revision 1.14 (approved by cgd).
Remove extraneous bits from MIPS3_PSL_XFLAGS.
|
| 1.14.8.1 |
| 01-Apr-2002 |
nathanw | Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
|
| 1.14.4.1 |
| 16-Mar-2002 |
jdolecek | Catch up with -current.
|
| 1.15.14.3 |
| 21-Sep-2004 |
skrll | Fix the sync with head I botched.
|
| 1.15.14.2 |
| 18-Sep-2004 |
skrll | Sync with HEAD.
|
| 1.15.14.1 |
| 03-Aug-2004 |
skrll | Sync with HEAD
|
| 1.17.96.3 |
| 19-Jan-2012 |
matt | When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses. There are exceptions.
bus_space_handles are now register_t instead of intptr_t. This allows them
to contain XKPHYS addresses. Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.
The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address. This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.
Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs. If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.
|
| 1.17.96.2 |
| 07-Sep-2009 |
matt | Add MIPS_SR_KX to PSL_USERSET if _LP64
|
| 1.17.96.1 |
| 16-Aug-2009 |
matt | Kill use of _MIPS_BSD_ABI - switch to __mips_<abi>
Use device_t where appropriate.
Remove magic numbers.
|
| 1.17.78.1 |
| 11-Mar-2010 |
yamt | sync with head
|
| 1.18.44.1 |
| 06-Aug-2016 |
pgoyette | Sync with HEAD
|
| 1.18.40.1 |
| 05-Oct-2016 |
skrll | Sync with HEAD
|
| 1.18.22.1 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
