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History log of /src/sys/arch/mips/include/trap.h
RevisionDateAuthorComments
 1.19  06-Jun-2015  matt Add missing but now defined trap types. (use define<tab> consistently)
 1.18  16-Aug-2011  matt branches: 1.18.12; 1.18.30;
Add support for the MIPS DSP ASE (as a second PCU).
 1.17  20-Feb-2011  matt Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU
 1.16  08-Feb-2011  rmind Remove clause 3 (UCB advertising clause) from the University of Utah
copyright. Confirmed by Mike Hibler, mike at cs.utah.edu - thanks!
Also, merge UCB and Utah copyright texts back into one, as they
originally were.

Extra verification by snj@.
 1.15  11-Dec-2005  christos branches: 1.15.96; 1.15.100; 1.15.106; 1.15.108;
merge ktrace-lwp.
 1.14  07-Aug-2003  agc Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.
 1.13  15-Sep-2000  jeffs branches: 1.13.24;
Handle R4K trap faults in user mode like overflows (deliver SIGFPE). This
prevents a panic running crashme. Better comment for VCE define.
 1.12  14-Jan-1999  castor branches: 1.12.8;
* Create mips_reg_t data type to allow register size to be
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
 1.11  06-Jan-1999  nisimura - Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.
 1.10  24-Oct-1998  jonathan Cleanup kdbpeek() definition as noted in PR port-mips/5252.
 1.9  01-Oct-1998  jonathan branches: 1.9.2;
More patches for ARC from Noriyuki Soda:
* commit isapnpvar.h changes required for ARC to support plain isa.
* fixup mistake over mips/include/cpuregs.h.
* mips/mips_machdep.c:
set L2 cache-size for arc, cleanup use of L2cache present
vs L2 cache-size variables. check for no L2 cache on kernels
configured to require one. misc cleanups.
* mips/mpis/trap.c: more locore stack-traceback label cleanup.
XXX Locore callbacks for mips3, mips4, r4600 cacheflush need more work.
 1.8  19-May-1998  simonb Change external declaration of kdbpeek to match reality.
 1.7  26-Mar-1998  jonathan * Create /sys/arch/mips/include/intr.h, with extern declaration of
interrupt-callout vector from mips locore dispatch code to port code.
* Move branch-emulation declaration to mips/include/trap.h.
* Garbage-collect pmax/pmax/trap.h.
Not needed now pmax/pmax_trap.c is gone, and after above tidy-up.
 1.6  24-Mar-1996  jonathan Change pmax T_USER bit (software only) to be 0x20, the same as the
Pica port. (The r4000 CPU used in the pica has more hardware execption types.)
 1.5  19-Mar-1996  jonathan Add trap definitions added for the r4000 port.
Note: T_USER is different in the pmax and pica ports!
 1.4  26-Oct-1994  cgd new RCS ID format.
 1.3  27-May-1994  glass bsd 4.4-lite pmax port as ported to NetBSD
 1.2  27-May-1994  glass upgrade to bsd 4.4-lite code base. only mod is rcsids
 1.1  12-Oct-1993  deraadt branches: 1.1.1;
Initial revision
 1.1.1.1  12-Oct-1993  deraadt pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
 1.9.2.1  15-Oct-1998  nisimura - cpuregs.h was modifed a bit, then renamed with cpuarch.h.
- mips_cpu.h has gone.
- CPU's register mnemonics in regdef.h is now a part of asm.h.
 1.12.8.1  20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.13.24.3  21-Sep-2004  skrll Fix the sync with head I botched.
 1.13.24.2  18-Sep-2004  skrll Sync with HEAD.
 1.13.24.1  03-Aug-2004  skrll Sync with HEAD
 1.15.108.2  05-Mar-2011  bouyer Sync with HEAD
 1.15.108.1  17-Feb-2011  bouyer Sync with HEAD
 1.15.106.1  06-Jun-2011  jruoho Sync with HEAD.
 1.15.100.1  05-Mar-2011  rmind sync with head
 1.15.96.2  23-Dec-2011  matt Add various new exceptions from MTE/32R2/64R2/DSP.
 1.15.96.1  29-Apr-2011  matt Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code. (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.
 1.18.30.1  06-Jun-2015  skrll Sync with HEAD
 1.18.12.1  03-Dec-2017  jdolecek update from HEAD

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