Cross Reference: /src/sys/arch/powerpc/booke/dev/pq3sdhc.c

History log of /src/sys/arch/powerpc/booke/dev/pq3sdhc.c
Revision	Date	Author	Comments
1.6	27-Feb-2015	nonaka	Enable DMA transfer.
1.5	26-Jul-2012	matt	branches: 1.5.2; 1.5.14; 1.5.16; When using DMA, make sure to initialize SNOOPing.
1.4	23-Feb-2012	matt	Use the new 32-bit and ESDHC support in sdhc.c
1.3	29-Jun-2011	matt	branches: 1.3.2; 1.3.6; 1.3.8; Use a private bus_space for freescale eSDHC controller (only allows 32 bit access).
1.2	18-Jan-2011	matt	branches: 1.2.4; Add support for BookE Freescale MPC85xx (e500 core) processors. Add fast softint support for PowerPC (though only booke uses it). Redo FPU/VEC support and add e500 SPE support. Rework trap/intrs to use a common trapframe format. Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.
1.1	07-Jan-2011	matt	branches: 1.1.2; 1.1.4; file pq3sdhc.c was initially added on branch matt-nb5-pq3.
1.1.4.1	06-Jun-2011	jruoho	Sync with HEAD.
1.1.2.1	07-Jan-2011	matt	Add mpc85xx support for netbsd-5 (with some incompatible kernel changes).
1.2.4.2	05-Mar-2011	rmind	sync with head
1.2.4.1	18-Jan-2011	rmind	file pq3sdhc.c was added on branch rmind-uvmplock on 2011-03-05 20:51:35 +0000
1.3.8.1	11-Jun-2012	riz	Pull up following revision(s) (requested by matt in ticket #254): sys/arch/powerpc/booke/dev/pq3sdhc.c: revision 1.4 sys/dev/sdmmc/sdhc.c: revision 1.11 sys/dev/sdmmc/sdhc.c: revision 1.13 Use the new 32-bit and ESDHC support in sdhc.c Support 32-bit only access to the SDHC registers. Add support for FreeScale "Enhanced" SDHC port. Add support for CGM mode (XLP and BCM2835 (Arason)). Do not read past array end, found by gcc -O3. This could cause to HWRITE4() a bad value, but maybe last 2 bytes are probably ignored by hardware anyway.
1.3.6.1	24-Feb-2012	mrg	sync to -current.
1.3.2.2	30-Oct-2012	yamt	sync with head
1.3.2.1	17-Apr-2012	yamt	sync with head
1.5.16.1	06-Apr-2015	skrll	Sync with HEAD
1.5.14.1	09-Mar-2015	snj	Pull up following revision(s) (requested by nonaka in ticket #577): sys/arch/powerpc/booke/dev/pq3sdhc.c: revision 1.6 sys/dev/sdmmc/sdhc.c: revision 1.54 sys/dev/sdmmc/sdmmc.c: revision 1.24 eSDHC has no DMA_BOUNDARY in BLOCK_SIZE register. So clear multi segment DMA transfer support bit. -- fix to simulate multi-segment dma transfer for pq3sdhc(4). -- pq3sdhc: Enable DMA transfer.
1.5.2.1	03-Dec-2017	jdolecek	update from HEAD

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