pq3sdhc.c revision 1.3
1 /* $NetBSD: pq3sdhc.c,v 1.3 2011/06/29 06:12:10 matt Exp $ */ 2 /*- 3 * Copyright (c) 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: pq3sdhc.c,v 1.3 2011/06/29 06:12:10 matt Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/kernel.h> 38 #include <sys/proc.h> 39 #include <sys/queue.h> 40 41 #include <sys/bus.h> 42 43 #include <powerpc/booke/cpuvar.h> 44 #include <powerpc/booke/e500var.h> 45 #include <powerpc/booke/e500reg.h> 46 47 #include <dev/sdmmc/sdhcreg.h> 48 #include <dev/sdmmc/sdhcvar.h> 49 50 #define EDSHC_HOST_CTL_RES 0x05 51 52 static int pq3sdhc_match(device_t, cfdata_t, void *); 53 static void pq3sdhc_attach(device_t, device_t, void *); 54 55 struct pq3sdhc_softc { 56 struct powerpc_bus_space sc_mybst; 57 struct sdhc_softc sc; 58 bus_space_tag_t sc_bst; 59 bus_space_handle_t sc_bsh; 60 struct sdhc_host *sc_hosts[1]; 61 void *sc_ih; /* interrupt vectoring */ 62 }; 63 64 CFATTACH_DECL_NEW(pq3sdhc, sizeof(struct pq3sdhc_softc), 65 pq3sdhc_match, pq3sdhc_attach, NULL, NULL); 66 67 static uint8_t 68 pq3sdhc_read_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 69 { 70 const struct pq3sdhc_softc * const sc = (const void *) t; 71 72 KASSERT((o & -4) != SDHC_DATA); 73 74 const uint32_t v = bus_space_read_4(sc->sc_bst, h, o & -4); 75 76 return v >> ((o & 3) * 8); 77 } 78 79 static uint16_t 80 pq3sdhc_read_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 81 { 82 const struct pq3sdhc_softc * const sc = (const void *) t; 83 84 KASSERT((o & 1) == 0); 85 KASSERT((o & -4) != SDHC_DATA); 86 87 uint32_t v = bus_space_read_4(sc->sc_bst, h, o & -4); 88 89 if (__predict_false(o == SDHC_HOST_VER)) 90 return v; 91 if (__predict_false(o == SDHC_NINTR_STATUS)) { 92 v |= SDHC_ERROR_INTERRUPT * ((v > 0xffff) != 0); 93 if (v != 0) 94 printf("get(INTR_STATUS)=%#x\n", v); 95 } 96 if (__predict_false(o == SDHC_EINTR_STATUS)) { 97 if (v != 0) 98 printf("get(INTR_STATUS)=%#x\n", v); 99 } 100 101 return v >> ((o & 2) * 8); 102 } 103 104 static uint32_t 105 pq3sdhc_read_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 106 { 107 const struct pq3sdhc_softc * const sc = (const void *) t; 108 109 KASSERT((o & 3) == 0); 110 111 uint32_t v = bus_space_read_4(sc->sc_bst, h, o & -4); 112 113 if (__predict_false(o == SDHC_DATA)) 114 v = htole32(v); 115 116 return v; 117 } 118 119 static void 120 pq3sdhc_write_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, uint8_t nv) 121 { 122 const struct pq3sdhc_softc * const sc = (const void *) t; 123 KASSERT((o & -4) != SDHC_DATA); 124 uint32_t v = bus_space_read_4(sc->sc_bst, h, o & -4); 125 const u_int shift = (o & 3) * 8; 126 127 if (o == SDHC_HOST_CTL) { 128 nv &= ~EDSHC_HOST_CTL_RES; 129 } 130 131 v &= ~(0xff << shift); 132 v |= (nv << shift); 133 134 bus_space_write_4(sc->sc_bst, h, o & -4, v); 135 } 136 137 static void 138 pq3sdhc_write_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, uint16_t nv) 139 { 140 const struct pq3sdhc_softc * const sc = (const void *) t; 141 KASSERT((o & 1) == 0); 142 KASSERT((o & -4) != SDHC_DATA); 143 const u_int shift = (o & 2) * 8; 144 uint32_t v; 145 146 /* 147 * Since NINTR_STATUS and EINTR_STATUS are W1C, don't bother getting 148 * the previous value since we'd clear them. 149 */ 150 if (__predict_true((o & -4) != SDHC_NINTR_STATUS)) { 151 v = bus_space_read_4(sc->sc_bst, h, o & -4); 152 v &= ~(0xffff << shift); 153 v |= nv << shift; 154 } else { 155 v = nv << shift; 156 printf("put(INTR_STATUS,%#x)\n", v); 157 } 158 159 bus_space_write_4(sc->sc_bst, h, o & -4, v); 160 } 161 162 static void 163 pq3sdhc_write_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, uint32_t v) 164 { 165 const struct pq3sdhc_softc * const sc = (const void *) t; 166 167 KASSERT((o & 3) == 0); 168 169 if (__predict_false(o == SDHC_DATA)) 170 v = le32toh(v); 171 172 bus_space_write_4(sc->sc_bst, h, o & -4, v); 173 } 174 175 static int 176 pq3sdhc_match(device_t parent, cfdata_t cf, void *aux) 177 { 178 179 if (!e500_cpunode_submatch(parent, cf, cf->cf_name, aux)) 180 return 0; 181 182 return 1; 183 } 184 185 static void 186 pq3sdhc_attach(device_t parent, device_t self, void *aux) 187 { 188 struct cpunode_softc * const psc = device_private(parent); 189 struct pq3sdhc_softc * const sc = device_private(self); 190 struct cpunode_attach_args * const cna = aux; 191 struct cpunode_locators * const cnl = &cna->cna_locs; 192 int error; 193 194 psc->sc_children |= cna->cna_childmask; 195 sc->sc.sc_dmat = cna->cna_dmat; 196 sc->sc.sc_dev = self; 197 //sc->sc.sc_flags |= SDHC_FLAG_USE_DMA; 198 sc->sc.sc_flags |= SDHC_FLAG_HAVE_DVS; 199 sc->sc.sc_host = sc->sc_hosts; 200 sc->sc.sc_clkbase = board_info_get_number("bus-frequency") / 2000; 201 sc->sc_bst = cna->cna_memt; 202 sc->sc_mybst = *cna->cna_memt; 203 204 sc->sc_mybst.pbs_scalar.pbss_read_1 = pq3sdhc_read_1; 205 sc->sc_mybst.pbs_scalar.pbss_read_2 = pq3sdhc_read_2; 206 sc->sc_mybst.pbs_scalar.pbss_read_4 = pq3sdhc_read_4; 207 sc->sc_mybst.pbs_scalar.pbss_write_1 = pq3sdhc_write_1; 208 sc->sc_mybst.pbs_scalar.pbss_write_2 = pq3sdhc_write_2; 209 sc->sc_mybst.pbs_scalar.pbss_write_4 = pq3sdhc_write_4; 210 211 error = bus_space_map(sc->sc_bst, cnl->cnl_addr, cnl->cnl_size, 0, 212 &sc->sc_bsh); 213 if (error) { 214 aprint_error_dev(self, 215 "can't map registers for %s: %d\n", cnl->cnl_name, error); 216 return; 217 } 218 219 aprint_naive(": SDHC controller\n"); 220 aprint_normal(": SDHC controller\n"); 221 222 sc->sc_ih = intr_establish(cnl->cnl_intrs[0], IPL_VM, IST_ONCHIP, 223 sdhc_intr, &sc->sc); 224 if (sc->sc_ih == NULL) { 225 aprint_error_dev(self, "failed to establish interrupt %d\n", 226 cnl->cnl_intrs[0]); 227 goto fail; 228 } 229 aprint_normal_dev(self, "interrupting on irq %d\n", 230 cnl->cnl_intrs[0]); 231 232 error = sdhc_host_found(&sc->sc, &sc->sc_mybst, sc->sc_bsh, 233 cnl->cnl_size); 234 if (error != 0) { 235 aprint_error_dev(self, "couldn't initialize host, error=%d\n", 236 error); 237 goto fail; 238 } 239 return; 240 241 fail: 242 if (sc->sc_ih) { 243 intr_disestablish(sc->sc_ih); 244 sc->sc_ih = NULL; 245 } 246 bus_space_unmap(sc->sc_bst, sc->sc_bsh, cnl->cnl_size); 247 } 248
Indexes created Mon Sep 29 21:09:56 GMT 2025