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History log of /src/sys/arch/riscv/conf/std.riscv64
RevisionDateAuthorComments
 1.5  01-Jan-2025  skrll risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.
 1.4  13-Aug-2024  skrll risc-v: Allwinner D1 support

Add the Allwinnder D1 support provided by Rui-Xiang Guo and updated
but me.

https://mail-index.netbsd.org/port-riscv/2024/08/04/msg000127.html

Only driver listed as attaching in

https://github.com/picohive/netbsd-mangopi-mq-pro/blob/main/boot.log

have been added.

There is no need for the platform stuff as the board's u-boot is able
to load bootriscv64.efi and boot a generic kernel.
 1.3  07-May-2023  skrll branches: 1.3.6;
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
 1.2  11-Apr-2019  kamil Fix CVS Id usage
 1.1  28-Mar-2015  matt branches: 1.1.2; 1.1.18; 1.1.22;
Beginnings of RISCV kernel support. Note that the pmap support is not yet
committed and probably won't be for awhile. This is mostly preliminary
waiting for the supervisor specification to come out. Lots of missing pieces
but it mostly builds.
 1.1.22.1  10-Jun-2019  christos Sync with HEAD
 1.1.18.2  03-Dec-2017  jdolecek update from HEAD
 1.1.18.1  28-Mar-2015  jdolecek file std.riscv64 was added on branch tls-maxphys on 2017-12-03 11:36:38 +0000
 1.1.2.2  06-Apr-2015  skrll Sync with HEAD
 1.1.2.1  28-Mar-2015  skrll file std.riscv64 was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000
 1.3.6.1  02-Aug-2025  perseant Sync with HEAD

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