Improve cpu_idle() by allowing a platform specific implementaion (same logic as the sparc implementation) - currently only used by sun4v

branches: 1.84.6; 1.84.8;
G/C LS{SLEEP,RUN,ONPROC}

LWP status manipulation was moved out of assembly long ago.

Hopefully fix some problems seen with MP support on non-x86, in particular
where curcpu() is defined as curlwp->l_cpu:

- mi_switch(): undo the ~2007ish optimisation to unlock curlwp before
calling cpu_switchto(). It's not safe to let other actors mess with the
LWP (in particular l->l_cpu) while it's still context switching. This
removes l->l_ctxswtch.

- Move the LP_RUNNING flag into l->l_flag and rename to LW_RUNNING since
it's now covered by the LWP's lock.

- Ditch lwp_exit_switchaway() and just call mi_switch() instead. Everything
is in cache anyway so it wasn't buying much by trying to avoid saving old
state. This means cpu_switchto() will never be called with prevlwp ==
NULL.

- Remove some KERNEL_LOCK handling which hasn't been needed for years.

branches: 1.82.2;
cpu_need_resched():

- Remove all code that should be MI, leaving the bare minimum under arch/.
- Make the required actions very explicit.
- Pass in LWP pointer for convenience.
- When a trap is required on another CPU, have the IPI set it locally.
- Expunge cpu_did_resched().

branches: 1.81.14;
sun4v: Added handling of trap type 0x034 (address alignment error) + fixed typo mmfsa -> mmufsa. Verified for both sun4u and sun4v using qemu.

sun4v: implement missing handling of itsb traps 0x008 and 0x009. Based on code from OpenBSD. Tested using qemu.

branches: 1.79.2; 1.79.4;
sun4v: Implement missng MMU protection trap handling - mostly from OpenBSD

Avoid assembler-specific defines by using the export keyword in genassym.cf instead

sun4v: make device interrupts work. Introduce a new intrhand_alloc() function for allocation of interrupt handlers and adapt to this. Parts from OpenBSD. ok martin@

sun4v: Implement handling of cpu_mondo trap - from OpenBSD - tested using the Legion simulator

branches: 1.75.2;
sun4v: add code to enable startup of secondary cpus on both sun4u and sun4v systems - ok martin@

sun4v: All cpus must be setup with a TSB descriptor, so pmap_setup_tsb_sun4v() must take a pointer to the TSB descriptor

sun4v: Rename TLB_ defines to SUN4U_TLB_ so entries created using TSB_DATA() are properly setup for sun4u and sun4v. Relocate the cputyp variable from autoconf.c to locore.s and make it const in param.h so optimized code can be generated. Parts from OpenBSD. Optimization suggested by nakayama@. OK martin@, mrg@, nakayama@

sun4v: Add handling of spill/fill and dtsb miss traps (with a XXX to be handled later)

No need to make CI_MMFSA depend on SUN4V since the ci_mmfsa field is always present in the cpu_info struct now

Uncomment ifdef/endif and tabify.

sun4v: trap table setup - currently populated with dummy entries which will be properly implemented later - parts from OpenBSD - OK martin@

CI_UPAID has been renamed to CI_CPUID.

a) make the hunt through the cpus list more generic b) sun4v: ensure that the interrupt stack is mapped permanently and the TSB is setup properly - parts from OpenBSD. OK martin@

branches: 1.66.2; 1.66.12; 1.66.16;
add per ivec event counters

Add fast softint(9) support for sparc64.

Reviewed on port-sparc64.

branches: 1.64.6;
Retire struct user, remove sys/user.h inclusions. Note sys/user.h header
as obsolete. Remove USER_TO_UAREA/UAREA_TO_USER macros.

Various #include fixes and review by matt@.

Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits. Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

branches: 1.62.4;
Rename L_ADDR to L_PCB and amend some comments accordingly.

s/L_ADDR/L_PCB/, requested by rmind.

Remove advertising clause for UCB in various genassym.cf files,
which were derived from genassym.c in 4.4BSD-Lite2 (or 386BSD).
Closes PR misc/39573. Approved by martin@.

Remove a few components of struct lwp that we do not touch any more.

branches: 1.58.2; 1.58.6;
Move TNF licenses to 2 clause form

branches: 1.57.2;
include "opt_multiprocessor.h"

branches: 1.56.2;
Remove unused symbol

Make schedintr interrupt handler per-CPU.
While there rename tickintr interrupt handler and share initialization
code with schedintr.

Improve IPI handling:
- make IPI takes two arguments.
- add IPI event counters per-CPU.
- implement IPI functions which were missing or broken.
- insert DELAY while halting primary CPU in IPI handler.

- make interrupt pending list per-CPU.
- make tickintr() MP-safe.
- remove unused port-sparc derived interrupt code.

Ok by martin@.

Make TSBs and MMU contexts per-cpu.

Get rid of the IPI simple_lock.

branches: 1.50.6; 1.50.10;
Provide cpu_intr_p(), at least for non-MULTIPROCESSOR kernels.
Based on suggestions by Andrew Doran.

branches: 1.49.4; 1.49.6;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Cleanup cpu_info: get rid of ci_number and ci_upaid, use ci_index
and ci_cpuid instead.

Make cpufrequency and friends per cpu values.
Prepare a hz tick interrupt on secondary CPUs via %tick, but do not
enable it yet, as it breaks ddb.

branches: 1.46.2;
Remove INITSTACK completely - at the time we used to switch to it, we
already have access to all of lwp0 and it's uarea - so we can switch
to the correct lwp0 stack easily before calling main.

branches: 1.45.4; 1.45.8;
Simplify tf_tstate setting when leaving for userland initially - I seem
to have confused the if with the else case of the previous C code.
Funny that it worked at all.

Remove special case handling for userland lwps from cpu_lwp_fork, instead
do it in lwp_trampoline when we first return to userland.

page_idle_zero is now checked in MI code

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.41.6; 1.41.10; 1.41.12; 1.41.18;
SMP cleanup. provide support for multiple CPUs in DDB. (SMP itself
is still not working.)

cpu.h:
- add a pointer for DDB regs in SMP environment to struct cpu_info
- remove the #defines for mp_pause_cpus() and mp_resume_cpus()
cpuset.h:
- remove CPUSET_ALL() and rename CPUSET_ALL_BUT() to CPUSET_EXCEPT()
from petrov.
db_machdep.h:
- rename the members of db_regs_t to be the same as sparc
- change "db_regs_t ddb_regs" to "db_regs_t *ddb_regp" and change
all references to suit
- redo DDB_REGS to no longer be a pointer to a fixed data structure
but to one allocated per-cpu when ddb is entered
- move a bunch of prototypes in here
intr.h:
- remove SPARC64_IPI_* macros, no longer used
db_interface.c:
- change "db_regs_t ddb_regs" to "db_regs_t *ddb_regp" and change
all references to suit
- make "nil" a 64 bit entity
- change the ddb register access methods to work in multiprocessor
environment, it is now very much like sparc does it
- in kdb_trap() avoid accessing ddb_regp when it is NULL
- update several messages to include the cpu number
- unpause other cpus much later when resuming from ddb
- rename db_lock() to db_lock_cmd(), as the sparc-like code has
db_lock as a simple lock
- remove "mach cpus" command, and replace it with "mach cpu" (which
does the same) and also implement "mach cpu N" to switch to
another cpus saved trapframe
db_trace.c:
- update for the ddb_regs -> ddb_regp change
genassym.cf:
- add TF_KSTACK as offsetof(struct trapframe64, tf_kstack)
ipifuncs.c:
- overhaul extensively
- remove all normal interrupt handlers as IPI's, we now handle
them all specially in locore.s:interrupt_vector
- add a simplelock around all ipi functions - it's not safe for
multiple cpus to be sending IPI's to each other right now
- rename sparc64_ipi_pause() to sparc64_ipi_pause_thiscpu() and,
if DDB is configured, enable it to save the passed-in trapframe
to a db_regs_t for this cpu's saved DDB registers.
- remove the "ipimask" system (SPARC64_IPI_* macros) and instead
pass functions directly
- in sparc64_send_ipi() always set the interrupt arguments to 0,
the address and argument of the to be called function. (the
argument right now is the address of ipi_tlb_args variable, and
part of the reason why only one CPU can send IPI's at a time.)
don't wait forever for an IPI to complete. some of this is
from petrov.
- rename sparc64_ipi_{halt,pause,resume}_cpus() to
mp_{halt,pause,resume}_cpus()
- new function mp_cpu_is_paused() used to avoid access missing
saved DDB registers
- actually broadcast the flush in smp_tlb_flush_pte(),
smp_tlb_flush_ctx() and smp_tlb_flush_all(). the other end may
not do anything yet in the pte/ctx cases yet...
kgdb_machdep.c:
- rework for changed member names in db_regs_t.
locore.s:
- shave an instruction from syscall_setup() (set + ld -> sethi + ld)
- remove some old dead debug code
- add new sparc64_ipi_halt IPI entry point, it just calls the C
vector to shutdown.
- add new sparc64_ipi_pause IPI entry point, which just traps into
the debugger using the normal breakpoint trap. these cpus usually
lose the race in db_interface.c:db_suspend_others() and end up
calling the C vector sparc64_ipi_pause_thiscpu().
- add #if 0'ed code to sparc64_ipi_flush_{pte,ctx}() IPI entry
points to call the sp_ version of these functions.
- in rft_kernel (return from trap, kernel), check to see if the
%tpc is at the sparc64_ipi_pause_trap_point and if so, call
"done" not "retry"
- rework cpu_switch slightly: save the passed-in lwp instead of
using the one in curlwp
- in cpu_loadproc(), save the new lwp not the old lwp, to curlwp
- in cpu_initialize(), set %tl to zero as well. from petrov.
- in cpu_exit(), fix a load register confusion. from petrov.
- change some "set" in delay branch to "mov".
machdep.c:
- deal with function renames
pmap.c:
- remove a spurious space
trap.c:
- remove unused "trapstats" variable
- add cpu number to a couple of messages

branches: 1.40.6; 1.40.18;
Alter sparc64 bootstrap, catch up to ofwboot v1.9:

- Accept bootinfo structure passed down from ofwboot v1.9
- Drop kernel re-mapping code
- Use permanent 4MB mappings provided by the loader instead
- Change kernel entry address to point directly at the code instead of pointing
at the trap table's first slot. This allows the bootloader to detect
those kernels which are aware of the new boot scheme
- Due to the changes in kernel mapping code, alter secondary CPU bootstrap
code to use trampoline just like FreeBSD does (some FreeBSD code is used
here as well)

branches: 1.39.2;
merge ktrace-lwp.

Re-factor syscall, and make it use syscall_{plain,fancy}.

branches: 1.37.12;
remove cache_flush_virt() and PADDRT, they're no longer used.
allocate a stack frame for blast_dcache() when profiling so it shows up.
in dcache_flush_page(), use a stride of 32 instead of 16 to match the
cache line size. correct various comments.

Use want_resched from cpu_info area.

Replace intrcnts by evcnts. XXX - needs slight tweaking for MULTIPROCESSOR.

checkpoint of MP work from dennis and myself. includes cross-processor
interrupt framework, a sledgehammer TLB invalidation and misc MP fixes.
doesn't work at all yet.

Implement restartable atomic sequences (RAS) for sparc64.

Spinup secondary cpus. Based on codes sent to me by Dennis Chernoivanov
and Chuck Silvers.

Initial siginfo support for sparc64 (untested). COMPAT_16 sigcontext signal
delivery tested.

branches: 1.30.2;
Provide PAGE_SIZE to assembler source.

Make the pmap count resident/wired mappings on the fly instead of
walking the page tables whenever this information is needed.

Add an option PMAP_COUNT_DEBUG to assert the new counts and the
page table walk agree.

The old solution had very bad performance impact, for example
by the high CPU load when running top(1).

Thanks to Simon Burge for pointing at the cause of the problem and
to Valeriy E. Ushakov for optimizing my simple minded assembler code.

Merge the nathanw_sa branch.

Remove include of <sys/map.h>, since it's gone now (and wasn't used
here anyway).

Trapframes only have locals or ins if the kernel is compiled DEBUG.

branches: 1.25.4; 1.25.8;
clean up for fd changes.

Remove bsd_openprom.h, which is only for compatibility with the sparc port.

branches: 1.23.2;
Add some useful mbuf fields.

branches: 1.22.4;
Add UVM_PAGEIDLE_ZERO.

Define UVM_PAGE_IDLE_ZERO.

Move some macro definitions out of genassym and into locore.s

Prevent interrupts from being posted if they are active and deprecate polled
interrupts. This seems to eliminate the spurious interrupts.

Clean up interrupt handling some more.

Fix interrupt delivery on UltraSPARC IIi machines.

With these changes the kernel seems almost stable again.

branches: 1.15.2;
Have separate data and text segments, make text read-only.

branches: 1.14.2;
Introduce a new process state distinct from SRUN called SONPROC
which indicates that the process is actually running on a
processor. Test against SONPROC as appropriate rather than
combinations of SRUN and curproc. Update all context switch code
to properly set SONPROC when the process becomes the current
process on the CPU.

Add proc->md->fpstate and GSR to fpstate.

Explicitly use 64-bit types.

branches: 1.11.8; 1.11.10; 1.11.14;
COMPAT_SPARC32 -> COMPAT_NETBSD32

Add FS_SIZE.

Use block load/store in pmap_zero_page()/pmap_copy_page().

Fix more syscall32 and signal breakage.

SYS_sigreturn -> SYS___sigreturn14.

Fixup signal changes (hopefully). However SUN_COMPAT is likely broken by
this and I don't know how to fix it.

We can now exec a 64-bit init through a really ugly hack (don't ask.)

It slices. It dices. It does everything except exec a sparc32_compat init.

Assign copyright to TNF.

Merge paddr_t changes into the main branch.

branches: 1.2.2;
Make this work for a change.

General update:

Added genassym.cf
Removed lderr which should never have gotten in
Removed lots of dead code from locore.s
Added some softint stuff to intr.c
Added support for halt -p
esp and le both use bus_dmamap_*() functions now
instead of kdvma_mapin()
groundwork for PCI (but we still have no drivers for
any sun4u PCI devices)