History log of /src/sys/arch/x86/x86/coretemp.c
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Revision tags: perseant-exfatfs-base-20250801 netbsd-11-base
# 1.42 15-Jul-2024 gutteridge

coretemp.c: drop redundant condition (NFCI)

Checking for a processor model upper limit has no point inside a block
that is already limited further. Noted from code inspection by Sotiris
Lamprinidis in PR kern/58372.

While here, also update to a cached version of an URL for processor
references, as both original URLs have now been removed by Intel.


Revision tags: perseant-exfatfs-base-20240630 perseant-exfatfs-base
# 1.41 12-Mar-2024 gutteridge

branches: 1.41.2;
coretemp.c: don't accept impossibly low TjMax values

r. 1.39 introduced a regression where instead of applying a reasonable
default maximum (as was done prior to that change), incorrect values
were accepted and applied, as failures to retrieve an expected MSR
value weren't accounted for.

Apply different logic for unexpectedly low vs. high maximums, with
distinct warnings for each. Also add another warning about a retrieval
failure right at the outset (which also just uses the default, then).

This change fundamentally doesn't address the fact that
__SHIFTOUT(msr, MSR_TEMP_TARGET_READOUT)
doesn't necessarily return a valid value. It just restores prior
behaviour, which is more reasonable than applying a zero value, which
started happening on some older hardware. (I infer this is most likely
an issue with dated generations of Intel hardware with this feature.)
The challenge is that this evidently isn't all documented properly
anywhere. Various "magic values" in this driver need further
investigation.

While here, also fix output so warnings are cleanly formatted, rather
than the slightly scrambled way they were appearing.

Tested on older Intel hardware I had on hand:
E7500 (now falls back to default 100 rather than 0)
E5540 (successfully retrieves 97, as before)
i5-3340M (successfully retrieves 105, as before)


# 1.40 29-Feb-2024 gutteridge

coretemp.c: fix grammar in a warning message

(I get several of these warnings on boot on a particular machine. Now,
it also seems that the code isn't retrieving the correct value, either;
TBD.)


Revision tags: thorpej-ifq-base thorpej-altq-separation-base
# 1.39 13-Jul-2023 msaitoh

coretemp(4): Change limits of Tjmax.

- Change the lower limit from 70 to 60. At least, some BIOSes can change
the value down to 62.
- Change the upper limit from 110 to 120. At least, some BIOSes can change
the value up to 115.
- Print error message when rdmsr(TEMPERATURE_TARGET) failed.
- When Tjmax exceeded the limit, print warning message and use the value
as it is.


Revision tags: netbsd-10-base bouyer-sunxi-drm-base
# 1.38 07-Oct-2021 msaitoh

branches: 1.38.4;
KNF. No functional change.


Revision tags: thorpej-i2c-spi-conf2-base thorpej-futex2-base thorpej-cfargs2-base cjep_sun2x-base1 cjep_sun2x-base cjep_staticlib_x-base1 cjep_staticlib_x-base thorpej-i2c-spi-conf-base thorpej-cfargs-base thorpej-futex-base bouyer-xenpvh-base2 phil-wifi-20200421 bouyer-xenpvh-base1 phil-wifi-20200411 bouyer-xenpvh-base phil-wifi-20200406
# 1.37 27-Mar-2020 msaitoh

Add special handling for model 0x0f stepping >=2 or mode 0x0e to get Tjmax.


Revision tags: is-mlppp-base ad-namecache-base3 netbsd-9-0-RELEASE netbsd-9-0-RC2 ad-namecache-base2 ad-namecache-base1 ad-namecache-base netbsd-9-0-RC1 phil-wifi-20191119 netbsd-9-base phil-wifi-20190609 isaki-audio2-base pgoyette-compat-20190127 pgoyette-compat-20190118 pgoyette-compat-1226 pgoyette-compat-1126 pgoyette-compat-1020 pgoyette-compat-0930 pgoyette-compat-0906 pgoyette-compat-0728
# 1.36 11-Jul-2018 msaitoh

branches: 1.36.4;
- Detect and set Atom's Tj(max) to 90 if it's not the 45nm D400/D500/N400
series (90 for Diamondville and 100 for Pineview). From FreeBSD r221509.
- Reduce diff a little against FreeBSD.


Revision tags: netbsd-8-0-RELEASE phil-wifi-base pgoyette-compat-0625 netbsd-8-0-RC2 pgoyette-compat-0521 pgoyette-compat-0502 pgoyette-compat-0422 netbsd-8-0-RC1 pgoyette-compat-0415 pgoyette-compat-0407 pgoyette-compat-0330 pgoyette-compat-0322 pgoyette-compat-0315 pgoyette-compat-base tls-maxphys-base-20171202 matt-nb8-mediatek-base nick-nhusb-base-20170825 perseant-stdc-iso10646-base netbsd-8-base prg-localcount2-base3 prg-localcount2-base2 prg-localcount2-base1 prg-localcount2-base pgoyette-localcount-20170426 bouyer-socketcan-base1 jdolecek-ncq-base pgoyette-localcount-20170320 nick-nhusb-base-20170204 bouyer-socketcan-base pgoyette-localcount-20170107 nick-nhusb-base-20161204 pgoyette-localcount-20161104 nick-nhusb-base-20161004 localcount-20160914 pgoyette-localcount-20160806 pgoyette-localcount-20160726 pgoyette-localcount-base nick-nhusb-base-20160907
# 1.35 07-Jul-2016 msaitoh

branches: 1.35.10; 1.35.16; 1.35.18;
KNF. Remove extra spaces. No functional change.


Revision tags: nick-nhusb-base-20160529 nick-nhusb-base-20160422 nick-nhusb-base-20160319 nick-nhusb-base-20151226 nick-nhusb-base-20150921 nick-nhusb-base-20150606
# 1.34 27-May-2015 msaitoh

- Change the Upper limit of Tjmax from 100 to 110 because some new
CPUs have 105. This change is the same as FreeBSD.
- Print Tjmax with aprint_verbose().
- Reduce the diff against FreeBSD.


# 1.33 23-Apr-2015 pgoyette

Update module dependencies for all the existing modules that depend on sysmon components.


Revision tags: netbsd-7-0-RC2 netbsd-7-0-RC1 nick-nhusb-base-20150406 nick-nhusb-base netbsd-7-base yamt-pagecache-base9 tls-earlyentropy-base riastradh-xf86-video-intel-2-7-1-pre-2-21-15 riastradh-drm2-base3 rmind-smpnet-nbase rmind-smpnet-base tls-maxphys-base
# 1.32 17-Nov-2013 martin

branches: 1.32.4; 1.32.6;
Remove unused variable


# 1.31 15-Nov-2013 msaitoh

Modify some macros and add some new macros for CPU family and model
to reduce code duplication and to avoid bug.

CPUID_TO_STEPPING(cpuid) (not changed)

CPUID_TO_FAMILY(cpuid) (new)
CPUID_TO_MODEL(cpuid) (new)

Return the display family and the display model.
The macro names are the same as FreeBSD.

CPUID_TO_BASEFAMILY(cpuid) (The old name was CPUID2FAMILY)
CPUID_TO_BASEMODEL(cpuid) (The old name was CPUID2MODEL)

Only for the base field.

CPUID_TO_EXTFAMILY(cpuid) (The old name was CPUID2EXTFAMILY)
CPUID_TO_EXTMODEL(cpuid) (The old name was CPUID2EXTMODEL)

Only for the extended field.

See http://mail-index.netbsd.org/port-amd64/2013/11/12/msg001978.html


# 1.30 12-Nov-2013 msaitoh

Fix calculation of the cpu model (display model) in coretemp_tjmax().
The CPUID2MODEL() macro returns only low 4bit, so the checking against 0x17
doesn't work correctly. The correct way is to use the display model.
Remove incorrect extmodel check. Same as FreeBSD.


Revision tags: riastradh-drm2-base2 riastradh-drm2-base1 riastradh-drm2-base agc-symver-base yamt-pagecache-base8 yamt-pagecache-base7 yamt-pagecache-base6
# 1.29 14-Aug-2012 jruoho

branches: 1.29.2; 1.29.4;
Collect rnd(9) entropy from coretemp(4), acpibat(4), aibs(4), hpacel(4),
thinkpad(4), and aps(4).


Revision tags: netbsd-6-0-6-RELEASE netbsd-6-1-5-RELEASE netbsd-6-1-4-RELEASE netbsd-6-0-5-RELEASE netbsd-6-1-3-RELEASE netbsd-6-0-4-RELEASE netbsd-6-1-2-RELEASE netbsd-6-0-3-RELEASE netbsd-6-1-1-RELEASE netbsd-6-0-2-RELEASE netbsd-6-1-RELEASE netbsd-6-1-RC4 netbsd-6-1-RC3 netbsd-6-1-RC2 netbsd-6-1-RC1 netbsd-6-0-1-RELEASE matt-nb6-plus-nbase netbsd-6-0-RELEASE netbsd-6-0-RC2 matt-nb6-plus-base netbsd-6-0-RC1 jmcneill-usbmp-base10 yamt-pagecache-base5 jmcneill-usbmp-base9 yamt-pagecache-base4 jmcneill-usbmp-base8 jmcneill-usbmp-base7 jmcneill-usbmp-base6 jmcneill-usbmp-base5 jmcneill-usbmp-base4 jmcneill-usbmp-base3 jmcneill-usbmp-pre-base2 jmcneill-usbmp-base2 netbsd-6-base jmcneill-usbmp-base jmcneill-audiomp3-base yamt-pagecache-base3 yamt-pagecache-base2 yamt-pagecache-base
# 1.28 06-Oct-2011 jruoho

branches: 1.28.2;
Like the comment says, also MSR_IA32_EXT_CONFIG is unsafe; use rdmsr_safe().
Fixes the panic reported by njoly@.


# 1.27 24-Sep-2011 jruoho

Use rdmsr_safe() when reading IA32_TEMPERATURE_TARGET.


Revision tags: jym-xensuspend-nbase jym-xensuspend-base
# 1.26 20-Jun-2011 pgoyette

Inialize sensor state before registering.


Revision tags: rmind-uvmplock-nbase cherry-xenmp-base rmind-uvmplock-base
# 1.25 19-Mar-2011 ahoka

branches: 1.25.2;
Dont try to read MSR_TEMPERATURE_TARGET on Core Duo Yonah


# 1.24 18-Mar-2011 jruoho

Comment out IA32_TEMPERATURE_TARGET temporarily.


Revision tags: bouyer-quota2-nbase
# 1.23 04-Mar-2011 jruoho

Only attach on the first SMT ID (as in revision 1.16).


# 1.22 24-Feb-2011 jruoho

Fix autoconf(9) of cpufeaturebus.


# 1.21 21-Feb-2011 jruoho

Call pmf_device_deregister(9) during detach.


# 1.20 21-Feb-2011 jruoho

Add couple of additional CPU model checks for the undocumented Tj(max).


# 1.19 21-Feb-2011 jruoho

Use constants and bits(3), and fix a typo.


# 1.18 20-Feb-2011 jruoho

Add proper definitions. Remove (too) verbose comments. Remove (wrong) debug
printf. Do not mark the sensor as invalid based on whether the critical
detector output signal has (ever) been asserted without reset. Support for
trip-points will be added later.


# 1.17 20-Feb-2011 jruoho

Modularize coretemp(4). Ok jmcneill@.


Revision tags: uebayasi-xip-base7 bouyer-quota2-base jruoho-x86intr-base matt-mips64-premerge-20101231 uebayasi-xip-base6 uebayasi-xip-base5 uebayasi-xip-base4 uebayasi-xip-base3 yamt-nfs-mp-base11
# 1.16 25-Aug-2010 jruoho

branches: 1.16.2; 1.16.4;
Add definitions for Intel Digital Thermal Sensor and Power Management, at
CPUID Fn0000_0006, %eax, %ecx. Use these instead of magic numbers.


Revision tags: uebayasi-xip-base2
# 1.15 15-Aug-2010 mrg

only attach on SMT ID 0 cpus.

on my i7, cpus 0/4, 1/5, 2/6 and 3/7 have identical information and the
processor manual says that there are only 4 actual sensors.


this still doesn't attach (yet) on that system, due to a core solo/duo
errata being wrongly applied, but i haven't figured out the right way
to do that.


Revision tags: yamt-nfs-mp-base10 uebayasi-xip-base1
# 1.14 14-Mar-2010 pgoyette

branches: 1.14.2;
Remove setting of the edata->monitor since that member no longer exists.


Revision tags: yamt-nfs-mp-base9 uebayasi-xip-base matt-premerge-20091211
# 1.13 03-Dec-2009 sborrill

branches: 1.13.2;
CPU model and CPU extended model cannot simply be summed; the extended model
differentiates different CPUs within a given model type (i.e. model 0xe with
extended model 0x1 is NOT the same as a model 0xf).
Modern Xeons do not support MSR_IA32_EXT_CONFIG, so use model and extended
model correctly to avoid it


Revision tags: yamt-nfs-mp-base8 yamt-nfs-mp-base7 jymxensuspend-base yamt-nfs-mp-base6 yamt-nfs-mp-base5 yamt-nfs-mp-base4 yamt-nfs-mp-base3 nick-hppapmap-base4 nick-hppapmap-base3 nick-hppapmap-base
# 1.12 25-Mar-2009 dyoung

It is only by accident that these get definitions they need from
<sys/device.h>, so explicitly #include <sys/device.h>.


Revision tags: netbsd-5-0-2-RELEASE matt-nb5-mips64-premerge-20091211 matt-nb5-mips64-u2-k2-k4-k7-k8-k9 matt-nb4-mips64-k7-u2a-k9b matt-nb5-mips64-u1-k1-k5 netbsd-5-0-1-RELEASE netbsd-5-0-RELEASE netbsd-5-0-RC4 netbsd-5-0-RC3 nick-hppapmap-base2 netbsd-5-0-RC2 netbsd-5-0-RC1 haad-dm-base2 haad-nbase2 ad-audiomp2-base netbsd-5-base matt-mips64-base2 haad-dm-base1 wrstuden-revivesa-base-4 haad-dm-base mjf-devfs2-base
# 1.11 23-Sep-2008 christos

branches: 1.11.2; 1.11.4; 1.11.8; 1.11.12;
PR/39458: Juan RP: avoid attaching coretemp on systems that don't have it
by checking the read valid bit.


Revision tags: wrstuden-revivesa-base-3 wrstuden-revivesa-base-2 wrstuden-revivesa-base-1 simonb-wapbl-nbase yamt-pf42-base4 simonb-wapbl-base yamt-pf42-base3 hpcarm-cleanup-nbase yamt-pf42-base2 yamt-nfs-mp-base2 wrstuden-revivesa-base
# 1.10 11-May-2008 ad

branches: 1.10.4;
Don't abuse ci_cpuid - in particular, ci_cpuid != ci_signature.


Revision tags: yamt-pf42-baseX yamt-pf42-X yamt-nfs-mp-base yamt-pf42-base ad-socklock-base1 yamt-lazymbuf-base15 yamt-lazymbuf-base14 keiichi-mipv6-nbase nick-net80211-sync-base keiichi-mipv6-base matt-armv6-nbase mjf-devfs-base hpcarm-cleanup-base
# 1.9 28-Jan-2008 xtraeme

branches: 1.9.6; 1.9.8; 1.9.10; 1.9.12;
coretemp_refresh: run xc_unicast() regardless if sc->sc_ci is curcpu()
or not, this fixes a deadlock seen by Greg Oster in a Dual Quad Core
machine with 8 coretemp instances.


# 1.8 28-Jan-2008 xtraeme

Pass the same size to both kmem_alloc(9) and kmem_free(9), this fixes
the kmem_poison_check in DEBUG kernels.


Revision tags: bouyer-xeni386-nbase bouyer-xeni386-base matt-armv6-base
# 1.7 04-Jan-2008 ad

Start detangling lock.h from intr.h. This is likely to cause short term
breakage, but the mess of dependencies has been regularly breaking the
build recently anyhow.


# 1.6 04-Jan-2008 xtraeme

machine/cpufunc.h is required now.


Revision tags: vmlocking2-base3
# 1.5 21-Dec-2007 xtraeme

After comments from joerg@, backout previous and use 'cpuN'.


# 1.4 21-Dec-2007 xtraeme

Change the description to 'coreN' rather than 'cpuN', which seems to
be more correct.


Revision tags: yamt-kmem-base3 cube-autoconf-base yamt-kmem-base2 yamt-kmem-base vmlocking2-base2 reinoud-bufcleanup-nbase reinoud-bufcleanup-base vmlocking2-base1 vmlocking-nbase jmcneill-pm-base
# 1.3 22-Nov-2007 xtraeme

branches: 1.3.2; 1.3.4; 1.3.8;
Use the returned value of xc_unicast() on xc_wait(), that will wait
for completion on the CPU running the xcall thread.

Tested on a 8-way Xeon by Greg Oster.


Revision tags: bouyer-xenamd64-base bouyer-xenamd64-base2
# 1.2 16-Nov-2007 xtraeme

Extend the envsys2 API (one more time, sorry) as defined in:

http://mail-index.netbsd.org/tech-kern/2007/11/09/0001.html

sysmon_envsys_create() and sysmon_envsys_destroy() were added to
create/destroy sysmon_envsys objects (and its TAILQ/LIST for sensors/events).

sysmon_envsys_sensor_attach() and sysmon_envsys_sensor_detach() were
added to attach/detach sensors to a specified sysmon_envsys device.

The events framework is now per device and configurable via the
ENVSYS_SETDICTIONARY ioctl or /etc/envsys.conf and envstat(8).

Update all users and documentation to reflect these changes.


Revision tags: jmcneill-base
# 1.1 29-Oct-2007 xtraeme

branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8; 1.1.10;
Add coretemp(4). A new driver for Intel Core's on-die thermal sensor,
available on Intel Core or newer CPUs.

Ported from FreeBSD. Tested by rmind on i386 and joerg on amd64.

Enabled with "options INTEL_CORETEMP".