| History log of /src/usr.sbin/cpuctl/arch/aarch64.c |
| Revision | | Date | Author | Comments |
| 1.25 |
| 07-Oct-2024 |
jakllsch | CPU ID strings for Arm Cortex-A710, Neoverse V1, Neoverse N2, and Fujitsu A64FX
|
| 1.24 |
| 27-Sep-2024 |
jakllsch | add Ampere 1 and 1A
|
| 1.23 |
| 07-Feb-2024 |
msaitoh | Remove ryo@'s mail addresses.
|
| 1.22 |
| 03-Feb-2023 |
skrll | MPIDR is 64bits. Without this AFF3 would always be zero.
Spotted by Cyprien.
|
| 1.21 |
| 30-Apr-2022 |
ryo | branches: 1.21.2;
add CPU_ID_APPLE_M1_ICESTORM and CPU_ID_APPLE_M1_FIRESTORM.
sync cpuids[] to sys/arch/aarch64/aarch64/cpu.c r1.69
|
| 1.20 |
| 06-Jan-2022 |
ryo | display the raw value of each field when -v specified
|
| 1.19 |
| 06-Jan-2022 |
ryo | fix typo
|
| 1.18 |
| 06-Jan-2022 |
ryo | Added more field definitions for ARMv8.x system registers
|
| 1.17 |
| 06-Jan-2022 |
ryo | macroify. NFC.
|
| 1.16 |
| 05-Jan-2022 |
ryo | fix ID_AA64ISAR0_EL1.ATOMIC field definition
|
| 1.15 |
| 17-May-2021 |
riastradh | Teach cpuctl(8) about some additional aarch64 feature bits.
(Descriptions for CSV3 and CSV2 are not very good, but the blurbs in
the arm arm are an entire paragraph long each. Please fix if you have
a conciser summary!)
|
| 1.14 |
| 16-Jan-2021 |
jmcneill | branches: 1.14.2;
ID_AA64PFR0_EL1.GIC=0 means that the CPU interface system registers are
not implemented. This does not necessarily mean that there is no GIC in the
system, as GICv2 uses MMIO instead of system registers for the CPU
interface.
While here, add description for GIC=3, which means that the v4.1 system
register interface is supported.
|
| 1.13 |
| 04-Jan-2021 |
ryo | sync cpuids[] of sys/arch/aarch64/aarch64/cpu.c r1.43
|
| 1.12 |
| 10-Oct-2020 |
jmcneill | Report half-precision FP and SIMD support
|
| 1.11 |
| 05-Jul-2020 |
riastradh | (cpuctl/aarch64) Add some more aa64isar0_eli1 flags.
|
| 1.10 |
| 01-Jul-2020 |
ryo | show clidr_el1 and ctr_el0.
|
| 1.9 |
| 10-May-2020 |
riastradh | Teach cpuctl(8) about ARMv8.5-RNG RNDR/RNDRRS support.
|
| 1.8 |
| 28-Jan-2020 |
maxv | More identification.
|
| 1.7 |
| 09-May-2019 |
mrg | add cortex A-76 detection.
|
| 1.6 |
| 23-Jan-2019 |
skrll | Fix mvfr0.fptrap = 0 description
|
| 1.5 |
| 20-Dec-2018 |
ryo | - show detail of debug feature register (ID_AA64DFR0_EL1)
- print raw value of registers when verbose flag is set.
- keep forward compatibility. read kernel's aarch64_sysctl_cpu_id, but avoid unknown system registers.
|
| 1.4 |
| 26-Nov-2018 |
ryo | Add ThunderX IDs
|
| 1.3 |
| 20-Nov-2018 |
mrg | rewrite the CPU identification on arm64:
- publish per-cpu data
- publish a whole bunch of info in struct aarch64_sysctl_cpu_id
instead of various individual nodes (there are 16 total.)
- add MIDR extractor bits
- define ARMv8.2-A id_aa64mmfr2_el1 and id_aa64zfr0_el1 regs,
but avoid using them until we make sure they exist. (these
members are added to aarch64_sysctl_cpu_id to avoid future
compat issues.)
the arm32 and aarch32 version of these need to be adjusted as
well (and aarch32 data published at all.) still trying to
work out how to make the same userland binary running on a
real arm32 or an aarch32 system can work sanely here.
ok ryo@.
|
| 1.2 |
| 08-May-2018 |
ryo | branches: 1.2.2; 1.2.4;
TGran64 indication was actually the opposite
|
| 1.1 |
| 03-May-2018 |
ryo | add aarch64 support for cpuctl identify.
|
| 1.2.4.2 |
| 08-Apr-2020 |
martin | Merge changes from current as of 20200406
|
| 1.2.4.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.2.2.5 |
| 26-Jan-2019 |
pgoyette | Sync with HEAD
|
| 1.2.2.4 |
| 26-Dec-2018 |
pgoyette | Sync with HEAD, resolve a few conflicts
|
| 1.2.2.3 |
| 26-Nov-2018 |
pgoyette | Sync with HEAD, resolve a couple of conflicts
|
| 1.2.2.2 |
| 21-May-2018 |
pgoyette | Sync with HEAD
|
| 1.2.2.1 |
| 08-May-2018 |
pgoyette | file aarch64.c was added on branch pgoyette-compat on 2018-05-21 04:36:19 +0000
|
| 1.14.2.1 |
| 31-May-2021 |
cjep | sync with head
|
| 1.21.2.2 |
| 03-Oct-2024 |
martin | Pull up following revision(s) (requested by jakllsch in ticket #922):
sys/arch/aarch64/aarch64/cpu.c: revision 1.79
sys/arch/arm/include/cputypes.h: revision 1.17
usr.sbin/cpuctl/arch/aarch64.c: revision 1.24
sys/arch/aarch64/aarch64/cpu.c: revision 1.80
Add Ampere 1 and 1A CPU IDs
refine previous
add Ampere 1 and 1A
|
| 1.21.2.1 |
| 20-Sep-2024 |
martin | Pull up following revision(s) (requested by rin in ticket #869):
usr.sbin/cpuctl/arch/aarch64.c: revision 1.22
sys/arch/aarch64/aarch64/cpu.c: revision 1.73
Remove useless/harmful casts in debug messages. MPIDR AFF3 would not
be printed before.
MPIDR is 64bits. Without this AFF3 would always be zero.
Spotted by Cyprien.
|
