Lines Matching defs:the
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
36 /* The offset for pc-relative addressing is currently defined to be 0. */
41 /* An enum containing all known CPU features. The values act as bit positions
358 Then use REP_NO_SEP in the SEP field. */
375 /* These macros take an initial argument X that gives the index into
376 an aarch64_feature_set. The macros then return the bitmask for
389 /* A mask of the features that are enabled by each architecture version,
485 /* Architectures are the sum of the base and extensions. */
592 including all the features that are enabled by default for that architecture
620 version ARCH, and additionally provides the N features listed in "...". */
627 /* An aarch64_feature_set initializer for the N features listed in "...". */
735 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
736 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
737 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
739 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
745 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
753 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
758 AARCH64_OPND_COND, /* Standard condition as the last operand. */
759 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
772 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
775 is only used to support the programmer-
776 friendly feature of using LDR/STR as the
777 the mnemonic name for LDUR/STUR instructions
1012 AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */
1042 indicating the operand data size or a specific register. */
1050 size or the size of each SIMD vector element in the case of a SIMD
1053 indicate the size of data element a load/store instruction is
1055 They are also used for the immediate shift operand in e.g. SSHR. Such
1056 a use is only for the ease of operand encoding/decoding and qualifier
1057 sequence matching; such a use should not be applied widely; use the value
1065 4 x 1 byte or 2 x 2 byte are selected by the instruction. Other than that
1075 They are also used for the immediate shift operand in e.g. SSHR. Such
1076 a use is only for the ease of operand encoding/decoding and qualifier
1077 sequence matching; such a use should not be applied widely; use the value
1112 /* Special qualifier helping retrieve qualifier information during the
1247 the,
1381 /* FIXME: improve the efficiency. */
1403 /* The name of the mnemonic. */
1406 /* The opcode itself. Those bits which will be filled in with
1410 /* The opcode mask. This is used by the disassembler. This is a
1411 mask containing ones indicating those bits which must match the
1425 /* An array of operand codes. Each code is an index into the
1426 operand table. They appear in the order which the operands must
1431 code qualifies the corresponding operand code. Each operand
1439 /* Extra constraints on the instruction that the verifier checks. */
1443 are required to have the same register number. */
1454 /* Table describing all the AArch64 opcodes. */
1460 /* Disassembly preference priority 1-3 (the larger the higher). If nothing
1461 is specified, it is the priority 0 by default, i.e. the lowest priority. */
1467 /* Instruction has the field of 'sf'. */
1469 /* Instruction has the field of 'size:Q'. */
1471 /* Floating-point instruction has the field of 'type'. */
1473 /* AdvSIMD scalar instruction has the field of 'size'. */
1487 /* Default value for the optional operand when omitted from the assembly. */
1490 encoded/decoded by converting it to/from the real form, followed by
1491 the encoding/decoding according to the rules of the real opcode.
1492 This compares to the direct coding using the alias's information.
1496 friendly pseudo instruction available only in the assembly code (thus will
1497 not show up in the disassembly). */
1501 /* Instruction has the field of 'N'; used in conjunction with F_SF. */
1505 /* Instruction has the field of 'sz'. */
1516 /* Instruction takes a pair of optional operands. If we specify the Nth operand
1520 /* This instruction does not allow the full range of values that the
1521 width of fields in the assembler instruction would theoretically
1522 allow. This impacts the constraints on assembly but yields no
1525 /* For the instruction with size[22:23] field. */
1527 /* RCPC3 instruction has the field of 'size'. */
1529 /* This instruction need VGx2 or VGx4 mandatorily in the operand passed to
1534 Note the overlap between the set of subclass flags in each logical category
1535 (F_LDST_*, F_ARITH_*, F_BRANCH_* etc.); The usage of flags as
1575 /* This instruction has a predication constraint on the instruction at PC+4. */
1577 /* This instruction's operation width is determined by the operand with the
1611 /* Whether the opcode has the specific subclass flag.
1612 N.B. The overlap between F_LDST_*, F_ARITH_*, and F_BRANCH_* etc. subclass
1613 flags means that the callers of this function have the responsibility of
1614 checking for the flags appropriate for the specific iclass. */
1621 /* Deal with two possible scenarios: If F_OP_PAIR_OPT not set, as is the case
1747 /* A list of names with the first one as the disassembly preference;
1767 /* The 32-bit index register. */
1770 /* The first (or only) immediate offset. */
1773 /* The last immediate offset minus the first immediate offset.
1774 Unlike the range size, this is guaranteed not to overflow
1775 when the end offset > the start offset. */
1779 /* The vector group size, or 0 if none. */
1792 /* The difference between the nth and the n+1th register. */
1848 /* The encoding of the system register. */
1851 /* The system register flags. */
1859 /* The encoding of the PSTATE field. */
1867 /* Operand shifter; in use when the operand is a register offset address,
1873 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1880 cases, we need to tell libopcodes to skip the
1881 constraint checking and the encoding for this
1882 operand, so that the libopcodes can pick up the
1883 right opcode before the operand is fixed-up. This
1884 flag should only be used during the
1886 unsigned present:1; /* Whether this operand is present in the assembly
1887 line; not used during the disassembly. */
1894 It is used during both the assembling and disassembling. The assembler
1895 fills an aarch64_inst after a successful parsing and then passes it to the
1896 encoding routine to do the encoding. During the disassembling, the
1897 disassembler calls the decoding routine to decode a binary instruction; on a
1898 successful return, such a structure will be filled with information of the
1899 instruction; then the disassembler uses the information to print out the
1904 /* The value of the binary instruction. */
1917 /* Defining the HINT #imm values for the aarch64_hint_options. */
1934 Less severe error found during the parsing, very possibly because that
1935 GAS has picked up a wrong instruction template for the parsing.
1938 The instruction forms (or is expected to form) part of a sequence,
1939 but the preceding instruction in the sequence wasn't the expected one.
1940 The message refers to two strings: the name of the current instruction,
1941 followed by the name of the expected preceding instruction.
1944 Same as AARCH64_OPDE_A_SHOULD_FOLLOW_B, but shifting the focus
1945 so that the current instruction is assumed to be the incorrect one:
1946 "since the previous instruction was B, the current one should be A".
1956 No syntax error, but the operands are not a valid combination, e.g.
1959 The following errors are only reported against an asm string that is
1963 Error about a "VGx<n>" modifier in a ZA index not having the
1965 AARCH64_OPDE_REG_LIST_LENGTH, since both errors relate to the number
1966 of vectors that an instruction operates on. However, the "VGx<n>"
1969 importance on the register list length when selecting an opcode table
1976 opcode entry that supports the given number of registers.
1979 Error about a register list operand having the correct number
1982 that the length is known to be correct. However, it is lower than
1984 the same number of registers but have different strides.
1987 The asm failed to use the same immediate for a destination operand
1991 The asm failed to use the same register for a destination operand
2002 Error of the highest severity and used for any severe issue that does not
2003 fall into any of the above categories.
2006 A register was syntactically valid and had the right type, but it was
2007 outside the range supported by the associated operand field. This is
2009 would accept the operands that precede the erroneous one (if any) and
2013 AARCH64_OPDE_FATAL_SYNTAX_ERROR are only detected by GAS while the
2015 only libopcodes has the information about the valid variants of each
2018 The enumerators have an increasing severity. This is helpful when there are
2020 FMOV); this mechanism will help choose the most suitable template from which
2021 the generated diagnostics can most closely describe the issues, if any.
2064 /* The instructions in the sequence, starting with the one that
2067 /* The number of instructions already in the sequence. */
2069 /* The number of instructions allocated to the sequence. */
2084 /* Given the opcode enumerator OP, return the pointer to the corresponding
2091 the callback within this structure is used to apply styling to the
2092 disassembler output. This structure encapsulates the callback and a
2097 /* The callback used to apply styling. Returns a string created from FMT
2098 and ARGS with STYLE applied to the string. STYLER is a pointer back
2099 to this object so that the callback can access the state member.
2101 The string returned from this callback must remain valid until the
2108 /* A pointer to a state object which can be used by the apply_style
2113 /* Generate the string representation of an operand. */
2149 /* Given an operand qualifier, return the expected data element size
Indexes created Fri Mar 27 00:22:57 UTC 2026