Lines Matching defs:in_src1
378 INT in_src1 = -1;
380 in_src1 = FLD (in_src1);
384 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
407 INT in_src1 = -1;
411 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
434 INT in_src1 = -1;
438 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
461 INT in_src1 = -1;
465 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
488 INT in_src1 = -1;
492 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
515 INT in_src1 = -1;
519 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
542 INT in_src1 = -1;
546 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
677 INT in_src1 = -1;
679 in_src1 = FLD (in_src1);
683 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
771 INT in_src1 = -1;
773 in_src1 = FLD (in_src1);
777 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
793 INT in_src1 = -1;
797 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
813 INT in_src1 = -1;
815 in_src1 = FLD (in_src1);
819 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
835 INT in_src1 = -1;
839 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
855 INT in_src1 = -1;
857 in_src1 = FLD (in_src1);
861 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
877 INT in_src1 = -1;
881 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1441 INT in_src1 = -1;
1443 in_src1 = FLD (in_src1);
1447 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1463 INT in_src1 = -1;
1465 in_src1 = FLD (in_src1);
1469 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1485 INT in_src1 = -1;
1487 in_src1 = FLD (in_src1);
1491 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1507 INT in_src1 = -1;
1509 in_src1 = FLD (in_src1);
1513 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1554 INT in_src1 = -1;
1556 in_src1 = FLD (in_src1);
1560 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1576 INT in_src1 = -1;
1578 in_src1 = FLD (in_src1);
1582 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1598 INT in_src1 = -1;
1600 in_src1 = FLD (in_src1);
1604 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1620 INT in_src1 = -1;
1622 in_src1 = FLD (in_src1);
1626 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1752 in_sr = FLD (in_src1);
1772 in_sr = FLD (in_src1);
1875 INT in_src1 = -1;
1877 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1893 INT in_src1 = -1;
1895 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2164 INT in_src1 = 0;
2166 in_src1 = FLD (in_src1);
2170 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2186 INT in_src1 = 0;
2188 in_src1 = FLD (in_src1);
2192 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2208 INT in_src1 = 0;
2210 in_src1 = FLD (in_src1);
2214 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2230 INT in_src1 = 0;
2232 in_src1 = FLD (in_src1);
2236 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2252 INT in_src1 = 0;
2254 in_src1 = FLD (in_src1);
2258 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2274 INT in_src1 = 0;
2276 in_src1 = FLD (in_src1);
2280 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2296 INT in_src1 = 0;
2298 in_src1 = FLD (in_src1);
2302 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2328 INT in_src1 = 0;
2330 in_src1 = FLD (in_src1);
2334 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2360 INT in_src1 = 0;
2362 in_src1 = FLD (in_src1);
2366 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2392 INT in_src1 = 0;
2394 in_src1 = FLD (in_src1);
2398 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2605 INT in_src1 = -1;
2609 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2625 INT in_src1 = -1;
2627 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2643 INT in_src1 = -1;
2645 in_src1 = FLD (in_src1);
2649 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2665 INT in_src1 = -1;
2667 in_src1 = FLD (in_src1);
2671 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2687 INT in_src1 = -1;
2689 in_src1 = FLD (in_src1);
2693 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2709 INT in_src1 = -1;
2711 in_src1 = FLD (in_src1);
2715 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
Indexes created Sun May 03 00:22:47 UTC 2026