1 /* Simulator model support for m32rxf. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright (C) 1996-2024 Free Software Foundation, Inc. 6 7 This file is part of the GNU simulators. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23 */ 24 25 #define WANT_CPU m32rxf 26 #define WANT_CPU_M32RXF 27 28 #include "sim-main.h" 29 30 /* The profiling data is recorded here, but is accessed via the profiling 31 mechanism. After all, this is information for profiling. */ 32 33 #if WITH_PROFILE_MODEL_P 34 35 /* Model handlers for each insn. */ 36 37 static int 38 model_m32rx_add (SIM_CPU *current_cpu, void *sem_arg) 39 { 40 #define FLD(f) abuf->fields.sfmt_add.f 41 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 42 const IDESC * UNUSED idesc = abuf->idesc; 43 int cycles = 0; 44 { 45 int referenced = 0; 46 int UNUSED insn_referenced = abuf->written; 47 INT in_sr = -1; 48 INT in_dr = -1; 49 INT out_dr = -1; 50 in_sr = FLD (in_sr); 51 in_dr = FLD (in_dr); 52 out_dr = FLD (out_dr); 53 referenced |= 1 << 0; 54 referenced |= 1 << 1; 55 referenced |= 1 << 2; 56 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 57 } 58 return cycles; 59 #undef FLD 60 } 61 62 static int 63 model_m32rx_add3 (SIM_CPU *current_cpu, void *sem_arg) 64 { 65 #define FLD(f) abuf->fields.sfmt_add3.f 66 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 67 const IDESC * UNUSED idesc = abuf->idesc; 68 int cycles = 0; 69 { 70 int referenced = 0; 71 int UNUSED insn_referenced = abuf->written; 72 INT in_sr = -1; 73 INT in_dr = -1; 74 INT out_dr = -1; 75 in_sr = FLD (in_sr); 76 out_dr = FLD (out_dr); 77 referenced |= 1 << 0; 78 referenced |= 1 << 2; 79 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 80 } 81 return cycles; 82 #undef FLD 83 } 84 85 static int 86 model_m32rx_and (SIM_CPU *current_cpu, void *sem_arg) 87 { 88 #define FLD(f) abuf->fields.sfmt_add.f 89 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 90 const IDESC * UNUSED idesc = abuf->idesc; 91 int cycles = 0; 92 { 93 int referenced = 0; 94 int UNUSED insn_referenced = abuf->written; 95 INT in_sr = -1; 96 INT in_dr = -1; 97 INT out_dr = -1; 98 in_sr = FLD (in_sr); 99 in_dr = FLD (in_dr); 100 out_dr = FLD (out_dr); 101 referenced |= 1 << 0; 102 referenced |= 1 << 1; 103 referenced |= 1 << 2; 104 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 105 } 106 return cycles; 107 #undef FLD 108 } 109 110 static int 111 model_m32rx_and3 (SIM_CPU *current_cpu, void *sem_arg) 112 { 113 #define FLD(f) abuf->fields.sfmt_and3.f 114 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 115 const IDESC * UNUSED idesc = abuf->idesc; 116 int cycles = 0; 117 { 118 int referenced = 0; 119 int UNUSED insn_referenced = abuf->written; 120 INT in_sr = -1; 121 INT in_dr = -1; 122 INT out_dr = -1; 123 in_sr = FLD (in_sr); 124 out_dr = FLD (out_dr); 125 referenced |= 1 << 0; 126 referenced |= 1 << 2; 127 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 128 } 129 return cycles; 130 #undef FLD 131 } 132 133 static int 134 model_m32rx_or (SIM_CPU *current_cpu, void *sem_arg) 135 { 136 #define FLD(f) abuf->fields.sfmt_add.f 137 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 138 const IDESC * UNUSED idesc = abuf->idesc; 139 int cycles = 0; 140 { 141 int referenced = 0; 142 int UNUSED insn_referenced = abuf->written; 143 INT in_sr = -1; 144 INT in_dr = -1; 145 INT out_dr = -1; 146 in_sr = FLD (in_sr); 147 in_dr = FLD (in_dr); 148 out_dr = FLD (out_dr); 149 referenced |= 1 << 0; 150 referenced |= 1 << 1; 151 referenced |= 1 << 2; 152 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 153 } 154 return cycles; 155 #undef FLD 156 } 157 158 static int 159 model_m32rx_or3 (SIM_CPU *current_cpu, void *sem_arg) 160 { 161 #define FLD(f) abuf->fields.sfmt_and3.f 162 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 163 const IDESC * UNUSED idesc = abuf->idesc; 164 int cycles = 0; 165 { 166 int referenced = 0; 167 int UNUSED insn_referenced = abuf->written; 168 INT in_sr = -1; 169 INT in_dr = -1; 170 INT out_dr = -1; 171 in_sr = FLD (in_sr); 172 out_dr = FLD (out_dr); 173 referenced |= 1 << 0; 174 referenced |= 1 << 2; 175 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 176 } 177 return cycles; 178 #undef FLD 179 } 180 181 static int 182 model_m32rx_xor (SIM_CPU *current_cpu, void *sem_arg) 183 { 184 #define FLD(f) abuf->fields.sfmt_add.f 185 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 186 const IDESC * UNUSED idesc = abuf->idesc; 187 int cycles = 0; 188 { 189 int referenced = 0; 190 int UNUSED insn_referenced = abuf->written; 191 INT in_sr = -1; 192 INT in_dr = -1; 193 INT out_dr = -1; 194 in_sr = FLD (in_sr); 195 in_dr = FLD (in_dr); 196 out_dr = FLD (out_dr); 197 referenced |= 1 << 0; 198 referenced |= 1 << 1; 199 referenced |= 1 << 2; 200 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 201 } 202 return cycles; 203 #undef FLD 204 } 205 206 static int 207 model_m32rx_xor3 (SIM_CPU *current_cpu, void *sem_arg) 208 { 209 #define FLD(f) abuf->fields.sfmt_and3.f 210 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 211 const IDESC * UNUSED idesc = abuf->idesc; 212 int cycles = 0; 213 { 214 int referenced = 0; 215 int UNUSED insn_referenced = abuf->written; 216 INT in_sr = -1; 217 INT in_dr = -1; 218 INT out_dr = -1; 219 in_sr = FLD (in_sr); 220 out_dr = FLD (out_dr); 221 referenced |= 1 << 0; 222 referenced |= 1 << 2; 223 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 224 } 225 return cycles; 226 #undef FLD 227 } 228 229 static int 230 model_m32rx_addi (SIM_CPU *current_cpu, void *sem_arg) 231 { 232 #define FLD(f) abuf->fields.sfmt_addi.f 233 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 234 const IDESC * UNUSED idesc = abuf->idesc; 235 int cycles = 0; 236 { 237 int referenced = 0; 238 int UNUSED insn_referenced = abuf->written; 239 INT in_sr = -1; 240 INT in_dr = -1; 241 INT out_dr = -1; 242 in_dr = FLD (in_dr); 243 out_dr = FLD (out_dr); 244 referenced |= 1 << 1; 245 referenced |= 1 << 2; 246 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 247 } 248 return cycles; 249 #undef FLD 250 } 251 252 static int 253 model_m32rx_addv (SIM_CPU *current_cpu, void *sem_arg) 254 { 255 #define FLD(f) abuf->fields.sfmt_add.f 256 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 257 const IDESC * UNUSED idesc = abuf->idesc; 258 int cycles = 0; 259 { 260 int referenced = 0; 261 int UNUSED insn_referenced = abuf->written; 262 INT in_sr = -1; 263 INT in_dr = -1; 264 INT out_dr = -1; 265 in_sr = FLD (in_sr); 266 in_dr = FLD (in_dr); 267 out_dr = FLD (out_dr); 268 referenced |= 1 << 0; 269 referenced |= 1 << 1; 270 referenced |= 1 << 2; 271 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 272 } 273 return cycles; 274 #undef FLD 275 } 276 277 static int 278 model_m32rx_addv3 (SIM_CPU *current_cpu, void *sem_arg) 279 { 280 #define FLD(f) abuf->fields.sfmt_add3.f 281 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 282 const IDESC * UNUSED idesc = abuf->idesc; 283 int cycles = 0; 284 { 285 int referenced = 0; 286 int UNUSED insn_referenced = abuf->written; 287 INT in_sr = -1; 288 INT in_dr = -1; 289 INT out_dr = -1; 290 in_sr = FLD (in_sr); 291 out_dr = FLD (out_dr); 292 referenced |= 1 << 0; 293 referenced |= 1 << 2; 294 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 295 } 296 return cycles; 297 #undef FLD 298 } 299 300 static int 301 model_m32rx_addx (SIM_CPU *current_cpu, void *sem_arg) 302 { 303 #define FLD(f) abuf->fields.sfmt_add.f 304 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 305 const IDESC * UNUSED idesc = abuf->idesc; 306 int cycles = 0; 307 { 308 int referenced = 0; 309 int UNUSED insn_referenced = abuf->written; 310 INT in_sr = -1; 311 INT in_dr = -1; 312 INT out_dr = -1; 313 in_sr = FLD (in_sr); 314 in_dr = FLD (in_dr); 315 out_dr = FLD (out_dr); 316 referenced |= 1 << 0; 317 referenced |= 1 << 1; 318 referenced |= 1 << 2; 319 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 320 } 321 return cycles; 322 #undef FLD 323 } 324 325 static int 326 model_m32rx_bc8 (SIM_CPU *current_cpu, void *sem_arg) 327 { 328 #define FLD(f) abuf->fields.sfmt_bl8.f 329 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 330 const IDESC * UNUSED idesc = abuf->idesc; 331 int cycles = 0; 332 { 333 int referenced = 0; 334 int UNUSED insn_referenced = abuf->written; 335 INT in_sr = -1; 336 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 337 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 338 } 339 return cycles; 340 #undef FLD 341 } 342 343 static int 344 model_m32rx_bc24 (SIM_CPU *current_cpu, void *sem_arg) 345 { 346 #define FLD(f) abuf->fields.sfmt_bl24.f 347 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 348 const IDESC * UNUSED idesc = abuf->idesc; 349 int cycles = 0; 350 { 351 int referenced = 0; 352 int UNUSED insn_referenced = abuf->written; 353 INT in_sr = -1; 354 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 355 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 356 } 357 return cycles; 358 #undef FLD 359 } 360 361 static int 362 model_m32rx_beq (SIM_CPU *current_cpu, void *sem_arg) 363 { 364 #define FLD(f) abuf->fields.sfmt_beq.f 365 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 366 const IDESC * UNUSED idesc = abuf->idesc; 367 int cycles = 0; 368 { 369 int referenced = 0; 370 int UNUSED insn_referenced = abuf->written; 371 INT in_sr = -1; 372 if (insn_referenced & (1 << 3)) referenced |= 1 << 1; 373 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 374 } 375 { 376 int referenced = 0; 377 int UNUSED insn_referenced = abuf->written; 378 INT in_src1 = -1; 379 INT in_src2 = -1; 380 in_src1 = FLD (in_src1); 381 in_src2 = FLD (in_src2); 382 referenced |= 1 << 0; 383 referenced |= 1 << 1; 384 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); 385 } 386 return cycles; 387 #undef FLD 388 } 389 390 static int 391 model_m32rx_beqz (SIM_CPU *current_cpu, void *sem_arg) 392 { 393 #define FLD(f) abuf->fields.sfmt_beq.f 394 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 395 const IDESC * UNUSED idesc = abuf->idesc; 396 int cycles = 0; 397 { 398 int referenced = 0; 399 int UNUSED insn_referenced = abuf->written; 400 INT in_sr = -1; 401 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 402 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 403 } 404 { 405 int referenced = 0; 406 int UNUSED insn_referenced = abuf->written; 407 INT in_src1 = -1; 408 INT in_src2 = -1; 409 in_src2 = FLD (in_src2); 410 referenced |= 1 << 1; 411 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); 412 } 413 return cycles; 414 #undef FLD 415 } 416 417 static int 418 model_m32rx_bgez (SIM_CPU *current_cpu, void *sem_arg) 419 { 420 #define FLD(f) abuf->fields.sfmt_beq.f 421 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 422 const IDESC * UNUSED idesc = abuf->idesc; 423 int cycles = 0; 424 { 425 int referenced = 0; 426 int UNUSED insn_referenced = abuf->written; 427 INT in_sr = -1; 428 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 429 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 430 } 431 { 432 int referenced = 0; 433 int UNUSED insn_referenced = abuf->written; 434 INT in_src1 = -1; 435 INT in_src2 = -1; 436 in_src2 = FLD (in_src2); 437 referenced |= 1 << 1; 438 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); 439 } 440 return cycles; 441 #undef FLD 442 } 443 444 static int 445 model_m32rx_bgtz (SIM_CPU *current_cpu, void *sem_arg) 446 { 447 #define FLD(f) abuf->fields.sfmt_beq.f 448 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 449 const IDESC * UNUSED idesc = abuf->idesc; 450 int cycles = 0; 451 { 452 int referenced = 0; 453 int UNUSED insn_referenced = abuf->written; 454 INT in_sr = -1; 455 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 456 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 457 } 458 { 459 int referenced = 0; 460 int UNUSED insn_referenced = abuf->written; 461 INT in_src1 = -1; 462 INT in_src2 = -1; 463 in_src2 = FLD (in_src2); 464 referenced |= 1 << 1; 465 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); 466 } 467 return cycles; 468 #undef FLD 469 } 470 471 static int 472 model_m32rx_blez (SIM_CPU *current_cpu, void *sem_arg) 473 { 474 #define FLD(f) abuf->fields.sfmt_beq.f 475 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 476 const IDESC * UNUSED idesc = abuf->idesc; 477 int cycles = 0; 478 { 479 int referenced = 0; 480 int UNUSED insn_referenced = abuf->written; 481 INT in_sr = -1; 482 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 483 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 484 } 485 { 486 int referenced = 0; 487 int UNUSED insn_referenced = abuf->written; 488 INT in_src1 = -1; 489 INT in_src2 = -1; 490 in_src2 = FLD (in_src2); 491 referenced |= 1 << 1; 492 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); 493 } 494 return cycles; 495 #undef FLD 496 } 497 498 static int 499 model_m32rx_bltz (SIM_CPU *current_cpu, void *sem_arg) 500 { 501 #define FLD(f) abuf->fields.sfmt_beq.f 502 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 503 const IDESC * UNUSED idesc = abuf->idesc; 504 int cycles = 0; 505 { 506 int referenced = 0; 507 int UNUSED insn_referenced = abuf->written; 508 INT in_sr = -1; 509 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 510 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 511 } 512 { 513 int referenced = 0; 514 int UNUSED insn_referenced = abuf->written; 515 INT in_src1 = -1; 516 INT in_src2 = -1; 517 in_src2 = FLD (in_src2); 518 referenced |= 1 << 1; 519 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); 520 } 521 return cycles; 522 #undef FLD 523 } 524 525 static int 526 model_m32rx_bnez (SIM_CPU *current_cpu, void *sem_arg) 527 { 528 #define FLD(f) abuf->fields.sfmt_beq.f 529 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 530 const IDESC * UNUSED idesc = abuf->idesc; 531 int cycles = 0; 532 { 533 int referenced = 0; 534 int UNUSED insn_referenced = abuf->written; 535 INT in_sr = -1; 536 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 537 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 538 } 539 { 540 int referenced = 0; 541 int UNUSED insn_referenced = abuf->written; 542 INT in_src1 = -1; 543 INT in_src2 = -1; 544 in_src2 = FLD (in_src2); 545 referenced |= 1 << 1; 546 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); 547 } 548 return cycles; 549 #undef FLD 550 } 551 552 static int 553 model_m32rx_bl8 (SIM_CPU *current_cpu, void *sem_arg) 554 { 555 #define FLD(f) abuf->fields.sfmt_bl8.f 556 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 557 const IDESC * UNUSED idesc = abuf->idesc; 558 int cycles = 0; 559 { 560 int referenced = 0; 561 int UNUSED insn_referenced = abuf->written; 562 INT in_sr = -1; 563 referenced |= 1 << 1; 564 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 565 } 566 return cycles; 567 #undef FLD 568 } 569 570 static int 571 model_m32rx_bl24 (SIM_CPU *current_cpu, void *sem_arg) 572 { 573 #define FLD(f) abuf->fields.sfmt_bl24.f 574 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 575 const IDESC * UNUSED idesc = abuf->idesc; 576 int cycles = 0; 577 { 578 int referenced = 0; 579 int UNUSED insn_referenced = abuf->written; 580 INT in_sr = -1; 581 referenced |= 1 << 1; 582 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 583 } 584 return cycles; 585 #undef FLD 586 } 587 588 static int 589 model_m32rx_bcl8 (SIM_CPU *current_cpu, void *sem_arg) 590 { 591 #define FLD(f) abuf->fields.sfmt_bl8.f 592 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 593 const IDESC * UNUSED idesc = abuf->idesc; 594 int cycles = 0; 595 { 596 int referenced = 0; 597 int UNUSED insn_referenced = abuf->written; 598 INT in_sr = -1; 599 if (insn_referenced & (1 << 4)) referenced |= 1 << 1; 600 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 601 } 602 return cycles; 603 #undef FLD 604 } 605 606 static int 607 model_m32rx_bcl24 (SIM_CPU *current_cpu, void *sem_arg) 608 { 609 #define FLD(f) abuf->fields.sfmt_bl24.f 610 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 611 const IDESC * UNUSED idesc = abuf->idesc; 612 int cycles = 0; 613 { 614 int referenced = 0; 615 int UNUSED insn_referenced = abuf->written; 616 INT in_sr = -1; 617 if (insn_referenced & (1 << 4)) referenced |= 1 << 1; 618 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 619 } 620 return cycles; 621 #undef FLD 622 } 623 624 static int 625 model_m32rx_bnc8 (SIM_CPU *current_cpu, void *sem_arg) 626 { 627 #define FLD(f) abuf->fields.sfmt_bl8.f 628 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 629 const IDESC * UNUSED idesc = abuf->idesc; 630 int cycles = 0; 631 { 632 int referenced = 0; 633 int UNUSED insn_referenced = abuf->written; 634 INT in_sr = -1; 635 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 636 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 637 } 638 return cycles; 639 #undef FLD 640 } 641 642 static int 643 model_m32rx_bnc24 (SIM_CPU *current_cpu, void *sem_arg) 644 { 645 #define FLD(f) abuf->fields.sfmt_bl24.f 646 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 647 const IDESC * UNUSED idesc = abuf->idesc; 648 int cycles = 0; 649 { 650 int referenced = 0; 651 int UNUSED insn_referenced = abuf->written; 652 INT in_sr = -1; 653 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 654 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 655 } 656 return cycles; 657 #undef FLD 658 } 659 660 static int 661 model_m32rx_bne (SIM_CPU *current_cpu, void *sem_arg) 662 { 663 #define FLD(f) abuf->fields.sfmt_beq.f 664 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 665 const IDESC * UNUSED idesc = abuf->idesc; 666 int cycles = 0; 667 { 668 int referenced = 0; 669 int UNUSED insn_referenced = abuf->written; 670 INT in_sr = -1; 671 if (insn_referenced & (1 << 3)) referenced |= 1 << 1; 672 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 673 } 674 { 675 int referenced = 0; 676 int UNUSED insn_referenced = abuf->written; 677 INT in_src1 = -1; 678 INT in_src2 = -1; 679 in_src1 = FLD (in_src1); 680 in_src2 = FLD (in_src2); 681 referenced |= 1 << 0; 682 referenced |= 1 << 1; 683 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); 684 } 685 return cycles; 686 #undef FLD 687 } 688 689 static int 690 model_m32rx_bra8 (SIM_CPU *current_cpu, void *sem_arg) 691 { 692 #define FLD(f) abuf->fields.sfmt_bl8.f 693 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 694 const IDESC * UNUSED idesc = abuf->idesc; 695 int cycles = 0; 696 { 697 int referenced = 0; 698 int UNUSED insn_referenced = abuf->written; 699 INT in_sr = -1; 700 referenced |= 1 << 1; 701 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 702 } 703 return cycles; 704 #undef FLD 705 } 706 707 static int 708 model_m32rx_bra24 (SIM_CPU *current_cpu, void *sem_arg) 709 { 710 #define FLD(f) abuf->fields.sfmt_bl24.f 711 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 712 const IDESC * UNUSED idesc = abuf->idesc; 713 int cycles = 0; 714 { 715 int referenced = 0; 716 int UNUSED insn_referenced = abuf->written; 717 INT in_sr = -1; 718 referenced |= 1 << 1; 719 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 720 } 721 return cycles; 722 #undef FLD 723 } 724 725 static int 726 model_m32rx_bncl8 (SIM_CPU *current_cpu, void *sem_arg) 727 { 728 #define FLD(f) abuf->fields.sfmt_bl8.f 729 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 730 const IDESC * UNUSED idesc = abuf->idesc; 731 int cycles = 0; 732 { 733 int referenced = 0; 734 int UNUSED insn_referenced = abuf->written; 735 INT in_sr = -1; 736 if (insn_referenced & (1 << 4)) referenced |= 1 << 1; 737 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 738 } 739 return cycles; 740 #undef FLD 741 } 742 743 static int 744 model_m32rx_bncl24 (SIM_CPU *current_cpu, void *sem_arg) 745 { 746 #define FLD(f) abuf->fields.sfmt_bl24.f 747 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 748 const IDESC * UNUSED idesc = abuf->idesc; 749 int cycles = 0; 750 { 751 int referenced = 0; 752 int UNUSED insn_referenced = abuf->written; 753 INT in_sr = -1; 754 if (insn_referenced & (1 << 4)) referenced |= 1 << 1; 755 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 756 } 757 return cycles; 758 #undef FLD 759 } 760 761 static int 762 model_m32rx_cmp (SIM_CPU *current_cpu, void *sem_arg) 763 { 764 #define FLD(f) abuf->fields.sfmt_st_plus.f 765 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 766 const IDESC * UNUSED idesc = abuf->idesc; 767 int cycles = 0; 768 { 769 int referenced = 0; 770 int UNUSED insn_referenced = abuf->written; 771 INT in_src1 = -1; 772 INT in_src2 = -1; 773 in_src1 = FLD (in_src1); 774 in_src2 = FLD (in_src2); 775 referenced |= 1 << 0; 776 referenced |= 1 << 1; 777 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); 778 } 779 return cycles; 780 #undef FLD 781 } 782 783 static int 784 model_m32rx_cmpi (SIM_CPU *current_cpu, void *sem_arg) 785 { 786 #define FLD(f) abuf->fields.sfmt_st_d.f 787 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 788 const IDESC * UNUSED idesc = abuf->idesc; 789 int cycles = 0; 790 { 791 int referenced = 0; 792 int UNUSED insn_referenced = abuf->written; 793 INT in_src1 = -1; 794 INT in_src2 = -1; 795 in_src2 = FLD (in_src2); 796 referenced |= 1 << 1; 797 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); 798 } 799 return cycles; 800 #undef FLD 801 } 802 803 static int 804 model_m32rx_cmpu (SIM_CPU *current_cpu, void *sem_arg) 805 { 806 #define FLD(f) abuf->fields.sfmt_st_plus.f 807 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 808 const IDESC * UNUSED idesc = abuf->idesc; 809 int cycles = 0; 810 { 811 int referenced = 0; 812 int UNUSED insn_referenced = abuf->written; 813 INT in_src1 = -1; 814 INT in_src2 = -1; 815 in_src1 = FLD (in_src1); 816 in_src2 = FLD (in_src2); 817 referenced |= 1 << 0; 818 referenced |= 1 << 1; 819 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); 820 } 821 return cycles; 822 #undef FLD 823 } 824 825 static int 826 model_m32rx_cmpui (SIM_CPU *current_cpu, void *sem_arg) 827 { 828 #define FLD(f) abuf->fields.sfmt_st_d.f 829 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 830 const IDESC * UNUSED idesc = abuf->idesc; 831 int cycles = 0; 832 { 833 int referenced = 0; 834 int UNUSED insn_referenced = abuf->written; 835 INT in_src1 = -1; 836 INT in_src2 = -1; 837 in_src2 = FLD (in_src2); 838 referenced |= 1 << 1; 839 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); 840 } 841 return cycles; 842 #undef FLD 843 } 844 845 static int 846 model_m32rx_cmpeq (SIM_CPU *current_cpu, void *sem_arg) 847 { 848 #define FLD(f) abuf->fields.sfmt_st_plus.f 849 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 850 const IDESC * UNUSED idesc = abuf->idesc; 851 int cycles = 0; 852 { 853 int referenced = 0; 854 int UNUSED insn_referenced = abuf->written; 855 INT in_src1 = -1; 856 INT in_src2 = -1; 857 in_src1 = FLD (in_src1); 858 in_src2 = FLD (in_src2); 859 referenced |= 1 << 0; 860 referenced |= 1 << 1; 861 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); 862 } 863 return cycles; 864 #undef FLD 865 } 866 867 static int 868 model_m32rx_cmpz (SIM_CPU *current_cpu, void *sem_arg) 869 { 870 #define FLD(f) abuf->fields.sfmt_st_plus.f 871 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 872 const IDESC * UNUSED idesc = abuf->idesc; 873 int cycles = 0; 874 { 875 int referenced = 0; 876 int UNUSED insn_referenced = abuf->written; 877 INT in_src1 = -1; 878 INT in_src2 = -1; 879 in_src2 = FLD (in_src2); 880 referenced |= 1 << 1; 881 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); 882 } 883 return cycles; 884 #undef FLD 885 } 886 887 static int 888 model_m32rx_div (SIM_CPU *current_cpu, void *sem_arg) 889 { 890 #define FLD(f) abuf->fields.sfmt_add.f 891 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 892 const IDESC * UNUSED idesc = abuf->idesc; 893 int cycles = 0; 894 { 895 int referenced = 0; 896 int UNUSED insn_referenced = abuf->written; 897 INT in_sr = -1; 898 INT in_dr = -1; 899 INT out_dr = -1; 900 in_sr = FLD (in_sr); 901 in_dr = FLD (in_dr); 902 out_dr = FLD (out_dr); 903 referenced |= 1 << 0; 904 if (insn_referenced & (1 << 0)) referenced |= 1 << 1; 905 if (insn_referenced & (1 << 2)) referenced |= 1 << 2; 906 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 907 } 908 return cycles; 909 #undef FLD 910 } 911 912 static int 913 model_m32rx_divu (SIM_CPU *current_cpu, void *sem_arg) 914 { 915 #define FLD(f) abuf->fields.sfmt_add.f 916 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 917 const IDESC * UNUSED idesc = abuf->idesc; 918 int cycles = 0; 919 { 920 int referenced = 0; 921 int UNUSED insn_referenced = abuf->written; 922 INT in_sr = -1; 923 INT in_dr = -1; 924 INT out_dr = -1; 925 in_sr = FLD (in_sr); 926 in_dr = FLD (in_dr); 927 out_dr = FLD (out_dr); 928 referenced |= 1 << 0; 929 if (insn_referenced & (1 << 0)) referenced |= 1 << 1; 930 if (insn_referenced & (1 << 2)) referenced |= 1 << 2; 931 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 932 } 933 return cycles; 934 #undef FLD 935 } 936 937 static int 938 model_m32rx_rem (SIM_CPU *current_cpu, void *sem_arg) 939 { 940 #define FLD(f) abuf->fields.sfmt_add.f 941 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 942 const IDESC * UNUSED idesc = abuf->idesc; 943 int cycles = 0; 944 { 945 int referenced = 0; 946 int UNUSED insn_referenced = abuf->written; 947 INT in_sr = -1; 948 INT in_dr = -1; 949 INT out_dr = -1; 950 in_sr = FLD (in_sr); 951 in_dr = FLD (in_dr); 952 out_dr = FLD (out_dr); 953 referenced |= 1 << 0; 954 if (insn_referenced & (1 << 0)) referenced |= 1 << 1; 955 if (insn_referenced & (1 << 2)) referenced |= 1 << 2; 956 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 957 } 958 return cycles; 959 #undef FLD 960 } 961 962 static int 963 model_m32rx_remu (SIM_CPU *current_cpu, void *sem_arg) 964 { 965 #define FLD(f) abuf->fields.sfmt_add.f 966 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 967 const IDESC * UNUSED idesc = abuf->idesc; 968 int cycles = 0; 969 { 970 int referenced = 0; 971 int UNUSED insn_referenced = abuf->written; 972 INT in_sr = -1; 973 INT in_dr = -1; 974 INT out_dr = -1; 975 in_sr = FLD (in_sr); 976 in_dr = FLD (in_dr); 977 out_dr = FLD (out_dr); 978 referenced |= 1 << 0; 979 if (insn_referenced & (1 << 0)) referenced |= 1 << 1; 980 if (insn_referenced & (1 << 2)) referenced |= 1 << 2; 981 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 982 } 983 return cycles; 984 #undef FLD 985 } 986 987 static int 988 model_m32rx_divh (SIM_CPU *current_cpu, void *sem_arg) 989 { 990 #define FLD(f) abuf->fields.sfmt_add.f 991 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 992 const IDESC * UNUSED idesc = abuf->idesc; 993 int cycles = 0; 994 { 995 int referenced = 0; 996 int UNUSED insn_referenced = abuf->written; 997 INT in_sr = -1; 998 INT in_dr = -1; 999 INT out_dr = -1; 1000 in_sr = FLD (in_sr); 1001 in_dr = FLD (in_dr); 1002 out_dr = FLD (out_dr); 1003 referenced |= 1 << 0; 1004 if (insn_referenced & (1 << 0)) referenced |= 1 << 1; 1005 if (insn_referenced & (1 << 2)) referenced |= 1 << 2; 1006 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1007 } 1008 return cycles; 1009 #undef FLD 1010 } 1011 1012 static int 1013 model_m32rx_jc (SIM_CPU *current_cpu, void *sem_arg) 1014 { 1015 #define FLD(f) abuf->fields.sfmt_jl.f 1016 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1017 const IDESC * UNUSED idesc = abuf->idesc; 1018 int cycles = 0; 1019 { 1020 int referenced = 0; 1021 int UNUSED insn_referenced = abuf->written; 1022 INT in_sr = -1; 1023 in_sr = FLD (in_sr); 1024 if (insn_referenced & (1 << 1)) referenced |= 1 << 0; 1025 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 1026 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 1027 } 1028 return cycles; 1029 #undef FLD 1030 } 1031 1032 static int 1033 model_m32rx_jnc (SIM_CPU *current_cpu, void *sem_arg) 1034 { 1035 #define FLD(f) abuf->fields.sfmt_jl.f 1036 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1037 const IDESC * UNUSED idesc = abuf->idesc; 1038 int cycles = 0; 1039 { 1040 int referenced = 0; 1041 int UNUSED insn_referenced = abuf->written; 1042 INT in_sr = -1; 1043 in_sr = FLD (in_sr); 1044 if (insn_referenced & (1 << 1)) referenced |= 1 << 0; 1045 if (insn_referenced & (1 << 2)) referenced |= 1 << 1; 1046 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 1047 } 1048 return cycles; 1049 #undef FLD 1050 } 1051 1052 static int 1053 model_m32rx_jl (SIM_CPU *current_cpu, void *sem_arg) 1054 { 1055 #define FLD(f) abuf->fields.sfmt_jl.f 1056 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1057 const IDESC * UNUSED idesc = abuf->idesc; 1058 int cycles = 0; 1059 { 1060 int referenced = 0; 1061 int UNUSED insn_referenced = abuf->written; 1062 INT in_sr = -1; 1063 in_sr = FLD (in_sr); 1064 referenced |= 1 << 0; 1065 referenced |= 1 << 1; 1066 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 1067 } 1068 return cycles; 1069 #undef FLD 1070 } 1071 1072 static int 1073 model_m32rx_jmp (SIM_CPU *current_cpu, void *sem_arg) 1074 { 1075 #define FLD(f) abuf->fields.sfmt_jl.f 1076 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1077 const IDESC * UNUSED idesc = abuf->idesc; 1078 int cycles = 0; 1079 { 1080 int referenced = 0; 1081 int UNUSED insn_referenced = abuf->written; 1082 INT in_sr = -1; 1083 in_sr = FLD (in_sr); 1084 referenced |= 1 << 0; 1085 referenced |= 1 << 1; 1086 cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); 1087 } 1088 return cycles; 1089 #undef FLD 1090 } 1091 1092 static int 1093 model_m32rx_ld (SIM_CPU *current_cpu, void *sem_arg) 1094 { 1095 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1096 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1097 const IDESC * UNUSED idesc = abuf->idesc; 1098 int cycles = 0; 1099 { 1100 int referenced = 0; 1101 int UNUSED insn_referenced = abuf->written; 1102 INT in_sr = 0; 1103 INT out_dr = 0; 1104 in_sr = FLD (in_sr); 1105 out_dr = FLD (out_dr); 1106 referenced |= 1 << 0; 1107 referenced |= 1 << 1; 1108 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1109 } 1110 return cycles; 1111 #undef FLD 1112 } 1113 1114 static int 1115 model_m32rx_ld_d (SIM_CPU *current_cpu, void *sem_arg) 1116 { 1117 #define FLD(f) abuf->fields.sfmt_add3.f 1118 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1119 const IDESC * UNUSED idesc = abuf->idesc; 1120 int cycles = 0; 1121 { 1122 int referenced = 0; 1123 int UNUSED insn_referenced = abuf->written; 1124 INT in_sr = 0; 1125 INT out_dr = 0; 1126 in_sr = FLD (in_sr); 1127 out_dr = FLD (out_dr); 1128 referenced |= 1 << 0; 1129 referenced |= 1 << 1; 1130 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1131 } 1132 return cycles; 1133 #undef FLD 1134 } 1135 1136 static int 1137 model_m32rx_ldb (SIM_CPU *current_cpu, void *sem_arg) 1138 { 1139 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1140 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1141 const IDESC * UNUSED idesc = abuf->idesc; 1142 int cycles = 0; 1143 { 1144 int referenced = 0; 1145 int UNUSED insn_referenced = abuf->written; 1146 INT in_sr = 0; 1147 INT out_dr = 0; 1148 in_sr = FLD (in_sr); 1149 out_dr = FLD (out_dr); 1150 referenced |= 1 << 0; 1151 referenced |= 1 << 1; 1152 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1153 } 1154 return cycles; 1155 #undef FLD 1156 } 1157 1158 static int 1159 model_m32rx_ldb_d (SIM_CPU *current_cpu, void *sem_arg) 1160 { 1161 #define FLD(f) abuf->fields.sfmt_add3.f 1162 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1163 const IDESC * UNUSED idesc = abuf->idesc; 1164 int cycles = 0; 1165 { 1166 int referenced = 0; 1167 int UNUSED insn_referenced = abuf->written; 1168 INT in_sr = 0; 1169 INT out_dr = 0; 1170 in_sr = FLD (in_sr); 1171 out_dr = FLD (out_dr); 1172 referenced |= 1 << 0; 1173 referenced |= 1 << 1; 1174 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1175 } 1176 return cycles; 1177 #undef FLD 1178 } 1179 1180 static int 1181 model_m32rx_ldh (SIM_CPU *current_cpu, void *sem_arg) 1182 { 1183 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1184 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1185 const IDESC * UNUSED idesc = abuf->idesc; 1186 int cycles = 0; 1187 { 1188 int referenced = 0; 1189 int UNUSED insn_referenced = abuf->written; 1190 INT in_sr = 0; 1191 INT out_dr = 0; 1192 in_sr = FLD (in_sr); 1193 out_dr = FLD (out_dr); 1194 referenced |= 1 << 0; 1195 referenced |= 1 << 1; 1196 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1197 } 1198 return cycles; 1199 #undef FLD 1200 } 1201 1202 static int 1203 model_m32rx_ldh_d (SIM_CPU *current_cpu, void *sem_arg) 1204 { 1205 #define FLD(f) abuf->fields.sfmt_add3.f 1206 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1207 const IDESC * UNUSED idesc = abuf->idesc; 1208 int cycles = 0; 1209 { 1210 int referenced = 0; 1211 int UNUSED insn_referenced = abuf->written; 1212 INT in_sr = 0; 1213 INT out_dr = 0; 1214 in_sr = FLD (in_sr); 1215 out_dr = FLD (out_dr); 1216 referenced |= 1 << 0; 1217 referenced |= 1 << 1; 1218 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1219 } 1220 return cycles; 1221 #undef FLD 1222 } 1223 1224 static int 1225 model_m32rx_ldub (SIM_CPU *current_cpu, void *sem_arg) 1226 { 1227 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1228 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1229 const IDESC * UNUSED idesc = abuf->idesc; 1230 int cycles = 0; 1231 { 1232 int referenced = 0; 1233 int UNUSED insn_referenced = abuf->written; 1234 INT in_sr = 0; 1235 INT out_dr = 0; 1236 in_sr = FLD (in_sr); 1237 out_dr = FLD (out_dr); 1238 referenced |= 1 << 0; 1239 referenced |= 1 << 1; 1240 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1241 } 1242 return cycles; 1243 #undef FLD 1244 } 1245 1246 static int 1247 model_m32rx_ldub_d (SIM_CPU *current_cpu, void *sem_arg) 1248 { 1249 #define FLD(f) abuf->fields.sfmt_add3.f 1250 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1251 const IDESC * UNUSED idesc = abuf->idesc; 1252 int cycles = 0; 1253 { 1254 int referenced = 0; 1255 int UNUSED insn_referenced = abuf->written; 1256 INT in_sr = 0; 1257 INT out_dr = 0; 1258 in_sr = FLD (in_sr); 1259 out_dr = FLD (out_dr); 1260 referenced |= 1 << 0; 1261 referenced |= 1 << 1; 1262 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1263 } 1264 return cycles; 1265 #undef FLD 1266 } 1267 1268 static int 1269 model_m32rx_lduh (SIM_CPU *current_cpu, void *sem_arg) 1270 { 1271 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1272 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1273 const IDESC * UNUSED idesc = abuf->idesc; 1274 int cycles = 0; 1275 { 1276 int referenced = 0; 1277 int UNUSED insn_referenced = abuf->written; 1278 INT in_sr = 0; 1279 INT out_dr = 0; 1280 in_sr = FLD (in_sr); 1281 out_dr = FLD (out_dr); 1282 referenced |= 1 << 0; 1283 referenced |= 1 << 1; 1284 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1285 } 1286 return cycles; 1287 #undef FLD 1288 } 1289 1290 static int 1291 model_m32rx_lduh_d (SIM_CPU *current_cpu, void *sem_arg) 1292 { 1293 #define FLD(f) abuf->fields.sfmt_add3.f 1294 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1295 const IDESC * UNUSED idesc = abuf->idesc; 1296 int cycles = 0; 1297 { 1298 int referenced = 0; 1299 int UNUSED insn_referenced = abuf->written; 1300 INT in_sr = 0; 1301 INT out_dr = 0; 1302 in_sr = FLD (in_sr); 1303 out_dr = FLD (out_dr); 1304 referenced |= 1 << 0; 1305 referenced |= 1 << 1; 1306 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1307 } 1308 return cycles; 1309 #undef FLD 1310 } 1311 1312 static int 1313 model_m32rx_ld_plus (SIM_CPU *current_cpu, void *sem_arg) 1314 { 1315 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1316 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1317 const IDESC * UNUSED idesc = abuf->idesc; 1318 int cycles = 0; 1319 { 1320 int referenced = 0; 1321 int UNUSED insn_referenced = abuf->written; 1322 INT in_sr = 0; 1323 INT out_dr = 0; 1324 in_sr = FLD (in_sr); 1325 out_dr = FLD (out_dr); 1326 referenced |= 1 << 0; 1327 referenced |= 1 << 1; 1328 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1329 } 1330 { 1331 int referenced = 0; 1332 int UNUSED insn_referenced = abuf->written; 1333 INT in_sr = -1; 1334 INT in_dr = -1; 1335 INT out_dr = -1; 1336 in_dr = FLD (in_sr); 1337 out_dr = FLD (out_sr); 1338 referenced |= 1 << 0; 1339 referenced |= 1 << 2; 1340 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); 1341 } 1342 return cycles; 1343 #undef FLD 1344 } 1345 1346 static int 1347 model_m32rx_ld24 (SIM_CPU *current_cpu, void *sem_arg) 1348 { 1349 #define FLD(f) abuf->fields.sfmt_ld24.f 1350 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1351 const IDESC * UNUSED idesc = abuf->idesc; 1352 int cycles = 0; 1353 { 1354 int referenced = 0; 1355 int UNUSED insn_referenced = abuf->written; 1356 INT in_sr = -1; 1357 INT in_dr = -1; 1358 INT out_dr = -1; 1359 out_dr = FLD (out_dr); 1360 referenced |= 1 << 2; 1361 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1362 } 1363 return cycles; 1364 #undef FLD 1365 } 1366 1367 static int 1368 model_m32rx_ldi8 (SIM_CPU *current_cpu, void *sem_arg) 1369 { 1370 #define FLD(f) abuf->fields.sfmt_addi.f 1371 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1372 const IDESC * UNUSED idesc = abuf->idesc; 1373 int cycles = 0; 1374 { 1375 int referenced = 0; 1376 int UNUSED insn_referenced = abuf->written; 1377 INT in_sr = -1; 1378 INT in_dr = -1; 1379 INT out_dr = -1; 1380 out_dr = FLD (out_dr); 1381 referenced |= 1 << 2; 1382 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1383 } 1384 return cycles; 1385 #undef FLD 1386 } 1387 1388 static int 1389 model_m32rx_ldi16 (SIM_CPU *current_cpu, void *sem_arg) 1390 { 1391 #define FLD(f) abuf->fields.sfmt_add3.f 1392 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1393 const IDESC * UNUSED idesc = abuf->idesc; 1394 int cycles = 0; 1395 { 1396 int referenced = 0; 1397 int UNUSED insn_referenced = abuf->written; 1398 INT in_sr = -1; 1399 INT in_dr = -1; 1400 INT out_dr = -1; 1401 out_dr = FLD (out_dr); 1402 referenced |= 1 << 2; 1403 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1404 } 1405 return cycles; 1406 #undef FLD 1407 } 1408 1409 static int 1410 model_m32rx_lock (SIM_CPU *current_cpu, void *sem_arg) 1411 { 1412 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1413 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1414 const IDESC * UNUSED idesc = abuf->idesc; 1415 int cycles = 0; 1416 { 1417 int referenced = 0; 1418 int UNUSED insn_referenced = abuf->written; 1419 INT in_sr = 0; 1420 INT out_dr = 0; 1421 in_sr = FLD (in_sr); 1422 out_dr = FLD (out_dr); 1423 referenced |= 1 << 0; 1424 referenced |= 1 << 1; 1425 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 1426 } 1427 return cycles; 1428 #undef FLD 1429 } 1430 1431 static int 1432 model_m32rx_machi_a (SIM_CPU *current_cpu, void *sem_arg) 1433 { 1434 #define FLD(f) abuf->fields.sfmt_machi_a.f 1435 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1436 const IDESC * UNUSED idesc = abuf->idesc; 1437 int cycles = 0; 1438 { 1439 int referenced = 0; 1440 int UNUSED insn_referenced = abuf->written; 1441 INT in_src1 = -1; 1442 INT in_src2 = -1; 1443 in_src1 = FLD (in_src1); 1444 in_src2 = FLD (in_src2); 1445 referenced |= 1 << 0; 1446 referenced |= 1 << 1; 1447 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1448 } 1449 return cycles; 1450 #undef FLD 1451 } 1452 1453 static int 1454 model_m32rx_maclo_a (SIM_CPU *current_cpu, void *sem_arg) 1455 { 1456 #define FLD(f) abuf->fields.sfmt_machi_a.f 1457 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1458 const IDESC * UNUSED idesc = abuf->idesc; 1459 int cycles = 0; 1460 { 1461 int referenced = 0; 1462 int UNUSED insn_referenced = abuf->written; 1463 INT in_src1 = -1; 1464 INT in_src2 = -1; 1465 in_src1 = FLD (in_src1); 1466 in_src2 = FLD (in_src2); 1467 referenced |= 1 << 0; 1468 referenced |= 1 << 1; 1469 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1470 } 1471 return cycles; 1472 #undef FLD 1473 } 1474 1475 static int 1476 model_m32rx_macwhi_a (SIM_CPU *current_cpu, void *sem_arg) 1477 { 1478 #define FLD(f) abuf->fields.sfmt_machi_a.f 1479 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1480 const IDESC * UNUSED idesc = abuf->idesc; 1481 int cycles = 0; 1482 { 1483 int referenced = 0; 1484 int UNUSED insn_referenced = abuf->written; 1485 INT in_src1 = -1; 1486 INT in_src2 = -1; 1487 in_src1 = FLD (in_src1); 1488 in_src2 = FLD (in_src2); 1489 referenced |= 1 << 0; 1490 referenced |= 1 << 1; 1491 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1492 } 1493 return cycles; 1494 #undef FLD 1495 } 1496 1497 static int 1498 model_m32rx_macwlo_a (SIM_CPU *current_cpu, void *sem_arg) 1499 { 1500 #define FLD(f) abuf->fields.sfmt_machi_a.f 1501 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1502 const IDESC * UNUSED idesc = abuf->idesc; 1503 int cycles = 0; 1504 { 1505 int referenced = 0; 1506 int UNUSED insn_referenced = abuf->written; 1507 INT in_src1 = -1; 1508 INT in_src2 = -1; 1509 in_src1 = FLD (in_src1); 1510 in_src2 = FLD (in_src2); 1511 referenced |= 1 << 0; 1512 referenced |= 1 << 1; 1513 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1514 } 1515 return cycles; 1516 #undef FLD 1517 } 1518 1519 static int 1520 model_m32rx_mul (SIM_CPU *current_cpu, void *sem_arg) 1521 { 1522 #define FLD(f) abuf->fields.sfmt_add.f 1523 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1524 const IDESC * UNUSED idesc = abuf->idesc; 1525 int cycles = 0; 1526 { 1527 int referenced = 0; 1528 int UNUSED insn_referenced = abuf->written; 1529 INT in_sr = -1; 1530 INT in_dr = -1; 1531 INT out_dr = -1; 1532 in_sr = FLD (in_sr); 1533 in_dr = FLD (in_dr); 1534 out_dr = FLD (out_dr); 1535 referenced |= 1 << 0; 1536 referenced |= 1 << 1; 1537 referenced |= 1 << 2; 1538 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1539 } 1540 return cycles; 1541 #undef FLD 1542 } 1543 1544 static int 1545 model_m32rx_mulhi_a (SIM_CPU *current_cpu, void *sem_arg) 1546 { 1547 #define FLD(f) abuf->fields.sfmt_machi_a.f 1548 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1549 const IDESC * UNUSED idesc = abuf->idesc; 1550 int cycles = 0; 1551 { 1552 int referenced = 0; 1553 int UNUSED insn_referenced = abuf->written; 1554 INT in_src1 = -1; 1555 INT in_src2 = -1; 1556 in_src1 = FLD (in_src1); 1557 in_src2 = FLD (in_src2); 1558 referenced |= 1 << 0; 1559 referenced |= 1 << 1; 1560 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1561 } 1562 return cycles; 1563 #undef FLD 1564 } 1565 1566 static int 1567 model_m32rx_mullo_a (SIM_CPU *current_cpu, void *sem_arg) 1568 { 1569 #define FLD(f) abuf->fields.sfmt_machi_a.f 1570 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1571 const IDESC * UNUSED idesc = abuf->idesc; 1572 int cycles = 0; 1573 { 1574 int referenced = 0; 1575 int UNUSED insn_referenced = abuf->written; 1576 INT in_src1 = -1; 1577 INT in_src2 = -1; 1578 in_src1 = FLD (in_src1); 1579 in_src2 = FLD (in_src2); 1580 referenced |= 1 << 0; 1581 referenced |= 1 << 1; 1582 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1583 } 1584 return cycles; 1585 #undef FLD 1586 } 1587 1588 static int 1589 model_m32rx_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg) 1590 { 1591 #define FLD(f) abuf->fields.sfmt_machi_a.f 1592 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1593 const IDESC * UNUSED idesc = abuf->idesc; 1594 int cycles = 0; 1595 { 1596 int referenced = 0; 1597 int UNUSED insn_referenced = abuf->written; 1598 INT in_src1 = -1; 1599 INT in_src2 = -1; 1600 in_src1 = FLD (in_src1); 1601 in_src2 = FLD (in_src2); 1602 referenced |= 1 << 0; 1603 referenced |= 1 << 1; 1604 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1605 } 1606 return cycles; 1607 #undef FLD 1608 } 1609 1610 static int 1611 model_m32rx_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg) 1612 { 1613 #define FLD(f) abuf->fields.sfmt_machi_a.f 1614 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1615 const IDESC * UNUSED idesc = abuf->idesc; 1616 int cycles = 0; 1617 { 1618 int referenced = 0; 1619 int UNUSED insn_referenced = abuf->written; 1620 INT in_src1 = -1; 1621 INT in_src2 = -1; 1622 in_src1 = FLD (in_src1); 1623 in_src2 = FLD (in_src2); 1624 referenced |= 1 << 0; 1625 referenced |= 1 << 1; 1626 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1627 } 1628 return cycles; 1629 #undef FLD 1630 } 1631 1632 static int 1633 model_m32rx_mv (SIM_CPU *current_cpu, void *sem_arg) 1634 { 1635 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1636 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1637 const IDESC * UNUSED idesc = abuf->idesc; 1638 int cycles = 0; 1639 { 1640 int referenced = 0; 1641 int UNUSED insn_referenced = abuf->written; 1642 INT in_sr = -1; 1643 INT in_dr = -1; 1644 INT out_dr = -1; 1645 in_sr = FLD (in_sr); 1646 out_dr = FLD (out_dr); 1647 referenced |= 1 << 0; 1648 referenced |= 1 << 2; 1649 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1650 } 1651 return cycles; 1652 #undef FLD 1653 } 1654 1655 static int 1656 model_m32rx_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg) 1657 { 1658 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f 1659 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1660 const IDESC * UNUSED idesc = abuf->idesc; 1661 int cycles = 0; 1662 { 1663 int referenced = 0; 1664 int UNUSED insn_referenced = abuf->written; 1665 INT in_sr = -1; 1666 INT in_dr = -1; 1667 INT out_dr = -1; 1668 out_dr = FLD (out_dr); 1669 referenced |= 1 << 2; 1670 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1671 } 1672 return cycles; 1673 #undef FLD 1674 } 1675 1676 static int 1677 model_m32rx_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg) 1678 { 1679 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f 1680 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1681 const IDESC * UNUSED idesc = abuf->idesc; 1682 int cycles = 0; 1683 { 1684 int referenced = 0; 1685 int UNUSED insn_referenced = abuf->written; 1686 INT in_sr = -1; 1687 INT in_dr = -1; 1688 INT out_dr = -1; 1689 out_dr = FLD (out_dr); 1690 referenced |= 1 << 2; 1691 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1692 } 1693 return cycles; 1694 #undef FLD 1695 } 1696 1697 static int 1698 model_m32rx_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg) 1699 { 1700 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f 1701 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1702 const IDESC * UNUSED idesc = abuf->idesc; 1703 int cycles = 0; 1704 { 1705 int referenced = 0; 1706 int UNUSED insn_referenced = abuf->written; 1707 INT in_sr = -1; 1708 INT in_dr = -1; 1709 INT out_dr = -1; 1710 out_dr = FLD (out_dr); 1711 referenced |= 1 << 2; 1712 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1713 } 1714 return cycles; 1715 #undef FLD 1716 } 1717 1718 static int 1719 model_m32rx_mvfc (SIM_CPU *current_cpu, void *sem_arg) 1720 { 1721 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1722 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1723 const IDESC * UNUSED idesc = abuf->idesc; 1724 int cycles = 0; 1725 { 1726 int referenced = 0; 1727 int UNUSED insn_referenced = abuf->written; 1728 INT in_sr = -1; 1729 INT in_dr = -1; 1730 INT out_dr = -1; 1731 out_dr = FLD (out_dr); 1732 referenced |= 1 << 2; 1733 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1734 } 1735 return cycles; 1736 #undef FLD 1737 } 1738 1739 static int 1740 model_m32rx_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg) 1741 { 1742 #define FLD(f) abuf->fields.sfmt_mvtachi_a.f 1743 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1744 const IDESC * UNUSED idesc = abuf->idesc; 1745 int cycles = 0; 1746 { 1747 int referenced = 0; 1748 int UNUSED insn_referenced = abuf->written; 1749 INT in_sr = -1; 1750 INT in_dr = -1; 1751 INT out_dr = -1; 1752 in_sr = FLD (in_src1); 1753 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1754 } 1755 return cycles; 1756 #undef FLD 1757 } 1758 1759 static int 1760 model_m32rx_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg) 1761 { 1762 #define FLD(f) abuf->fields.sfmt_mvtachi_a.f 1763 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1764 const IDESC * UNUSED idesc = abuf->idesc; 1765 int cycles = 0; 1766 { 1767 int referenced = 0; 1768 int UNUSED insn_referenced = abuf->written; 1769 INT in_sr = -1; 1770 INT in_dr = -1; 1771 INT out_dr = -1; 1772 in_sr = FLD (in_src1); 1773 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1774 } 1775 return cycles; 1776 #undef FLD 1777 } 1778 1779 static int 1780 model_m32rx_mvtc (SIM_CPU *current_cpu, void *sem_arg) 1781 { 1782 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1783 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1784 const IDESC * UNUSED idesc = abuf->idesc; 1785 int cycles = 0; 1786 { 1787 int referenced = 0; 1788 int UNUSED insn_referenced = abuf->written; 1789 INT in_sr = -1; 1790 INT in_dr = -1; 1791 INT out_dr = -1; 1792 in_sr = FLD (in_sr); 1793 referenced |= 1 << 0; 1794 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1795 } 1796 return cycles; 1797 #undef FLD 1798 } 1799 1800 static int 1801 model_m32rx_neg (SIM_CPU *current_cpu, void *sem_arg) 1802 { 1803 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1804 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1805 const IDESC * UNUSED idesc = abuf->idesc; 1806 int cycles = 0; 1807 { 1808 int referenced = 0; 1809 int UNUSED insn_referenced = abuf->written; 1810 INT in_sr = -1; 1811 INT in_dr = -1; 1812 INT out_dr = -1; 1813 in_sr = FLD (in_sr); 1814 out_dr = FLD (out_dr); 1815 referenced |= 1 << 0; 1816 referenced |= 1 << 2; 1817 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1818 } 1819 return cycles; 1820 #undef FLD 1821 } 1822 1823 static int 1824 model_m32rx_nop (SIM_CPU *current_cpu, void *sem_arg) 1825 { 1826 #define FLD(f) abuf->fields.sfmt_empty.f 1827 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1828 const IDESC * UNUSED idesc = abuf->idesc; 1829 int cycles = 0; 1830 { 1831 int referenced = 0; 1832 int UNUSED insn_referenced = abuf->written; 1833 INT in_sr = -1; 1834 INT in_dr = -1; 1835 INT out_dr = -1; 1836 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1837 } 1838 return cycles; 1839 #undef FLD 1840 } 1841 1842 static int 1843 model_m32rx_not (SIM_CPU *current_cpu, void *sem_arg) 1844 { 1845 #define FLD(f) abuf->fields.sfmt_ld_plus.f 1846 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1847 const IDESC * UNUSED idesc = abuf->idesc; 1848 int cycles = 0; 1849 { 1850 int referenced = 0; 1851 int UNUSED insn_referenced = abuf->written; 1852 INT in_sr = -1; 1853 INT in_dr = -1; 1854 INT out_dr = -1; 1855 in_sr = FLD (in_sr); 1856 out_dr = FLD (out_dr); 1857 referenced |= 1 << 0; 1858 referenced |= 1 << 2; 1859 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1860 } 1861 return cycles; 1862 #undef FLD 1863 } 1864 1865 static int 1866 model_m32rx_rac_dsi (SIM_CPU *current_cpu, void *sem_arg) 1867 { 1868 #define FLD(f) abuf->fields.sfmt_rac_dsi.f 1869 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1870 const IDESC * UNUSED idesc = abuf->idesc; 1871 int cycles = 0; 1872 { 1873 int referenced = 0; 1874 int UNUSED insn_referenced = abuf->written; 1875 INT in_src1 = -1; 1876 INT in_src2 = -1; 1877 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1878 } 1879 return cycles; 1880 #undef FLD 1881 } 1882 1883 static int 1884 model_m32rx_rach_dsi (SIM_CPU *current_cpu, void *sem_arg) 1885 { 1886 #define FLD(f) abuf->fields.sfmt_rac_dsi.f 1887 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1888 const IDESC * UNUSED idesc = abuf->idesc; 1889 int cycles = 0; 1890 { 1891 int referenced = 0; 1892 int UNUSED insn_referenced = abuf->written; 1893 INT in_src1 = -1; 1894 INT in_src2 = -1; 1895 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 1896 } 1897 return cycles; 1898 #undef FLD 1899 } 1900 1901 static int 1902 model_m32rx_rte (SIM_CPU *current_cpu, void *sem_arg) 1903 { 1904 #define FLD(f) abuf->fields.sfmt_empty.f 1905 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1906 const IDESC * UNUSED idesc = abuf->idesc; 1907 int cycles = 0; 1908 { 1909 int referenced = 0; 1910 int UNUSED insn_referenced = abuf->written; 1911 INT in_sr = -1; 1912 INT in_dr = -1; 1913 INT out_dr = -1; 1914 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1915 } 1916 return cycles; 1917 #undef FLD 1918 } 1919 1920 static int 1921 model_m32rx_seth (SIM_CPU *current_cpu, void *sem_arg) 1922 { 1923 #define FLD(f) abuf->fields.sfmt_seth.f 1924 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1925 const IDESC * UNUSED idesc = abuf->idesc; 1926 int cycles = 0; 1927 { 1928 int referenced = 0; 1929 int UNUSED insn_referenced = abuf->written; 1930 INT in_sr = -1; 1931 INT in_dr = -1; 1932 INT out_dr = -1; 1933 out_dr = FLD (out_dr); 1934 referenced |= 1 << 2; 1935 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1936 } 1937 return cycles; 1938 #undef FLD 1939 } 1940 1941 static int 1942 model_m32rx_sll (SIM_CPU *current_cpu, void *sem_arg) 1943 { 1944 #define FLD(f) abuf->fields.sfmt_add.f 1945 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1946 const IDESC * UNUSED idesc = abuf->idesc; 1947 int cycles = 0; 1948 { 1949 int referenced = 0; 1950 int UNUSED insn_referenced = abuf->written; 1951 INT in_sr = -1; 1952 INT in_dr = -1; 1953 INT out_dr = -1; 1954 in_sr = FLD (in_sr); 1955 in_dr = FLD (in_dr); 1956 out_dr = FLD (out_dr); 1957 referenced |= 1 << 0; 1958 referenced |= 1 << 1; 1959 referenced |= 1 << 2; 1960 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1961 } 1962 return cycles; 1963 #undef FLD 1964 } 1965 1966 static int 1967 model_m32rx_sll3 (SIM_CPU *current_cpu, void *sem_arg) 1968 { 1969 #define FLD(f) abuf->fields.sfmt_add3.f 1970 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1971 const IDESC * UNUSED idesc = abuf->idesc; 1972 int cycles = 0; 1973 { 1974 int referenced = 0; 1975 int UNUSED insn_referenced = abuf->written; 1976 INT in_sr = -1; 1977 INT in_dr = -1; 1978 INT out_dr = -1; 1979 in_sr = FLD (in_sr); 1980 out_dr = FLD (out_dr); 1981 referenced |= 1 << 0; 1982 referenced |= 1 << 2; 1983 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 1984 } 1985 return cycles; 1986 #undef FLD 1987 } 1988 1989 static int 1990 model_m32rx_slli (SIM_CPU *current_cpu, void *sem_arg) 1991 { 1992 #define FLD(f) abuf->fields.sfmt_slli.f 1993 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 1994 const IDESC * UNUSED idesc = abuf->idesc; 1995 int cycles = 0; 1996 { 1997 int referenced = 0; 1998 int UNUSED insn_referenced = abuf->written; 1999 INT in_sr = -1; 2000 INT in_dr = -1; 2001 INT out_dr = -1; 2002 in_dr = FLD (in_dr); 2003 out_dr = FLD (out_dr); 2004 referenced |= 1 << 1; 2005 referenced |= 1 << 2; 2006 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2007 } 2008 return cycles; 2009 #undef FLD 2010 } 2011 2012 static int 2013 model_m32rx_sra (SIM_CPU *current_cpu, void *sem_arg) 2014 { 2015 #define FLD(f) abuf->fields.sfmt_add.f 2016 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2017 const IDESC * UNUSED idesc = abuf->idesc; 2018 int cycles = 0; 2019 { 2020 int referenced = 0; 2021 int UNUSED insn_referenced = abuf->written; 2022 INT in_sr = -1; 2023 INT in_dr = -1; 2024 INT out_dr = -1; 2025 in_sr = FLD (in_sr); 2026 in_dr = FLD (in_dr); 2027 out_dr = FLD (out_dr); 2028 referenced |= 1 << 0; 2029 referenced |= 1 << 1; 2030 referenced |= 1 << 2; 2031 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2032 } 2033 return cycles; 2034 #undef FLD 2035 } 2036 2037 static int 2038 model_m32rx_sra3 (SIM_CPU *current_cpu, void *sem_arg) 2039 { 2040 #define FLD(f) abuf->fields.sfmt_add3.f 2041 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2042 const IDESC * UNUSED idesc = abuf->idesc; 2043 int cycles = 0; 2044 { 2045 int referenced = 0; 2046 int UNUSED insn_referenced = abuf->written; 2047 INT in_sr = -1; 2048 INT in_dr = -1; 2049 INT out_dr = -1; 2050 in_sr = FLD (in_sr); 2051 out_dr = FLD (out_dr); 2052 referenced |= 1 << 0; 2053 referenced |= 1 << 2; 2054 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2055 } 2056 return cycles; 2057 #undef FLD 2058 } 2059 2060 static int 2061 model_m32rx_srai (SIM_CPU *current_cpu, void *sem_arg) 2062 { 2063 #define FLD(f) abuf->fields.sfmt_slli.f 2064 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2065 const IDESC * UNUSED idesc = abuf->idesc; 2066 int cycles = 0; 2067 { 2068 int referenced = 0; 2069 int UNUSED insn_referenced = abuf->written; 2070 INT in_sr = -1; 2071 INT in_dr = -1; 2072 INT out_dr = -1; 2073 in_dr = FLD (in_dr); 2074 out_dr = FLD (out_dr); 2075 referenced |= 1 << 1; 2076 referenced |= 1 << 2; 2077 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2078 } 2079 return cycles; 2080 #undef FLD 2081 } 2082 2083 static int 2084 model_m32rx_srl (SIM_CPU *current_cpu, void *sem_arg) 2085 { 2086 #define FLD(f) abuf->fields.sfmt_add.f 2087 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2088 const IDESC * UNUSED idesc = abuf->idesc; 2089 int cycles = 0; 2090 { 2091 int referenced = 0; 2092 int UNUSED insn_referenced = abuf->written; 2093 INT in_sr = -1; 2094 INT in_dr = -1; 2095 INT out_dr = -1; 2096 in_sr = FLD (in_sr); 2097 in_dr = FLD (in_dr); 2098 out_dr = FLD (out_dr); 2099 referenced |= 1 << 0; 2100 referenced |= 1 << 1; 2101 referenced |= 1 << 2; 2102 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2103 } 2104 return cycles; 2105 #undef FLD 2106 } 2107 2108 static int 2109 model_m32rx_srl3 (SIM_CPU *current_cpu, void *sem_arg) 2110 { 2111 #define FLD(f) abuf->fields.sfmt_add3.f 2112 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2113 const IDESC * UNUSED idesc = abuf->idesc; 2114 int cycles = 0; 2115 { 2116 int referenced = 0; 2117 int UNUSED insn_referenced = abuf->written; 2118 INT in_sr = -1; 2119 INT in_dr = -1; 2120 INT out_dr = -1; 2121 in_sr = FLD (in_sr); 2122 out_dr = FLD (out_dr); 2123 referenced |= 1 << 0; 2124 referenced |= 1 << 2; 2125 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2126 } 2127 return cycles; 2128 #undef FLD 2129 } 2130 2131 static int 2132 model_m32rx_srli (SIM_CPU *current_cpu, void *sem_arg) 2133 { 2134 #define FLD(f) abuf->fields.sfmt_slli.f 2135 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2136 const IDESC * UNUSED idesc = abuf->idesc; 2137 int cycles = 0; 2138 { 2139 int referenced = 0; 2140 int UNUSED insn_referenced = abuf->written; 2141 INT in_sr = -1; 2142 INT in_dr = -1; 2143 INT out_dr = -1; 2144 in_dr = FLD (in_dr); 2145 out_dr = FLD (out_dr); 2146 referenced |= 1 << 1; 2147 referenced |= 1 << 2; 2148 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2149 } 2150 return cycles; 2151 #undef FLD 2152 } 2153 2154 static int 2155 model_m32rx_st (SIM_CPU *current_cpu, void *sem_arg) 2156 { 2157 #define FLD(f) abuf->fields.sfmt_st_plus.f 2158 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2159 const IDESC * UNUSED idesc = abuf->idesc; 2160 int cycles = 0; 2161 { 2162 int referenced = 0; 2163 int UNUSED insn_referenced = abuf->written; 2164 INT in_src1 = 0; 2165 INT in_src2 = 0; 2166 in_src1 = FLD (in_src1); 2167 in_src2 = FLD (in_src2); 2168 referenced |= 1 << 0; 2169 referenced |= 1 << 1; 2170 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2171 } 2172 return cycles; 2173 #undef FLD 2174 } 2175 2176 static int 2177 model_m32rx_st_d (SIM_CPU *current_cpu, void *sem_arg) 2178 { 2179 #define FLD(f) abuf->fields.sfmt_st_d.f 2180 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2181 const IDESC * UNUSED idesc = abuf->idesc; 2182 int cycles = 0; 2183 { 2184 int referenced = 0; 2185 int UNUSED insn_referenced = abuf->written; 2186 INT in_src1 = 0; 2187 INT in_src2 = 0; 2188 in_src1 = FLD (in_src1); 2189 in_src2 = FLD (in_src2); 2190 referenced |= 1 << 0; 2191 referenced |= 1 << 1; 2192 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2193 } 2194 return cycles; 2195 #undef FLD 2196 } 2197 2198 static int 2199 model_m32rx_stb (SIM_CPU *current_cpu, void *sem_arg) 2200 { 2201 #define FLD(f) abuf->fields.sfmt_st_plus.f 2202 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2203 const IDESC * UNUSED idesc = abuf->idesc; 2204 int cycles = 0; 2205 { 2206 int referenced = 0; 2207 int UNUSED insn_referenced = abuf->written; 2208 INT in_src1 = 0; 2209 INT in_src2 = 0; 2210 in_src1 = FLD (in_src1); 2211 in_src2 = FLD (in_src2); 2212 referenced |= 1 << 0; 2213 referenced |= 1 << 1; 2214 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2215 } 2216 return cycles; 2217 #undef FLD 2218 } 2219 2220 static int 2221 model_m32rx_stb_d (SIM_CPU *current_cpu, void *sem_arg) 2222 { 2223 #define FLD(f) abuf->fields.sfmt_st_d.f 2224 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2225 const IDESC * UNUSED idesc = abuf->idesc; 2226 int cycles = 0; 2227 { 2228 int referenced = 0; 2229 int UNUSED insn_referenced = abuf->written; 2230 INT in_src1 = 0; 2231 INT in_src2 = 0; 2232 in_src1 = FLD (in_src1); 2233 in_src2 = FLD (in_src2); 2234 referenced |= 1 << 0; 2235 referenced |= 1 << 1; 2236 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2237 } 2238 return cycles; 2239 #undef FLD 2240 } 2241 2242 static int 2243 model_m32rx_sth (SIM_CPU *current_cpu, void *sem_arg) 2244 { 2245 #define FLD(f) abuf->fields.sfmt_st_plus.f 2246 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2247 const IDESC * UNUSED idesc = abuf->idesc; 2248 int cycles = 0; 2249 { 2250 int referenced = 0; 2251 int UNUSED insn_referenced = abuf->written; 2252 INT in_src1 = 0; 2253 INT in_src2 = 0; 2254 in_src1 = FLD (in_src1); 2255 in_src2 = FLD (in_src2); 2256 referenced |= 1 << 0; 2257 referenced |= 1 << 1; 2258 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2259 } 2260 return cycles; 2261 #undef FLD 2262 } 2263 2264 static int 2265 model_m32rx_sth_d (SIM_CPU *current_cpu, void *sem_arg) 2266 { 2267 #define FLD(f) abuf->fields.sfmt_st_d.f 2268 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2269 const IDESC * UNUSED idesc = abuf->idesc; 2270 int cycles = 0; 2271 { 2272 int referenced = 0; 2273 int UNUSED insn_referenced = abuf->written; 2274 INT in_src1 = 0; 2275 INT in_src2 = 0; 2276 in_src1 = FLD (in_src1); 2277 in_src2 = FLD (in_src2); 2278 referenced |= 1 << 0; 2279 referenced |= 1 << 1; 2280 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2281 } 2282 return cycles; 2283 #undef FLD 2284 } 2285 2286 static int 2287 model_m32rx_st_plus (SIM_CPU *current_cpu, void *sem_arg) 2288 { 2289 #define FLD(f) abuf->fields.sfmt_st_plus.f 2290 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2291 const IDESC * UNUSED idesc = abuf->idesc; 2292 int cycles = 0; 2293 { 2294 int referenced = 0; 2295 int UNUSED insn_referenced = abuf->written; 2296 INT in_src1 = 0; 2297 INT in_src2 = 0; 2298 in_src1 = FLD (in_src1); 2299 in_src2 = FLD (in_src2); 2300 referenced |= 1 << 0; 2301 referenced |= 1 << 1; 2302 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2303 } 2304 { 2305 int referenced = 0; 2306 int UNUSED insn_referenced = abuf->written; 2307 INT in_sr = -1; 2308 INT in_dr = -1; 2309 INT out_dr = -1; 2310 in_dr = FLD (in_src2); 2311 out_dr = FLD (out_src2); 2312 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); 2313 } 2314 return cycles; 2315 #undef FLD 2316 } 2317 2318 static int 2319 model_m32rx_sth_plus (SIM_CPU *current_cpu, void *sem_arg) 2320 { 2321 #define FLD(f) abuf->fields.sfmt_st_plus.f 2322 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2323 const IDESC * UNUSED idesc = abuf->idesc; 2324 int cycles = 0; 2325 { 2326 int referenced = 0; 2327 int UNUSED insn_referenced = abuf->written; 2328 INT in_src1 = 0; 2329 INT in_src2 = 0; 2330 in_src1 = FLD (in_src1); 2331 in_src2 = FLD (in_src2); 2332 referenced |= 1 << 0; 2333 referenced |= 1 << 1; 2334 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2335 } 2336 { 2337 int referenced = 0; 2338 int UNUSED insn_referenced = abuf->written; 2339 INT in_sr = -1; 2340 INT in_dr = -1; 2341 INT out_dr = -1; 2342 in_dr = FLD (in_src2); 2343 out_dr = FLD (out_src2); 2344 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); 2345 } 2346 return cycles; 2347 #undef FLD 2348 } 2349 2350 static int 2351 model_m32rx_stb_plus (SIM_CPU *current_cpu, void *sem_arg) 2352 { 2353 #define FLD(f) abuf->fields.sfmt_st_plus.f 2354 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2355 const IDESC * UNUSED idesc = abuf->idesc; 2356 int cycles = 0; 2357 { 2358 int referenced = 0; 2359 int UNUSED insn_referenced = abuf->written; 2360 INT in_src1 = 0; 2361 INT in_src2 = 0; 2362 in_src1 = FLD (in_src1); 2363 in_src2 = FLD (in_src2); 2364 referenced |= 1 << 0; 2365 referenced |= 1 << 1; 2366 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2367 } 2368 { 2369 int referenced = 0; 2370 int UNUSED insn_referenced = abuf->written; 2371 INT in_sr = -1; 2372 INT in_dr = -1; 2373 INT out_dr = -1; 2374 in_dr = FLD (in_src2); 2375 out_dr = FLD (out_src2); 2376 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); 2377 } 2378 return cycles; 2379 #undef FLD 2380 } 2381 2382 static int 2383 model_m32rx_st_minus (SIM_CPU *current_cpu, void *sem_arg) 2384 { 2385 #define FLD(f) abuf->fields.sfmt_st_plus.f 2386 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2387 const IDESC * UNUSED idesc = abuf->idesc; 2388 int cycles = 0; 2389 { 2390 int referenced = 0; 2391 int UNUSED insn_referenced = abuf->written; 2392 INT in_src1 = 0; 2393 INT in_src2 = 0; 2394 in_src1 = FLD (in_src1); 2395 in_src2 = FLD (in_src2); 2396 referenced |= 1 << 0; 2397 referenced |= 1 << 1; 2398 cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2399 } 2400 { 2401 int referenced = 0; 2402 int UNUSED insn_referenced = abuf->written; 2403 INT in_sr = -1; 2404 INT in_dr = -1; 2405 INT out_dr = -1; 2406 in_dr = FLD (in_src2); 2407 out_dr = FLD (out_src2); 2408 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); 2409 } 2410 return cycles; 2411 #undef FLD 2412 } 2413 2414 static int 2415 model_m32rx_sub (SIM_CPU *current_cpu, void *sem_arg) 2416 { 2417 #define FLD(f) abuf->fields.sfmt_add.f 2418 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2419 const IDESC * UNUSED idesc = abuf->idesc; 2420 int cycles = 0; 2421 { 2422 int referenced = 0; 2423 int UNUSED insn_referenced = abuf->written; 2424 INT in_sr = -1; 2425 INT in_dr = -1; 2426 INT out_dr = -1; 2427 in_sr = FLD (in_sr); 2428 in_dr = FLD (in_dr); 2429 out_dr = FLD (out_dr); 2430 referenced |= 1 << 0; 2431 referenced |= 1 << 1; 2432 referenced |= 1 << 2; 2433 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2434 } 2435 return cycles; 2436 #undef FLD 2437 } 2438 2439 static int 2440 model_m32rx_subv (SIM_CPU *current_cpu, void *sem_arg) 2441 { 2442 #define FLD(f) abuf->fields.sfmt_add.f 2443 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2444 const IDESC * UNUSED idesc = abuf->idesc; 2445 int cycles = 0; 2446 { 2447 int referenced = 0; 2448 int UNUSED insn_referenced = abuf->written; 2449 INT in_sr = -1; 2450 INT in_dr = -1; 2451 INT out_dr = -1; 2452 in_sr = FLD (in_sr); 2453 in_dr = FLD (in_dr); 2454 out_dr = FLD (out_dr); 2455 referenced |= 1 << 0; 2456 referenced |= 1 << 1; 2457 referenced |= 1 << 2; 2458 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2459 } 2460 return cycles; 2461 #undef FLD 2462 } 2463 2464 static int 2465 model_m32rx_subx (SIM_CPU *current_cpu, void *sem_arg) 2466 { 2467 #define FLD(f) abuf->fields.sfmt_add.f 2468 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2469 const IDESC * UNUSED idesc = abuf->idesc; 2470 int cycles = 0; 2471 { 2472 int referenced = 0; 2473 int UNUSED insn_referenced = abuf->written; 2474 INT in_sr = -1; 2475 INT in_dr = -1; 2476 INT out_dr = -1; 2477 in_sr = FLD (in_sr); 2478 in_dr = FLD (in_dr); 2479 out_dr = FLD (out_dr); 2480 referenced |= 1 << 0; 2481 referenced |= 1 << 1; 2482 referenced |= 1 << 2; 2483 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2484 } 2485 return cycles; 2486 #undef FLD 2487 } 2488 2489 static int 2490 model_m32rx_trap (SIM_CPU *current_cpu, void *sem_arg) 2491 { 2492 #define FLD(f) abuf->fields.sfmt_trap.f 2493 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2494 const IDESC * UNUSED idesc = abuf->idesc; 2495 int cycles = 0; 2496 { 2497 int referenced = 0; 2498 int UNUSED insn_referenced = abuf->written; 2499 INT in_sr = -1; 2500 INT in_dr = -1; 2501 INT out_dr = -1; 2502 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2503 } 2504 return cycles; 2505 #undef FLD 2506 } 2507 2508 static int 2509 model_m32rx_unlock (SIM_CPU *current_cpu, void *sem_arg) 2510 { 2511 #define FLD(f) abuf->fields.sfmt_st_plus.f 2512 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2513 const IDESC * UNUSED idesc = abuf->idesc; 2514 int cycles = 0; 2515 { 2516 int referenced = 0; 2517 int UNUSED insn_referenced = abuf->written; 2518 INT in_sr = 0; 2519 INT out_dr = 0; 2520 cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); 2521 } 2522 return cycles; 2523 #undef FLD 2524 } 2525 2526 static int 2527 model_m32rx_satb (SIM_CPU *current_cpu, void *sem_arg) 2528 { 2529 #define FLD(f) abuf->fields.sfmt_ld_plus.f 2530 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2531 const IDESC * UNUSED idesc = abuf->idesc; 2532 int cycles = 0; 2533 { 2534 int referenced = 0; 2535 int UNUSED insn_referenced = abuf->written; 2536 INT in_sr = -1; 2537 INT in_dr = -1; 2538 INT out_dr = -1; 2539 in_sr = FLD (in_sr); 2540 out_dr = FLD (out_dr); 2541 referenced |= 1 << 0; 2542 referenced |= 1 << 2; 2543 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2544 } 2545 return cycles; 2546 #undef FLD 2547 } 2548 2549 static int 2550 model_m32rx_sath (SIM_CPU *current_cpu, void *sem_arg) 2551 { 2552 #define FLD(f) abuf->fields.sfmt_ld_plus.f 2553 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2554 const IDESC * UNUSED idesc = abuf->idesc; 2555 int cycles = 0; 2556 { 2557 int referenced = 0; 2558 int UNUSED insn_referenced = abuf->written; 2559 INT in_sr = -1; 2560 INT in_dr = -1; 2561 INT out_dr = -1; 2562 in_sr = FLD (in_sr); 2563 out_dr = FLD (out_dr); 2564 referenced |= 1 << 0; 2565 referenced |= 1 << 2; 2566 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2567 } 2568 return cycles; 2569 #undef FLD 2570 } 2571 2572 static int 2573 model_m32rx_sat (SIM_CPU *current_cpu, void *sem_arg) 2574 { 2575 #define FLD(f) abuf->fields.sfmt_ld_plus.f 2576 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2577 const IDESC * UNUSED idesc = abuf->idesc; 2578 int cycles = 0; 2579 { 2580 int referenced = 0; 2581 int UNUSED insn_referenced = abuf->written; 2582 INT in_sr = -1; 2583 INT in_dr = -1; 2584 INT out_dr = -1; 2585 in_sr = FLD (in_sr); 2586 out_dr = FLD (out_dr); 2587 if (insn_referenced & (1 << 1)) referenced |= 1 << 0; 2588 referenced |= 1 << 2; 2589 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2590 } 2591 return cycles; 2592 #undef FLD 2593 } 2594 2595 static int 2596 model_m32rx_pcmpbz (SIM_CPU *current_cpu, void *sem_arg) 2597 { 2598 #define FLD(f) abuf->fields.sfmt_st_plus.f 2599 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2600 const IDESC * UNUSED idesc = abuf->idesc; 2601 int cycles = 0; 2602 { 2603 int referenced = 0; 2604 int UNUSED insn_referenced = abuf->written; 2605 INT in_src1 = -1; 2606 INT in_src2 = -1; 2607 in_src2 = FLD (in_src2); 2608 referenced |= 1 << 1; 2609 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2610 } 2611 return cycles; 2612 #undef FLD 2613 } 2614 2615 static int 2616 model_m32rx_sadd (SIM_CPU *current_cpu, void *sem_arg) 2617 { 2618 #define FLD(f) abuf->fields.sfmt_empty.f 2619 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2620 const IDESC * UNUSED idesc = abuf->idesc; 2621 int cycles = 0; 2622 { 2623 int referenced = 0; 2624 int UNUSED insn_referenced = abuf->written; 2625 INT in_src1 = -1; 2626 INT in_src2 = -1; 2627 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2628 } 2629 return cycles; 2630 #undef FLD 2631 } 2632 2633 static int 2634 model_m32rx_macwu1 (SIM_CPU *current_cpu, void *sem_arg) 2635 { 2636 #define FLD(f) abuf->fields.sfmt_st_plus.f 2637 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2638 const IDESC * UNUSED idesc = abuf->idesc; 2639 int cycles = 0; 2640 { 2641 int referenced = 0; 2642 int UNUSED insn_referenced = abuf->written; 2643 INT in_src1 = -1; 2644 INT in_src2 = -1; 2645 in_src1 = FLD (in_src1); 2646 in_src2 = FLD (in_src2); 2647 referenced |= 1 << 0; 2648 referenced |= 1 << 1; 2649 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2650 } 2651 return cycles; 2652 #undef FLD 2653 } 2654 2655 static int 2656 model_m32rx_msblo (SIM_CPU *current_cpu, void *sem_arg) 2657 { 2658 #define FLD(f) abuf->fields.sfmt_st_plus.f 2659 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2660 const IDESC * UNUSED idesc = abuf->idesc; 2661 int cycles = 0; 2662 { 2663 int referenced = 0; 2664 int UNUSED insn_referenced = abuf->written; 2665 INT in_src1 = -1; 2666 INT in_src2 = -1; 2667 in_src1 = FLD (in_src1); 2668 in_src2 = FLD (in_src2); 2669 referenced |= 1 << 0; 2670 referenced |= 1 << 1; 2671 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2672 } 2673 return cycles; 2674 #undef FLD 2675 } 2676 2677 static int 2678 model_m32rx_mulwu1 (SIM_CPU *current_cpu, void *sem_arg) 2679 { 2680 #define FLD(f) abuf->fields.sfmt_st_plus.f 2681 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2682 const IDESC * UNUSED idesc = abuf->idesc; 2683 int cycles = 0; 2684 { 2685 int referenced = 0; 2686 int UNUSED insn_referenced = abuf->written; 2687 INT in_src1 = -1; 2688 INT in_src2 = -1; 2689 in_src1 = FLD (in_src1); 2690 in_src2 = FLD (in_src2); 2691 referenced |= 1 << 0; 2692 referenced |= 1 << 1; 2693 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2694 } 2695 return cycles; 2696 #undef FLD 2697 } 2698 2699 static int 2700 model_m32rx_maclh1 (SIM_CPU *current_cpu, void *sem_arg) 2701 { 2702 #define FLD(f) abuf->fields.sfmt_st_plus.f 2703 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2704 const IDESC * UNUSED idesc = abuf->idesc; 2705 int cycles = 0; 2706 { 2707 int referenced = 0; 2708 int UNUSED insn_referenced = abuf->written; 2709 INT in_src1 = -1; 2710 INT in_src2 = -1; 2711 in_src1 = FLD (in_src1); 2712 in_src2 = FLD (in_src2); 2713 referenced |= 1 << 0; 2714 referenced |= 1 << 1; 2715 cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); 2716 } 2717 return cycles; 2718 #undef FLD 2719 } 2720 2721 static int 2722 model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg) 2723 { 2724 #define FLD(f) abuf->fields.sfmt_empty.f 2725 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2726 const IDESC * UNUSED idesc = abuf->idesc; 2727 int cycles = 0; 2728 { 2729 int referenced = 0; 2730 int UNUSED insn_referenced = abuf->written; 2731 INT in_sr = -1; 2732 INT in_dr = -1; 2733 INT out_dr = -1; 2734 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2735 } 2736 return cycles; 2737 #undef FLD 2738 } 2739 2740 static int 2741 model_m32rx_snc (SIM_CPU *current_cpu, void *sem_arg) 2742 { 2743 #define FLD(f) abuf->fields.sfmt_empty.f 2744 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2745 const IDESC * UNUSED idesc = abuf->idesc; 2746 int cycles = 0; 2747 { 2748 int referenced = 0; 2749 int UNUSED insn_referenced = abuf->written; 2750 INT in_sr = -1; 2751 INT in_dr = -1; 2752 INT out_dr = -1; 2753 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2754 } 2755 return cycles; 2756 #undef FLD 2757 } 2758 2759 static int 2760 model_m32rx_clrpsw (SIM_CPU *current_cpu, void *sem_arg) 2761 { 2762 #define FLD(f) abuf->fields.sfmt_clrpsw.f 2763 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2764 const IDESC * UNUSED idesc = abuf->idesc; 2765 int cycles = 0; 2766 { 2767 int referenced = 0; 2768 int UNUSED insn_referenced = abuf->written; 2769 INT in_sr = -1; 2770 INT in_dr = -1; 2771 INT out_dr = -1; 2772 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2773 } 2774 return cycles; 2775 #undef FLD 2776 } 2777 2778 static int 2779 model_m32rx_setpsw (SIM_CPU *current_cpu, void *sem_arg) 2780 { 2781 #define FLD(f) abuf->fields.sfmt_clrpsw.f 2782 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2783 const IDESC * UNUSED idesc = abuf->idesc; 2784 int cycles = 0; 2785 { 2786 int referenced = 0; 2787 int UNUSED insn_referenced = abuf->written; 2788 INT in_sr = -1; 2789 INT in_dr = -1; 2790 INT out_dr = -1; 2791 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2792 } 2793 return cycles; 2794 #undef FLD 2795 } 2796 2797 static int 2798 model_m32rx_bset (SIM_CPU *current_cpu, void *sem_arg) 2799 { 2800 #define FLD(f) abuf->fields.sfmt_bset.f 2801 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2802 const IDESC * UNUSED idesc = abuf->idesc; 2803 int cycles = 0; 2804 { 2805 int referenced = 0; 2806 int UNUSED insn_referenced = abuf->written; 2807 INT in_sr = -1; 2808 INT in_dr = -1; 2809 INT out_dr = -1; 2810 in_sr = FLD (in_sr); 2811 referenced |= 1 << 0; 2812 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2813 } 2814 return cycles; 2815 #undef FLD 2816 } 2817 2818 static int 2819 model_m32rx_bclr (SIM_CPU *current_cpu, void *sem_arg) 2820 { 2821 #define FLD(f) abuf->fields.sfmt_bset.f 2822 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2823 const IDESC * UNUSED idesc = abuf->idesc; 2824 int cycles = 0; 2825 { 2826 int referenced = 0; 2827 int UNUSED insn_referenced = abuf->written; 2828 INT in_sr = -1; 2829 INT in_dr = -1; 2830 INT out_dr = -1; 2831 in_sr = FLD (in_sr); 2832 referenced |= 1 << 0; 2833 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2834 } 2835 return cycles; 2836 #undef FLD 2837 } 2838 2839 static int 2840 model_m32rx_btst (SIM_CPU *current_cpu, void *sem_arg) 2841 { 2842 #define FLD(f) abuf->fields.sfmt_bset.f 2843 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); 2844 const IDESC * UNUSED idesc = abuf->idesc; 2845 int cycles = 0; 2846 { 2847 int referenced = 0; 2848 int UNUSED insn_referenced = abuf->written; 2849 INT in_sr = -1; 2850 INT in_dr = -1; 2851 INT out_dr = -1; 2852 in_sr = FLD (in_sr); 2853 referenced |= 1 << 0; 2854 cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); 2855 } 2856 return cycles; 2857 #undef FLD 2858 } 2859 2860 /* We assume UNIT_NONE == 0 because the tables don't always terminate 2861 entries with it. */ 2862 2863 /* Model timing data for `m32rx'. */ 2864 2865 static const INSN_TIMING m32rx_timing[] = { 2866 { M32RXF_INSN_X_INVALID, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2867 { M32RXF_INSN_X_AFTER, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2868 { M32RXF_INSN_X_BEFORE, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2869 { M32RXF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2870 { M32RXF_INSN_X_CHAIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2871 { M32RXF_INSN_X_BEGIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2872 { M32RXF_INSN_ADD, model_m32rx_add, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2873 { M32RXF_INSN_ADD3, model_m32rx_add3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2874 { M32RXF_INSN_AND, model_m32rx_and, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2875 { M32RXF_INSN_AND3, model_m32rx_and3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2876 { M32RXF_INSN_OR, model_m32rx_or, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2877 { M32RXF_INSN_OR3, model_m32rx_or3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2878 { M32RXF_INSN_XOR, model_m32rx_xor, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2879 { M32RXF_INSN_XOR3, model_m32rx_xor3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2880 { M32RXF_INSN_ADDI, model_m32rx_addi, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2881 { M32RXF_INSN_ADDV, model_m32rx_addv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2882 { M32RXF_INSN_ADDV3, model_m32rx_addv3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2883 { M32RXF_INSN_ADDX, model_m32rx_addx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2884 { M32RXF_INSN_BC8, model_m32rx_bc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2885 { M32RXF_INSN_BC24, model_m32rx_bc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2886 { M32RXF_INSN_BEQ, model_m32rx_beq, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } }, 2887 { M32RXF_INSN_BEQZ, model_m32rx_beqz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } }, 2888 { M32RXF_INSN_BGEZ, model_m32rx_bgez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } }, 2889 { M32RXF_INSN_BGTZ, model_m32rx_bgtz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } }, 2890 { M32RXF_INSN_BLEZ, model_m32rx_blez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } }, 2891 { M32RXF_INSN_BLTZ, model_m32rx_bltz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } }, 2892 { M32RXF_INSN_BNEZ, model_m32rx_bnez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } }, 2893 { M32RXF_INSN_BL8, model_m32rx_bl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2894 { M32RXF_INSN_BL24, model_m32rx_bl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2895 { M32RXF_INSN_BCL8, model_m32rx_bcl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2896 { M32RXF_INSN_BCL24, model_m32rx_bcl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2897 { M32RXF_INSN_BNC8, model_m32rx_bnc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2898 { M32RXF_INSN_BNC24, model_m32rx_bnc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2899 { M32RXF_INSN_BNE, model_m32rx_bne, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } }, 2900 { M32RXF_INSN_BRA8, model_m32rx_bra8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2901 { M32RXF_INSN_BRA24, model_m32rx_bra24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2902 { M32RXF_INSN_BNCL8, model_m32rx_bncl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2903 { M32RXF_INSN_BNCL24, model_m32rx_bncl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2904 { M32RXF_INSN_CMP, model_m32rx_cmp, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } }, 2905 { M32RXF_INSN_CMPI, model_m32rx_cmpi, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } }, 2906 { M32RXF_INSN_CMPU, model_m32rx_cmpu, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } }, 2907 { M32RXF_INSN_CMPUI, model_m32rx_cmpui, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } }, 2908 { M32RXF_INSN_CMPEQ, model_m32rx_cmpeq, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } }, 2909 { M32RXF_INSN_CMPZ, model_m32rx_cmpz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } }, 2910 { M32RXF_INSN_DIV, model_m32rx_div, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } }, 2911 { M32RXF_INSN_DIVU, model_m32rx_divu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } }, 2912 { M32RXF_INSN_REM, model_m32rx_rem, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } }, 2913 { M32RXF_INSN_REMU, model_m32rx_remu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } }, 2914 { M32RXF_INSN_DIVH, model_m32rx_divh, { { (int) UNIT_M32RX_U_EXEC, 1, 21 } } }, 2915 { M32RXF_INSN_JC, model_m32rx_jc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2916 { M32RXF_INSN_JNC, model_m32rx_jnc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2917 { M32RXF_INSN_JL, model_m32rx_jl, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2918 { M32RXF_INSN_JMP, model_m32rx_jmp, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } }, 2919 { M32RXF_INSN_LD, model_m32rx_ld, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } }, 2920 { M32RXF_INSN_LD_D, model_m32rx_ld_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } }, 2921 { M32RXF_INSN_LDB, model_m32rx_ldb, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } }, 2922 { M32RXF_INSN_LDB_D, model_m32rx_ldb_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } }, 2923 { M32RXF_INSN_LDH, model_m32rx_ldh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } }, 2924 { M32RXF_INSN_LDH_D, model_m32rx_ldh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } }, 2925 { M32RXF_INSN_LDUB, model_m32rx_ldub, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } }, 2926 { M32RXF_INSN_LDUB_D, model_m32rx_ldub_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } }, 2927 { M32RXF_INSN_LDUH, model_m32rx_lduh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } }, 2928 { M32RXF_INSN_LDUH_D, model_m32rx_lduh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } }, 2929 { M32RXF_INSN_LD_PLUS, model_m32rx_ld_plus, { { (int) UNIT_M32RX_U_LOAD, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } }, 2930 { M32RXF_INSN_LD24, model_m32rx_ld24, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2931 { M32RXF_INSN_LDI8, model_m32rx_ldi8, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2932 { M32RXF_INSN_LDI16, model_m32rx_ldi16, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2933 { M32RXF_INSN_LOCK, model_m32rx_lock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } }, 2934 { M32RXF_INSN_MACHI_A, model_m32rx_machi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2935 { M32RXF_INSN_MACLO_A, model_m32rx_maclo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2936 { M32RXF_INSN_MACWHI_A, model_m32rx_macwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2937 { M32RXF_INSN_MACWLO_A, model_m32rx_macwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2938 { M32RXF_INSN_MUL, model_m32rx_mul, { { (int) UNIT_M32RX_U_EXEC, 1, 4 } } }, 2939 { M32RXF_INSN_MULHI_A, model_m32rx_mulhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2940 { M32RXF_INSN_MULLO_A, model_m32rx_mullo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2941 { M32RXF_INSN_MULWHI_A, model_m32rx_mulwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2942 { M32RXF_INSN_MULWLO_A, model_m32rx_mulwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2943 { M32RXF_INSN_MV, model_m32rx_mv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2944 { M32RXF_INSN_MVFACHI_A, model_m32rx_mvfachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } }, 2945 { M32RXF_INSN_MVFACLO_A, model_m32rx_mvfaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } }, 2946 { M32RXF_INSN_MVFACMI_A, model_m32rx_mvfacmi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } }, 2947 { M32RXF_INSN_MVFC, model_m32rx_mvfc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2948 { M32RXF_INSN_MVTACHI_A, model_m32rx_mvtachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2949 { M32RXF_INSN_MVTACLO_A, model_m32rx_mvtaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2950 { M32RXF_INSN_MVTC, model_m32rx_mvtc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2951 { M32RXF_INSN_NEG, model_m32rx_neg, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2952 { M32RXF_INSN_NOP, model_m32rx_nop, { { (int) UNIT_M32RX_U_EXEC, 1, 0 } } }, 2953 { M32RXF_INSN_NOT, model_m32rx_not, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2954 { M32RXF_INSN_RAC_DSI, model_m32rx_rac_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2955 { M32RXF_INSN_RACH_DSI, model_m32rx_rach_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2956 { M32RXF_INSN_RTE, model_m32rx_rte, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2957 { M32RXF_INSN_SETH, model_m32rx_seth, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2958 { M32RXF_INSN_SLL, model_m32rx_sll, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2959 { M32RXF_INSN_SLL3, model_m32rx_sll3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2960 { M32RXF_INSN_SLLI, model_m32rx_slli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2961 { M32RXF_INSN_SRA, model_m32rx_sra, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2962 { M32RXF_INSN_SRA3, model_m32rx_sra3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2963 { M32RXF_INSN_SRAI, model_m32rx_srai, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2964 { M32RXF_INSN_SRL, model_m32rx_srl, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2965 { M32RXF_INSN_SRL3, model_m32rx_srl3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2966 { M32RXF_INSN_SRLI, model_m32rx_srli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2967 { M32RXF_INSN_ST, model_m32rx_st, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } }, 2968 { M32RXF_INSN_ST_D, model_m32rx_st_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } }, 2969 { M32RXF_INSN_STB, model_m32rx_stb, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } }, 2970 { M32RXF_INSN_STB_D, model_m32rx_stb_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } }, 2971 { M32RXF_INSN_STH, model_m32rx_sth, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } }, 2972 { M32RXF_INSN_STH_D, model_m32rx_sth_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } }, 2973 { M32RXF_INSN_ST_PLUS, model_m32rx_st_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } }, 2974 { M32RXF_INSN_STH_PLUS, model_m32rx_sth_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } }, 2975 { M32RXF_INSN_STB_PLUS, model_m32rx_stb_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } }, 2976 { M32RXF_INSN_ST_MINUS, model_m32rx_st_minus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } }, 2977 { M32RXF_INSN_SUB, model_m32rx_sub, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2978 { M32RXF_INSN_SUBV, model_m32rx_subv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2979 { M32RXF_INSN_SUBX, model_m32rx_subx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2980 { M32RXF_INSN_TRAP, model_m32rx_trap, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2981 { M32RXF_INSN_UNLOCK, model_m32rx_unlock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } }, 2982 { M32RXF_INSN_SATB, model_m32rx_satb, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2983 { M32RXF_INSN_SATH, model_m32rx_sath, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2984 { M32RXF_INSN_SAT, model_m32rx_sat, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2985 { M32RXF_INSN_PCMPBZ, model_m32rx_pcmpbz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } }, 2986 { M32RXF_INSN_SADD, model_m32rx_sadd, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2987 { M32RXF_INSN_MACWU1, model_m32rx_macwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2988 { M32RXF_INSN_MSBLO, model_m32rx_msblo, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2989 { M32RXF_INSN_MULWU1, model_m32rx_mulwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2990 { M32RXF_INSN_MACLH1, model_m32rx_maclh1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } }, 2991 { M32RXF_INSN_SC, model_m32rx_sc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2992 { M32RXF_INSN_SNC, model_m32rx_snc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2993 { M32RXF_INSN_CLRPSW, model_m32rx_clrpsw, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2994 { M32RXF_INSN_SETPSW, model_m32rx_setpsw, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2995 { M32RXF_INSN_BSET, model_m32rx_bset, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2996 { M32RXF_INSN_BCLR, model_m32rx_bclr, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2997 { M32RXF_INSN_BTST, model_m32rx_btst, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } }, 2998 }; 2999 3000 #endif /* WITH_PROFILE_MODEL_P */ 3001 3002 static void 3003 m32rx_model_init (SIM_CPU *cpu) 3004 { 3005 CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32RX_DATA)); 3006 } 3007 3008 #if WITH_PROFILE_MODEL_P 3009 #define TIMING_DATA(td) td 3010 #else 3011 #define TIMING_DATA(td) 0 3012 #endif 3013 3014 static const SIM_MODEL m32rx_models[] = 3015 { 3016 { "m32rx", & m32rx_mach, MODEL_M32RX, TIMING_DATA (& m32rx_timing[0]), m32rx_model_init }, 3017 { 0 } 3018 }; 3019 3020 /* The properties of this cpu's implementation. */ 3021 3022 static const SIM_MACH_IMP_PROPERTIES m32rxf_imp_properties = 3023 { 3024 sizeof (SIM_CPU), 3025 #if WITH_SCACHE 3026 sizeof (SCACHE) 3027 #else 3028 0 3029 #endif 3030 }; 3031 3032 3033 static void 3034 m32rxf_prepare_run (SIM_CPU *cpu) 3035 { 3036 if (CPU_IDESC (cpu) == NULL) 3037 m32rxf_init_idesc_table (cpu); 3038 } 3039 3040 static const CGEN_INSN * 3041 m32rxf_get_idata (SIM_CPU *cpu, int inum) 3042 { 3043 return CPU_IDESC (cpu) [inum].idata; 3044 } 3045 3046 static void 3047 m32rx_init_cpu (SIM_CPU *cpu) 3048 { 3049 CPU_REG_FETCH (cpu) = m32rxf_fetch_register; 3050 CPU_REG_STORE (cpu) = m32rxf_store_register; 3051 CPU_PC_FETCH (cpu) = m32rxf_h_pc_get; 3052 CPU_PC_STORE (cpu) = m32rxf_h_pc_set; 3053 CPU_GET_IDATA (cpu) = m32rxf_get_idata; 3054 CPU_MAX_INSNS (cpu) = M32RXF_INSN__MAX; 3055 CPU_INSN_NAME (cpu) = cgen_insn_name; 3056 CPU_FULL_ENGINE_FN (cpu) = m32rxf_engine_run_full; 3057 #if WITH_FAST 3058 CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_fast; 3059 #else 3060 CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_full; 3061 #endif 3062 } 3063 3064 const SIM_MACH m32rx_mach = 3065 { 3066 "m32rx", "m32rx", MACH_M32RX, 3067 32, 32, & m32rx_models[0], & m32rxf_imp_properties, 3068 m32rx_init_cpu, 3069 m32rxf_prepare_run 3070 }; 3071 3072
Indexes created Mon Mar 02 05:31:46 UTC 2026