Lines Matching refs:uint64_t
91 uint64_t paltemp[32]; /* PAL TEMP REGS. */
92 uint64_t exc_addr; /* Address of excepting ins. */
93 uint64_t exc_sum; /* Summary of arithmetic traps. */
94 uint64_t exc_mask; /* Exception mask. */
95 uint64_t iccsr;
96 uint64_t pal_base; /* Base address for PALcode. */
97 uint64_t hier;
98 uint64_t hirr;
99 uint64_t mm_csr;
100 uint64_t dc_stat;
101 uint64_t dc_addr;
102 uint64_t abox_ctl;
103 uint64_t biu_stat; /* Bus Interface Unit Status. */
104 uint64_t biu_addr;
105 uint64_t biu_ctl;
106 uint64_t fill_syndrome;
107 uint64_t fill_addr;
108 uint64_t va;
109 uint64_t bc_tag;
112 uint64_t coma_gcr; /* Error and Diag. Status. */
113 uint64_t coma_edsr;
114 uint64_t coma_ter;
115 uint64_t coma_elar;
116 uint64_t coma_ehar;
117 uint64_t coma_ldlr;
118 uint64_t coma_ldhr;
119 uint64_t coma_base0;
120 uint64_t coma_base1;
121 uint64_t coma_base2;
122 uint64_t coma_cnfg0;
123 uint64_t coma_cnfg1;
124 uint64_t coma_cnfg2;
127 uint64_t epic_dcsr; /* Diag. Control and Status. */
128 uint64_t epic_pear;
129 uint64_t epic_sear;
130 uint64_t epic_tbr1;
131 uint64_t epic_tbr2;
132 uint64_t epic_pbr1;
133 uint64_t epic_pbr2;
134 uint64_t epic_pmr1;
135 uint64_t epic_pmr2;
136 uint64_t epic_harx1;
137 uint64_t epic_harx2;
138 uint64_t epic_pmlt;
139 uint64_t epic_tag0;
140 uint64_t epic_tag1;
141 uint64_t epic_tag2;
142 uint64_t epic_tag3;
143 uint64_t epic_tag4;
144 uint64_t epic_tag5;
145 uint64_t epic_tag6;
146 uint64_t epic_tag7;
147 uint64_t epic_data0;
148 uint64_t epic_data1;
149 uint64_t epic_data2;
150 uint64_t epic_data3;
151 uint64_t epic_data4;
152 uint64_t epic_data5;
153 uint64_t epic_data6;
154 uint64_t epic_data7;
192 uint64_t shadow[8]; /* Shadow reg. 8-14, 25 */
193 uint64_t paltemp[24]; /* PAL TEMP REGS. */
194 uint64_t exc_addr; /* Address of excepting ins. */
195 uint64_t exc_sum; /* Summary of arithmetic traps. */
196 uint64_t exc_mask; /* Exception mask. */
197 uint64_t pal_base; /* Base address for PALcode. */
198 uint64_t isr; /* Interrupt Status Reg. */
199 uint64_t icsr; /* CURRENT SETUP OF EV5 IBOX */
200 uint64_t ic_perr_stat; /*
206 uint64_t dc_perr_stat; /* D-CACHE error Reg:
213 uint64_t va; /* Effective VA of fault or miss. */
214 uint64_t mm_stat; /*
218 uint64_t sc_addr; /*
223 uint64_t sc_stat; /*
227 uint64_t bc_tag_addr; /* Contents of EV5 BC_TAG_ADDR */
228 uint64_t ei_addr; /*
232 uint64_t fill_syndrome; /* For correcting ECC errors. */
233 uint64_t ei_stat; /*
238 uint64_t ld_lock; /* Contents of EV5 LD_LOCK register*/
248 uint64_t ei_addr; /*
252 uint64_t fill_syndrome; /* For correcting ECC errors. */
253 uint64_t ei_stat; /*
258 uint64_t isr; /* Interrupt Status Reg. */
278 uint64_t i_stat;
279 uint64_t dc_stat;
280 uint64_t c_addr;
281 uint64_t c_syndrome1;
282 uint64_t c_syndrome0;
283 uint64_t c_stat;
284 uint64_t c_sts;
285 uint64_t mm_stat;
286 uint64_t exc_addr;
287 uint64_t ier_cm;
288 uint64_t isum;
289 uint64_t _r;
290 uint64_t pal_base;
291 uint64_t i_ctl;
292 uint64_t pctx;
296 uint64_t flags;
297 uint64_t dir;
298 uint64_t misc;
299 uint64_t p0_error;
300 uint64_t p1_error;
Indexes created Mon Oct 13 21:09:55 GMT 2025