Lines Matching refs:REG
50 #define REG 0x00
168 .reg = CBUS_REG((_gpiobase) + 0), \
173 .reg = CBUS_REG((_gpiobase) + 1), \
178 .reg = CBUS_REG((_gpiobase) + 2), \
183 .reg = CBUS_REG(_pullbase), \
188 .reg = CBUS_REG(_pullbase), \
284 .reg = 0, \
289 .reg = 0, \
294 .reg = 4, \
299 .reg = 0, \
304 .reg = 0, \
491 { "uart_tx_ao_a", REG, 12, { GPIOAO_0 }, 1 },
492 { "uart_rx_ao_a", REG, 11, { GPIOAO_1 }, 1 },
493 { "uart_cts_ao_a", REG, 10, { GPIOAO_2 }, 1 },
494 { "uart_rts_ao_a", REG, 9, { GPIOAO_3 }, 1 },
495 { "i2c_mst_sck_ao", REG, 6, { GPIOAO_4 }, 1 },
496 { "i2c_mst_sda_ao", REG, 5, { GPIOAO_5 }, 1 },
497 { "clk_32k_in_out", REG, 18, { GPIOAO_6 }, 1 },
498 { "remote_input", REG, 0, { GPIOAO_7 }, 1 },
499 { "hdmi_cec_1", REG, 17, { GPIOAO_12 }, 1 },
500 { "ir_blaster", REG, 31, { GPIOAO_13 }, 1 },
501 { "pwm_c2", REG, 22, { GPIOAO_3 }, 1 },
502 { "i2c_sck_ao", REG, 2, { GPIOAO_4 }, 1 },
503 { "i2c_sda_ao", REG, 1, { GPIOAO_5 }, 1 },
504 { "ir_remote_out", REG, 21, { GPIOAO_7 }, 1 },
505 { "i2s_am_clk_out", REG, 30, { GPIOAO_8 }, 1 },
506 { "i2s_ao_clk_out", REG, 29, { GPIOAO_9 }, 1 },
507 { "i2s_lr_clk_out", REG, 28, { GPIOAO_10 }, 1 },
508 { "i2s_out_01", REG, 27, { GPIOAO_11 }, 1 },
509 { "uart_tx_ao_b0", REG, 26, { GPIOAO_0 }, 1 },
510 { "uart_rx_ao_b0", REG, 25, { GPIOAO_1 }, 1 },
511 { "uart_cts_ao_b", REG, 8, { GPIOAO_2 }, 1 },
512 { "uart_rts_ao_b", REG, 7, { GPIOAO_3 }, 1 },
513 { "uart_tx_ao_b1", REG, 24, { GPIOAO_4 }, 1 },
514 { "uart_rx_ao_b1", REG, 23, { GPIOAO_5 }, 1 },
515 { "spdif_out_1", REG, 16, { GPIOAO_6 }, 1 },
516 { "i2s_in_ch01", REG, 13, { GPIOAO_6 }, 1 },
517 { "i2s_ao_clk_in", REG, 15, { GPIOAO_9 }, 1 },
518 { "i2s_lr_clk_in", REG, 14, { GPIOAO_10 }, 1 },
Indexes created Sun Oct 19 02:09:48 GMT 2025