1 /* $NetBSD: meson8b_pinctrl.c,v 1.3 2022/06/23 03:36:00 brook Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: meson8b_pinctrl.c,v 1.3 2022/06/23 03:36:00 brook Exp $"); 31 32 #include <sys/param.h> 33 34 #include <arm/amlogic/meson_pinctrl.h> 35 36 /* CBUS pinmux registers */ 37 #define CBUS_REG(n) ((n) << 2) 38 #define REG0 CBUS_REG(0) 39 #define REG1 CBUS_REG(1) 40 #define REG2 CBUS_REG(2) 41 #define REG3 CBUS_REG(3) 42 #define REG4 CBUS_REG(4) 43 #define REG5 CBUS_REG(5) 44 #define REG6 CBUS_REG(6) 45 #define REG7 CBUS_REG(7) 46 #define REG8 CBUS_REG(8) 47 #define REG9 CBUS_REG(9) 48 49 /* AO pinmux registers */ 50 #define REG 0x00 51 52 /* 53 * GPIO banks. The values must match those in dt-bindings/gpio/meson8b-gpio.h 54 */ 55 enum { 56 GPIOX_0 = 0, 57 GPIOX_1, 58 GPIOX_2, 59 GPIOX_3, 60 GPIOX_4, 61 GPIOX_5, 62 GPIOX_6, 63 GPIOX_7, 64 GPIOX_8, 65 GPIOX_9, 66 GPIOX_10, 67 GPIOX_11, 68 GPIOX_16, 69 GPIOX_17, 70 GPIOX_18, 71 GPIOX_19, 72 GPIOX_20, 73 GPIOX_21, 74 75 GPIOY_0 = 18, 76 GPIOY_1, 77 GPIOY_3, 78 GPIOY_6, 79 GPIOY_7, 80 GPIOY_8, 81 GPIOY_9, 82 GPIOY_10, 83 GPIOY_11, 84 GPIOY_12, 85 GPIOY_13, 86 GPIOY_14, 87 88 GPIODV_9 = 30, 89 GPIODV_24, 90 GPIODV_25, 91 GPIODV_26, 92 GPIODV_27, 93 GPIODV_28, 94 GPIODV_29, 95 96 GPIOH_0 = 37, 97 GPIOH_1, 98 GPIOH_2, 99 GPIOH_3, 100 GPIOH_4, 101 GPIOH_5, 102 GPIOH_6, 103 GPIOH_7, 104 GPIOH_8, 105 GPIOH_9, 106 107 CARD_0 = 47, 108 CARD_1, 109 CARD_2, 110 CARD_3, 111 CARD_4, 112 CARD_5, 113 CARD_6, 114 115 BOOT_0 = 54, 116 BOOT_1, 117 BOOT_2, 118 BOOT_3, 119 BOOT_4, 120 BOOT_5, 121 BOOT_6, 122 BOOT_7, 123 BOOT_8, 124 BOOT_9, 125 BOOT_10, 126 BOOT_11, 127 BOOT_12, 128 BOOT_13, 129 BOOT_14, 130 BOOT_15, 131 BOOT_18, 132 133 DIF_0_P = 73, 134 DIF_0_N, 135 DIF_1_P, 136 DIF_1_N, 137 DIF_2_P, 138 DIF_2_N, 139 DIF_3_P, 140 DIF_3_N, 141 DIF_4_P, 142 DIF_4_N, 143 144 GPIOAO_0 = 0, 145 GPIOAO_1, 146 GPIOAO_2, 147 GPIOAO_3, 148 GPIOAO_4, 149 GPIOAO_5, 150 GPIOAO_6, 151 GPIOAO_7, 152 GPIOAO_8, 153 GPIOAO_9, 154 GPIOAO_10, 155 GPIOAO_11, 156 GPIOAO_12, 157 GPIOAO_13, 158 GPIO_BSD_EN, 159 GPIO_TEST_N, 160 }; 161 162 #define CBUS_GPIO(_id, _gpiobase, _gpiobit, _pullbase, _pullbit) \ 163 [_id] = { \ 164 .id = (_id), \ 165 .name = __STRING(_id), \ 166 .oen = { \ 167 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 168 .reg = CBUS_REG((_gpiobase) + 0), \ 169 .mask = __BIT(_gpiobit) \ 170 }, \ 171 .out = { \ 172 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 173 .reg = CBUS_REG((_gpiobase) + 1), \ 174 .mask = __BIT(_gpiobit) \ 175 }, \ 176 .in = { \ 177 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 178 .reg = CBUS_REG((_gpiobase) + 2), \ 179 .mask = __BIT(_gpiobit) \ 180 }, \ 181 .pupden = { \ 182 .type = MESON_PINCTRL_REGTYPE_PULL_ENABLE, \ 183 .reg = CBUS_REG(_pullbase), \ 184 .mask = __BIT(_pullbit) \ 185 }, \ 186 .pupd = { \ 187 .type = MESON_PINCTRL_REGTYPE_PULL, \ 188 .reg = CBUS_REG(_pullbase), \ 189 .mask = __BIT(_pullbit) \ 190 }, \ 191 } 192 193 static const struct meson_pinctrl_gpio meson8b_cbus_gpios[] = { 194 /* GPIOX */ 195 CBUS_GPIO(GPIOX_0, 0, 0, 4, 0), 196 CBUS_GPIO(GPIOX_1, 0, 1, 4, 1), 197 CBUS_GPIO(GPIOX_2, 0, 2, 4, 2), 198 CBUS_GPIO(GPIOX_3, 0, 3, 4, 3), 199 CBUS_GPIO(GPIOX_4, 0, 4, 4, 4), 200 CBUS_GPIO(GPIOX_5, 0, 5, 4, 5), 201 CBUS_GPIO(GPIOX_6, 0, 6, 4, 6), 202 CBUS_GPIO(GPIOX_7, 0, 7, 4, 7), 203 CBUS_GPIO(GPIOX_8, 0, 8, 4, 8), 204 CBUS_GPIO(GPIOX_9, 0, 9, 4, 9), 205 CBUS_GPIO(GPIOX_10, 0, 10, 4, 10), 206 CBUS_GPIO(GPIOX_11, 0, 11, 4, 11), 207 CBUS_GPIO(GPIOX_16, 0, 16, 4, 16), 208 CBUS_GPIO(GPIOX_17, 0, 17, 4, 17), 209 CBUS_GPIO(GPIOX_18, 0, 18, 4, 18), 210 CBUS_GPIO(GPIOX_19, 0, 19, 4, 19), 211 CBUS_GPIO(GPIOX_20, 0, 20, 4, 20), 212 CBUS_GPIO(GPIOX_21, 0, 21, 4, 21), 213 214 /* GPIOY */ 215 CBUS_GPIO(GPIOY_0, 3, 0, 3, 0), 216 CBUS_GPIO(GPIOY_1, 3, 1, 3, 1), 217 CBUS_GPIO(GPIOY_3, 3, 3, 3, 3), 218 CBUS_GPIO(GPIOY_6, 3, 6, 3, 6), 219 CBUS_GPIO(GPIOY_7, 3, 7, 3, 7), 220 CBUS_GPIO(GPIOY_8, 3, 8, 3, 8), 221 CBUS_GPIO(GPIOY_9, 3, 9, 3, 9), 222 CBUS_GPIO(GPIOY_10, 3, 10, 3, 10), 223 CBUS_GPIO(GPIOY_11, 3, 11, 3, 11), 224 CBUS_GPIO(GPIOY_12, 3, 12, 3, 12), 225 CBUS_GPIO(GPIOY_13, 3, 13, 3, 13), 226 CBUS_GPIO(GPIOY_14, 3, 14, 3, 14), 227 228 /* GPIODV */ 229 CBUS_GPIO(GPIODV_9, 6, 9, 0, 9), 230 CBUS_GPIO(GPIODV_24, 6, 24, 0, 24), 231 CBUS_GPIO(GPIODV_25, 6, 25, 0, 25), 232 CBUS_GPIO(GPIODV_26, 6, 26, 0, 26), 233 CBUS_GPIO(GPIODV_27, 6, 27, 0, 27), 234 CBUS_GPIO(GPIODV_28, 6, 28, 0, 28), 235 CBUS_GPIO(GPIODV_29, 6, 29, 0, 29), 236 237 /* GPIOH */ 238 CBUS_GPIO(GPIOH_0, 9, 19, 1, 16), 239 CBUS_GPIO(GPIOH_1, 9, 20, 1, 17), 240 CBUS_GPIO(GPIOH_2, 9, 21, 1, 18), 241 CBUS_GPIO(GPIOH_3, 9, 22, 1, 19), 242 CBUS_GPIO(GPIOH_4, 9, 23, 1, 20), 243 CBUS_GPIO(GPIOH_5, 9, 24, 1, 21), 244 CBUS_GPIO(GPIOH_6, 9, 25, 1, 22), 245 CBUS_GPIO(GPIOH_7, 9, 26, 1, 23), 246 CBUS_GPIO(GPIOH_8, 9, 27, 1, 24), 247 CBUS_GPIO(GPIOH_9, 9, 28, 1, 25), 248 249 /* BOOT */ 250 CBUS_GPIO(BOOT_0, 9, 0, 2, 0), 251 CBUS_GPIO(BOOT_1, 9, 1, 2, 1), 252 CBUS_GPIO(BOOT_2, 9, 2, 2, 2), 253 CBUS_GPIO(BOOT_3, 9, 3, 2, 3), 254 CBUS_GPIO(BOOT_4, 9, 4, 2, 4), 255 CBUS_GPIO(BOOT_5, 9, 5, 2, 5), 256 CBUS_GPIO(BOOT_6, 9, 6, 2, 6), 257 CBUS_GPIO(BOOT_7, 9, 7, 2, 7), 258 CBUS_GPIO(BOOT_8, 9, 8, 2, 8), 259 CBUS_GPIO(BOOT_9, 9, 9, 2, 9), 260 CBUS_GPIO(BOOT_10, 9, 10, 2, 10), 261 CBUS_GPIO(BOOT_11, 9, 11, 2, 11), 262 CBUS_GPIO(BOOT_12, 9, 12, 2, 12), 263 CBUS_GPIO(BOOT_13, 9, 13, 2, 13), 264 CBUS_GPIO(BOOT_14, 9, 14, 2, 14), 265 CBUS_GPIO(BOOT_15, 9, 15, 2, 15), 266 CBUS_GPIO(BOOT_18, 9, 18, 2, 18), 267 268 /* CARD */ 269 CBUS_GPIO(CARD_0, 0, 22, 2, 20), 270 CBUS_GPIO(CARD_1, 0, 23, 2, 21), 271 CBUS_GPIO(CARD_2, 0, 24, 2, 22), 272 CBUS_GPIO(CARD_3, 0, 25, 2, 23), 273 CBUS_GPIO(CARD_4, 0, 26, 2, 24), 274 CBUS_GPIO(CARD_5, 0, 27, 2, 25), 275 CBUS_GPIO(CARD_6, 0, 28, 2, 26), 276 }; 277 278 #define AO_GPIO(_id, _bit) \ 279 [_id] = { \ 280 .id = (_id), \ 281 .name = __STRING(_id), \ 282 .oen = { \ 283 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 284 .reg = 0, \ 285 .mask = __BIT(_bit) \ 286 }, \ 287 .out = { \ 288 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 289 .reg = 0, \ 290 .mask = __BIT(_bit + 16) \ 291 }, \ 292 .in = { \ 293 .type = MESON_PINCTRL_REGTYPE_GPIO, \ 294 .reg = 4, \ 295 .mask = __BIT(_bit) \ 296 }, \ 297 .pupden = { \ 298 .type = MESON_PINCTRL_REGTYPE_PULL, \ 299 .reg = 0, \ 300 .mask = __BIT(_bit) \ 301 }, \ 302 .pupd = { \ 303 .type = MESON_PINCTRL_REGTYPE_PULL, \ 304 .reg = 0, \ 305 .mask = __BIT(_bit + 16) \ 306 }, \ 307 } 308 309 static const struct meson_pinctrl_gpio meson8b_aobus_gpios[] = { 310 /* GPIOAO */ 311 AO_GPIO(GPIOAO_0, 0), 312 AO_GPIO(GPIOAO_1, 1), 313 AO_GPIO(GPIOAO_2, 2), 314 AO_GPIO(GPIOAO_3, 3), 315 AO_GPIO(GPIOAO_4, 4), 316 AO_GPIO(GPIOAO_5, 5), 317 AO_GPIO(GPIOAO_6, 6), 318 AO_GPIO(GPIOAO_7, 7), 319 AO_GPIO(GPIOAO_8, 8), 320 AO_GPIO(GPIOAO_9, 9), 321 AO_GPIO(GPIOAO_10, 10), 322 AO_GPIO(GPIOAO_11, 11), 323 AO_GPIO(GPIOAO_12, 12), 324 AO_GPIO(GPIOAO_13, 13), 325 }; 326 327 static const struct meson_pinctrl_group meson8b_cbus_groups[] = { 328 /* GPIOX */ 329 { "sd_d0_a", REG8, 5, { GPIOX_0 }, 1 }, 330 { "sd_d1_a", REG8, 4, { GPIOX_1 }, 1 }, 331 { "sd_d2_a", REG8, 3, { GPIOX_2 }, 1 }, 332 { "sd_d3_a", REG8, 2, { GPIOX_3 }, 1 }, 333 { "sdxc_d0_0_a", REG5, 29, { GPIOX_4 }, 1 }, 334 { "sdxc_d47_a", REG5, 12, { GPIOX_4, GPIOX_5, GPIOX_6, GPIOX_7 }, 4 }, 335 { "sdxc_d13_0_a", REG5, 28, { GPIOX_5, GPIOX_6, GPIOX_7 }, 3 }, 336 { "sd_clk_a", REG8, 1, { GPIOX_8 }, 1 }, 337 { "sd_cmd_a", REG8, 0, { GPIOX_9 }, 1 }, 338 { "xtal_32k_out", REG3, 22, { GPIOX_10 }, 1 }, 339 { "xtal_24m_out", REG3, 20, { GPIOX_11 }, 1 }, 340 { "uart_tx_b0", REG4, 9, { GPIOX_16 }, 1 }, 341 { "uart_rx_b0", REG4, 8, { GPIOX_17 }, 1 }, 342 { "uart_cts_b0", REG4, 7, { GPIOX_18 }, 1 }, 343 { "uart_rts_b0", REG4, 6, { GPIOX_19 }, 1 }, 344 { "sdxc_d0_1_a", REG5, 14, { GPIOX_0 }, 1 }, 345 { "sdxc_d13_1_a", REG5, 13, { GPIOX_1, GPIOX_2, GPIOX_3 }, 3 }, 346 { "pcm_out_a", REG3, 30, { GPIOX_4 }, 1 }, 347 { "pcm_in_a", REG3, 29, { GPIOX_5 }, 1 }, 348 { "pcm_fs_a", REG3, 28, { GPIOX_6 }, 1 }, 349 { "pcm_clk_a", REG3, 27, { GPIOX_7 }, 1 }, 350 { "sdxc_clk_a", REG5, 11, { GPIOX_8 }, 1 }, 351 { "sdxc_cmd_a", REG5, 10, { GPIOX_9 }, 1 }, 352 { "pwm_vs_0", REG7, 31, { GPIOX_10 }, 1 }, 353 { "pwm_e", REG9, 19, { GPIOX_10 }, 1 }, 354 { "pwm_vs_1", REG7, 30, { GPIOX_11 }, 1 }, 355 { "uart_tx_a", REG4, 17, { GPIOX_4 }, 1 }, 356 { "uart_rx_a", REG4, 16, { GPIOX_5 }, 1 }, 357 { "uart_cts_a", REG4, 15, { GPIOX_6 }, 1 }, 358 { "uart_rts_a", REG4, 14, { GPIOX_7 }, 1 }, 359 { "uart_tx_b1", REG6, 19, { GPIOX_8 }, 1 }, 360 { "uart_rx_b1", REG6, 18, { GPIOX_9 }, 1 }, 361 { "uart_cts_b1", REG6, 17, { GPIOX_10 }, 1 }, 362 { "uart_rts_b1", REG6, 16, { GPIOX_20 }, 1 }, 363 { "iso7816_0_clk", REG5, 9, { GPIOX_6 }, 1 }, 364 { "iso7816_0_data", REG5, 8, { GPIOX_7 }, 1 }, 365 { "spi_sclk_0", REG4, 22, { GPIOX_8 }, 1 }, 366 { "spi_miso_0", REG4, 24, { GPIOX_9 }, 1 }, 367 { "spi_mosi_0", REG4, 23, { GPIOX_10 }, 1 }, 368 { "iso7816_det", REG4, 21, { GPIOX_16 }, 1 }, 369 { "iso7816_reset", REG4, 20, { GPIOX_17 }, 1 }, 370 { "iso7816_1_clk", REG4, 19, { GPIOX_18 }, 1 }, 371 { "iso7816_1_data", REG4, 18, { GPIOX_19 }, 1 }, 372 { "spi_ss0_0", REG4, 25, { GPIOX_20 }, 1 }, 373 { "tsin_clk_b", REG3, 6, { GPIOX_8 }, 1 }, 374 { "tsin_sop_b", REG3, 7, { GPIOX_9 }, 1 }, 375 { "tsin_d0_b", REG3, 8, { GPIOX_10 }, 1 }, 376 { "pwm_b", REG2, 3, { GPIOX_11 }, 1 }, 377 { "i2c_sda_d0", REG4, 5, { GPIOX_16 }, 1 }, 378 { "i2c_sck_d0", REG4, 4, { GPIOX_17 }, 1 }, 379 { "tsin_d_valid_b", REG3, 9, { GPIOX_20 }, 1 }, 380 381 /* GPIOY */ 382 { "tsin_d_valid_a", REG3, 2, { GPIOY_0 }, 1}, 383 { "tsin_sop_a", REG3, 1, { GPIOY_1 }, 1 }, 384 { "tsin_d17_a", REG3, 5, { GPIOY_6, GPIOY_7, GPIOY_10, GPIOY_11, GPIOY_12, GPIOY_13, GPIOY_14 }, 8 }, 385 { "tsin_clk_a", REG3, 0, { GPIOY_8 }, 1 }, 386 { "tsin_d0_a", REG3, 4, { GPIOY_9 }, 1 }, 387 { "spdif_out_0", REG1, 7, { GPIOY_3 }, 1 }, 388 { "xtal_24m", REG3, 18, { GPIOY_3 }, 1 }, 389 { "iso7816_2_clk", REG5, 7, { GPIOY_13 }, 1 }, 390 { "iso7816_2_data", REG5, 6, { GPIOY_14 }, 1 }, 391 392 /* GPIODV */ 393 { "pwm_d", REG3, 26, { GPIODV_28 }, 1 }, 394 { "pwm_c0", REG3, 25, { GPIODV_29 }, 1 }, 395 { "pwm_vs_2", REG7, 28, { GPIODV_9 }, 1 }, 396 { "pwm_vs_3", REG7, 27, { GPIODV_28 }, 1 }, 397 { "pwm_vs_4", REG7, 26, { GPIODV_29 }, 1 }, 398 { "xtal24_out", REG7, 25, { GPIODV_29 }, 1 }, 399 { "uart_tx_c", REG6, 23, { GPIODV_24 }, 1 }, 400 { "uart_rx_c", REG6, 22, { GPIODV_25 }, 1 }, 401 { "uart_cts_c", REG6, 21, { GPIODV_26 }, 1 }, 402 { "uart_rts_c", REG6, 20, { GPIODV_27 }, 1 }, 403 { "pwm_c1", REG3, 24, { GPIODV_9 }, 1 }, 404 { "i2c_sda_a", REG9, 31, { GPIODV_24 }, 1 }, 405 { "i2c_sck_a", REG9, 30, { GPIODV_25 }, 1 }, 406 { "i2c_sda_b0", REG9, 29, { GPIODV_26 }, 1 }, 407 { "i2c_sck_b0", REG9, 28, { GPIODV_27 }, 1 }, 408 { "i2c_sda_c0", REG9, 27, { GPIODV_28 }, 1 }, 409 { "i2c_sck_c0", REG9, 26, { GPIODV_29 }, 1 }, 410 411 /* GPIOH */ 412 { "hdmi_hpd", REG1, 26, { GPIOH_0 }, 1 }, 413 { "hdmi_sda", REG1, 25, { GPIOH_1 }, 1 }, 414 { "hdmi_scl", REG1, 24, { GPIOH_2 }, 1 }, 415 { "hdmi_cec_0", REG1, 23, { GPIOH_3 }, 1 }, 416 { "eth_txd1_0", REG7, 21, { GPIOH_5 }, 1 }, 417 { "eth_txd0_0", REG7, 20, { GPIOH_6 }, 1 }, 418 { "clk_24m_out", REG4, 1, { GPIOH_9 }, 1 }, 419 { "spi_ss1", REG8, 11, { GPIOH_0 }, 1 }, 420 { "spi_ss2", REG8, 12, { GPIOH_1 }, 1 }, 421 { "spi_ss0_1", REG9, 13, { GPIOH_3 }, 1 }, 422 { "spi_miso_1", REG9, 12, { GPIOH_4 }, 1 }, 423 { "spi_mosi_1", REG9, 11, { GPIOH_5 }, 1 }, 424 { "spi_sclk_1", REG9, 10, { GPIOH_6 }, 1 }, 425 { "eth_txd3", REG6, 13, { GPIOH_7 }, 1 }, 426 { "eth_txd2", REG6, 12, { GPIOH_8 }, 1 }, 427 { "eth_tx_clk", REG6, 11, { GPIOH_9 }, 1 }, 428 { "i2c_sda_b1", REG5, 27, { GPIOH_3 }, 1 }, 429 { "i2c_sck_b1", REG5, 26, { GPIOH_4 }, 1 }, 430 { "i2c_sda_c1", REG5, 25, { GPIOH_5 }, 1 }, 431 { "i2c_sck_c1", REG5, 24, { GPIOH_6 }, 1 }, 432 { "i2c_sda_d1", REG4, 3, { GPIOH_7 }, 1 }, 433 { "i2c_sck_d1", REG4, 2, { GPIOH_8 }, 1 }, 434 435 /* BOOT */ 436 { "nand_io", REG2, 26, { BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7 }, 8 }, 437 { "nand_io_ce0", REG2, 25, { BOOT_8 }, 1 }, 438 { "nand_io_ce1", REG2, 24, { BOOT_9 }, 1 }, 439 { "nand_io_rb0", REG2, 17, { BOOT_10 }, 1 }, 440 { "nand_ale", REG2, 21, { BOOT_11 }, 1 }, 441 { "nand_cle", REG2, 20, { BOOT_12 }, 1 }, 442 { "nand_wen_clk", REG2, 19, { BOOT_13 }, 1 }, 443 { "nand_ren_clk", REG2, 18, { BOOT_14 }, 1 }, 444 { "nand_dqs_15", REG2, 27, { BOOT_15 }, 1 }, 445 { "nand_dqs_18", REG2, 28, { BOOT_18 }, 1 }, 446 { "sdxc_d0_c", REG4, 30, { BOOT_0 }, 1 }, 447 { "sdxc_d13_c", REG4, 29, { BOOT_1, BOOT_2, BOOT_3 }, 3 }, 448 { "sdxc_d47_c", REG4, 28, { BOOT_4, BOOT_5, BOOT_6, BOOT_7 }, 4 }, 449 { "sdxc_clk_c", REG7, 19, { BOOT_8 }, 1 }, 450 { "sdxc_cmd_c", REG7, 18, { BOOT_10 }, 1 }, 451 { "nor_d", REG5, 1, { BOOT_11 }, 1 }, 452 { "nor_q", REG5, 3, { BOOT_12 }, 1 }, 453 { "nor_c", REG5, 2, { BOOT_13 }, 1 }, 454 { "nor_cs", REG5, 0, { BOOT_18 }, 1 }, 455 { "sd_d0_c", REG6, 29, { BOOT_0 }, 1 }, 456 { "sd_d1_c", REG6, 28, { BOOT_1 }, 1 }, 457 { "sd_d2_c", REG6, 27, { BOOT_2 }, 1 }, 458 { "sd_d3_c", REG6, 26, { BOOT_3 }, 1 }, 459 { "sd_cmd_c", REG6, 30, { BOOT_8 }, 1 }, 460 { "sd_clk_c", REG6, 31, { BOOT_10 }, 1 }, 461 462 /* CARD */ 463 { "sd_d1_b", REG2, 14, { CARD_0 }, 1 }, 464 { "sd_d0_b", REG2, 15, { CARD_1 }, 1 }, 465 { "sd_clk_b", REG2, 11, { CARD_2 }, 1 }, 466 { "sd_cmd_b", REG2, 10, { CARD_3 }, 1 }, 467 { "sd_d3_b", REG2, 12, { CARD_4 }, 1 }, 468 { "sd_d2_b", REG2, 13, { CARD_5 }, 1 }, 469 { "sdxc_d13_b", REG2, 6, { CARD_0, CARD_4, CARD_5 }, 3 }, 470 { "sdxc_d0_b", REG2, 7, { CARD_1 }, 1 }, 471 { "sdxc_clk_b", REG2, 5, { CARD_2 }, 1 }, 472 { "sdxc_cmd_b", REG2, 4, { CARD_3 }, 1 }, 473 474 /* DIF */ 475 { "eth_rxd1", REG6, 0, { DIF_0_P }, 1 }, 476 { "eth_rxd0", REG6, 1, { DIF_0_N }, 1 }, 477 { "eth_rx_dv", REG6, 2, { DIF_1_P }, 1 }, 478 { "eth_rx_clk", REG6, 3, { DIF_1_N }, 1 }, 479 { "eth_txd0_1", REG6, 4, { DIF_2_P }, 1 }, 480 { "eth_txd1_1", REG6, 5, { DIF_2_N }, 1 }, 481 { "eth_tx_en", REG6, 6, { DIF_3_P }, 1 }, 482 { "eth_ref_clk", REG6, 8, { DIF_3_N }, 1 }, 483 { "eth_mdc", REG6, 9, { DIF_4_P }, 1 }, 484 { "eth_mdio_en", REG6, 10, { DIF_4_N }, 1 }, 485 { "eth_rxd3", REG7, 22, { DIF_2_P }, 1 }, 486 { "eth_rxd2", REG7, 23, { DIF_2_N }, 1 }, 487 }; 488 489 static const struct meson_pinctrl_group meson8b_aobus_groups[] = { 490 /* GPIOAO */ 491 { "uart_tx_ao_a", REG, 12, { GPIOAO_0 }, 1 }, 492 { "uart_rx_ao_a", REG, 11, { GPIOAO_1 }, 1 }, 493 { "uart_cts_ao_a", REG, 10, { GPIOAO_2 }, 1 }, 494 { "uart_rts_ao_a", REG, 9, { GPIOAO_3 }, 1 }, 495 { "i2c_mst_sck_ao", REG, 6, { GPIOAO_4 }, 1 }, 496 { "i2c_mst_sda_ao", REG, 5, { GPIOAO_5 }, 1 }, 497 { "clk_32k_in_out", REG, 18, { GPIOAO_6 }, 1 }, 498 { "remote_input", REG, 0, { GPIOAO_7 }, 1 }, 499 { "hdmi_cec_1", REG, 17, { GPIOAO_12 }, 1 }, 500 { "ir_blaster", REG, 31, { GPIOAO_13 }, 1 }, 501 { "pwm_c2", REG, 22, { GPIOAO_3 }, 1 }, 502 { "i2c_sck_ao", REG, 2, { GPIOAO_4 }, 1 }, 503 { "i2c_sda_ao", REG, 1, { GPIOAO_5 }, 1 }, 504 { "ir_remote_out", REG, 21, { GPIOAO_7 }, 1 }, 505 { "i2s_am_clk_out", REG, 30, { GPIOAO_8 }, 1 }, 506 { "i2s_ao_clk_out", REG, 29, { GPIOAO_9 }, 1 }, 507 { "i2s_lr_clk_out", REG, 28, { GPIOAO_10 }, 1 }, 508 { "i2s_out_01", REG, 27, { GPIOAO_11 }, 1 }, 509 { "uart_tx_ao_b0", REG, 26, { GPIOAO_0 }, 1 }, 510 { "uart_rx_ao_b0", REG, 25, { GPIOAO_1 }, 1 }, 511 { "uart_cts_ao_b", REG, 8, { GPIOAO_2 }, 1 }, 512 { "uart_rts_ao_b", REG, 7, { GPIOAO_3 }, 1 }, 513 { "uart_tx_ao_b1", REG, 24, { GPIOAO_4 }, 1 }, 514 { "uart_rx_ao_b1", REG, 23, { GPIOAO_5 }, 1 }, 515 { "spdif_out_1", REG, 16, { GPIOAO_6 }, 1 }, 516 { "i2s_in_ch01", REG, 13, { GPIOAO_6 }, 1 }, 517 { "i2s_ao_clk_in", REG, 15, { GPIOAO_9 }, 1 }, 518 { "i2s_lr_clk_in", REG, 14, { GPIOAO_10 }, 1 }, 519 }; 520 521 const struct meson_pinctrl_config meson8b_cbus_pinctrl_config = { 522 .name = "Meson8b CBUS GPIO", 523 .groups = meson8b_cbus_groups, 524 .ngroups = __arraycount(meson8b_cbus_groups), 525 .gpios = meson8b_cbus_gpios, 526 .ngpios = __arraycount(meson8b_cbus_gpios), 527 }; 528 529 const struct meson_pinctrl_config meson8b_aobus_pinctrl_config = { 530 .name = "Meson8b AO GPIO", 531 .groups = meson8b_aobus_groups, 532 .ngroups = __arraycount(meson8b_aobus_groups), 533 .gpios = meson8b_aobus_gpios, 534 .ngpios = __arraycount(meson8b_aobus_gpios), 535 }; 536
Indexes created Sun Sep 21 19:09:51 GMT 2025